CN104484304A - RS422 communication control circuit adopting double FPGAs (field programmable gate array) as core - Google Patents
RS422 communication control circuit adopting double FPGAs (field programmable gate array) as core Download PDFInfo
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- CN104484304A CN104484304A CN201410756223.0A CN201410756223A CN104484304A CN 104484304 A CN104484304 A CN 104484304A CN 201410756223 A CN201410756223 A CN 201410756223A CN 104484304 A CN104484304 A CN 104484304A
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- fpga2
- relay assembly
- protocol chip
- auxiliary contact
- fpga1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention provides an RS422 communication control circuit adopting double FPGAs (field programmable gate array) as a core. The RS422 communication control circuit comprises a communication interface circuit, a relay assembly I, a relay assembly II, an RS422 protocol chip I, an RS422 protocol chip II, an FPGA I and an FPGA II. The RS422 communication control circuit disclosed by the invention is in data communication with external equipment by an RS422 communication chip and a communication interface circuit; a memory is used for memorizing real-time working information of the FPGAs; a crystal oscillator is used for providing a clock signal to the FPGAs; relays are used for switching a transmitting access and a drive access; by adopting the cooperative work mode of double FPGAs, the RS422 communication control circuit can be used for detecting mutual data work states of the double FPGAs in real time and realizing the work of the double FPGAs and improving the reliability of work as well.
Description
Technical field
The invention belongs to electronic circuit control applied technical field, being specifically related to a kind of double FPGA that adopts is the RS422 communication control circuit of core.
Background technology
In Electronic Control application technology, adopt FPGA as control core and the external unit of Circuits System carry out RS422 communicate time, by receiving external command frame, decision instruction frame thus make FPGA output level drive corresponding application circuit work, feedback frame is sent it back external unit, external unit can according to the duty of the command frame Real-Time Monitoring circuit of feedback simultaneously.This kind of circuit working mode is widely applied in electron controls technology.The mode realizing this application is at present broadly divided into:
1, independent FPGA is adopted to receive and dispatch instruction as core;
2, adopt double FPGA as core accepts instruction, monolithic FPGA sends instruction;
Adopt the 1st kind of mode circuit reliability not high, adopt the 2nd kind of mode improve the reliability of reception instruction but the instruction sent can be caused to occur extremely due to the factor such as sequential, level match because double FPGA sends instruction simultaneously.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of double FPGA that adopts is the RS422 communication control circuit of core, this employing double FPGA is that the RS422 communication control circuit of core is by the co-ordination mode between FPGA1 and FPGA2, ensure when appearance wherein one piece of FPGA operation irregularity time, another block FPGA can start transmission instruction works, solves circuit reliability instruction that is not high and that send and occurs abnormal problem.
The present invention is achieved by the following technical programs.
A kind of double FPGA that adopts provided by the invention is the RS422 communication control circuit of core, comprises communication interface circuit, relay assembly 1, relay assembly 2, RS422 protocol chip 1, RS422 protocol chip 2, FPGA1 and FPGA2; Described RS422 protocol chip 1 is all connected with the signal output part of external unit by communication interface circuit with the reception data terminal of RS422 protocol chip 2; The transmission data terminal of described RS422 protocol chip 1 is connected with one end of auxiliary contact K1, K2 of relay assembly 1, and the other end of auxiliary contact K1, K2 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit; The transmission data terminal of described RS422 protocol chip 2 is connected with one end of auxiliary contact K3, K4 of relay assembly 1, and the other end of auxiliary contact K3, K4 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit;
Described FPGA1 with FPGA2 is connected with RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the serial data bus of correspondence; Described FPGA1 with FPGA2 is connected with the feedback signal input terminal of RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the feedback data output terminal of correspondence, is connected between described FPGA1 and FPGA2 by 8 bit data bus;
Described FPGA1 is connected with one end of the auxiliary contact K5 of relay assembly 2 by drive wire 1, and the other end of described auxiliary contact K5 is connected with application circuit; Described FPGA2 is connected with one end of the auxiliary contact K6 of relay assembly 2 by drive wire 2, and the other end of described auxiliary contact K6 is connected with application circuit;
Described FPGA2 is connected with the signal input part of control line 2 with relay assembly 1, relay assembly 2 by control line 1.
Also comprise monitoring line, the input end of described monitoring line is connected with the feedback data output terminal of FPGA1, and output terminal is connected with the monitor signal input end of FPGA2.
Described FPGA1 is also connected with storer 1 and crystal oscillator 1.
Described FPGA2 is also connected with storer 2 and crystal oscillator 2.
Beneficial effect of the present invention is: carry out data communication by RS422 communication chip and communication interface circuit and external unit, storer is used for storing FPGA real-time working information, crystal oscillator is used for providing clock signal to FPGA, and relay is used for sendaisle and drives passage to switch; Have employed the mode of the mutual collaborative work of double FPGA, detect mutual datamation in real time dynamic, while achieving double FPGA work, improve the reliability of work.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present invention;
Fig. 2 is the software flow pattern of FPGA1 in Fig. 1;
Fig. 3 is the software flow pattern of FPGA2 in Fig. 1.
Embodiment
Further describe technical scheme of the present invention below, but described in claimed scope is not limited to.
As shown in Figure 1 a kind of adopts double FPGA to be the RS422 communication control circuit of core, comprises communication interface circuit, relay assembly 1, relay assembly 2, RS422 protocol chip 1, RS422 protocol chip 2, FPGA1 and FPGA2; Described RS422 protocol chip 1 is all connected with the signal output part of external unit by communication interface circuit with the reception data terminal of RS422 protocol chip 2; The transmission data terminal of described RS422 protocol chip 1 is connected with one end of auxiliary contact K1, K2 of relay assembly 1, and the other end of auxiliary contact K1, K2 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit; The transmission data terminal of described RS422 protocol chip 2 is connected with one end of auxiliary contact K3, K4 of relay assembly 1, and the other end of auxiliary contact K3, K4 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit;
Described FPGA1 with FPGA2 is connected with RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the serial data bus of correspondence; Described FPGA1 with FPGA2 is connected with the feedback signal input terminal of RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the feedback data output terminal of correspondence, is connected between described FPGA1 and FPGA2 by 8 bit data bus;
Described FPGA1 is connected with one end of the auxiliary contact K5 of relay assembly 2 by drive wire 1, and the other end of described auxiliary contact K5 is connected with application circuit; Described FPGA2 is connected with one end of the auxiliary contact K6 of relay assembly 2 by drive wire 2, and the other end of described auxiliary contact K6 is connected with application circuit;
Described FPGA2 is connected with the signal input part of control line 2 with relay assembly 1, relay assembly 2 by control line 1.
Also comprise monitoring line, the input end of described monitoring line is connected with the feedback data output terminal of FPGA1, and output terminal is connected with the monitor signal input end of FPGA2.
Described FPGA1 is also connected with storer 1 and crystal oscillator 1.
Described FPGA2 is also connected with storer 2 and crystal oscillator 2.
The present invention is in practical work process, external unit sends command frame to communication interface circuit, RS422 communication protocol chip 1 is by receiving data terminal RXD1+, RXD1-, RS422 communication protocol chip 2 is by receiving data terminal RXD2+, RXD2-receives instruction, then afterwards the differential signal line of RS422 communication protocol chip 1 and RS422 communication protocol chip 2 is turned and be changed to universal serial bus RXD1 and RXD2 respectively, FPGA1 and FPGA2 receives data respectively by universal serial bus RXD1 and RXD2, FPGA1 can send to FPGA2 according to the command frame received by 8 bit data bus, FPGA2 carries out contrast according to the data that the command frame received and FPGA1 send over and judges, when decision instruction frame is identical, FPGA2 drives the auxiliary contact K5 of relay assembly 2 to close by control line 2, auxiliary contact K6 disconnects, FPGA1 drive wire 1 output level drives application circuit.When FPGA2 decision instruction frame is different, FPGA2 drives the auxiliary contact K6 of relay group 2 to close by control line 2, and auxiliary contact K5 disconnects, and FPGA2 drive wire 2 output level drives application circuit.
When FPGA1 passes through feedback data output terminal TXD1 to RS422 communication protocol chip 1 feedback command, FPGA2 receives the feedback command of FPGA1 by monitoring line simultaneously, FPGA2 can judge whether instruction is now the correct instruction needing feedback, when instruction is correct, FPGA2 drives auxiliary contact K1, K2 of relay assembly 1 closed by control line 1, auxiliary contact K3, K4 disconnect, and command frame is fed back to external unit by FPGA1; When instruction errors, FPGA2 is closed by auxiliary contact K3, K4 of control line 1 starting relay combination 1, and auxiliary contact K1, K2 disconnect, and command frame is fed back to external unit by FPGA2.
The software flow pattern of FPGA1 as shown in Figure 2, the Frame that FPGA1 is sent by RXD1 serial data bus reception external unit, receive mode is for receive frame head, address field, command word, status word, check word and postamble successively, the validity that first FPGA1 judges frame head receiver address territory, command word and status word successively again, when reception judges check word and postamble is invalid, FPGA1 can return initial receive state until reception one frame is effective.Receive the effectively rear FPGA1 of a frame and can close receive interruption, by exporting the frame state that 8 BITBUS network data tell FPGA2 to receive, then output level drives application circuit, finally return former Frame to external unit, notice external unit has effectively received and has performed Frame instruction, waits for external unit next instruction frame.
The software flow pattern of FPGA2 as shown in Figure 3, similar with FPGA1 software flow, first FPGA2 receives the Frame that sends of external unit by RXD2 serial data bus, then contrast with the data sent by 8 bit data bus from FPGA1, when Data Comparison is different, FPGA2 drives the auxiliary contact K5 in relay group 2 to disconnect by control line 2, and auxiliary contact K6 closes, and drives application circuit by FPGA2 output level; When Data Comparison is identical, FPGA2 drives the auxiliary contact K5 in relay group 2 to close by control line 2, and auxiliary contact K6 disconnects.Now, FPGA2 feeds back to the command frame of external unit by TXD1 by monitoring line monitoring FPGA1, if the command frame of monitoring feedback is correct, FPGA2 drives auxiliary contact K1, K2 in relay assembly 1 closed by control line 1, and auxiliary contact K3, K4 disconnect; Otherwise if the command frame mistake of monitoring feedback, FPGA2 then drives auxiliary contact K1, K2 in relay assembly 1 to disconnect by control line 1, and auxiliary contact K3, K4 are closed, by TXD2, command frame are fed back to external unit by FPGA2.
Claims (4)
1. one kind adopts double FPGA to be the RS422 communication control circuit of core, comprise communication interface circuit, relay assembly 1, relay assembly 2, RS422 protocol chip 1, RS422 protocol chip 2, FPGA1 and FPGA2, it is characterized in that: described RS422 protocol chip 1 is all connected with the signal output part of external unit by communication interface circuit with the reception data terminal of RS422 protocol chip 2; The transmission data terminal of described RS422 protocol chip 1 is connected with one end of auxiliary contact K1, K2 of relay assembly 1, and the other end of auxiliary contact K1, K2 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit; The transmission data terminal of described RS422 protocol chip 2 is connected with one end of auxiliary contact K3, K4 of relay assembly 1, and the other end of auxiliary contact K3, K4 of described relay assembly 1 is all connected with the signal input part of external unit by communication interface circuit;
Described FPGA1 with FPGA2 is connected with RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the serial data bus of correspondence; Described FPGA1 with FPGA2 is connected with the feedback signal input terminal of RS422 protocol chip 1 and RS422 protocol chip 2 respectively by the feedback data output terminal of correspondence, is connected between described FPGA1 and FPGA2 by 8 bit data bus;
Described FPGA1 is connected with one end of the auxiliary contact K5 of relay assembly 2 by drive wire 1, and the other end of described auxiliary contact K5 is connected with application circuit; Described FPGA2 is connected with one end of the auxiliary contact K6 of relay assembly 2 by drive wire 2, and the other end of described auxiliary contact K6 is connected with application circuit;
Described FPGA2 is connected with the signal input part of control line 2 with relay assembly 1, relay assembly 2 by control line 1.
2. employing double FPGA as claimed in claim 1 is the RS422 communication control circuit of core, it is characterized in that: also comprise monitoring line, the input end of described monitoring line is connected with the feedback data output terminal of FPGA1, and output terminal is connected with the monitor signal input end of FPGA2.
3. employing double FPGA as claimed in claim 1 is the RS422 communication control circuit of core, it is characterized in that: described FPGA1 is also connected with storer 1 and crystal oscillator 1.
4. employing double FPGA as claimed in claim 1 is the RS422 communication control circuit of core, it is characterized in that: described FPGA2 is also connected with storer 2 and crystal oscillator 2.
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| CN201410756223.0A CN104484304B (en) | 2014-12-10 | 2014-12-10 | A kind of RS422 communication control circuits for using double FPGA for core |
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| CN201410756223.0A CN104484304B (en) | 2014-12-10 | 2014-12-10 | A kind of RS422 communication control circuits for using double FPGA for core |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114615104A (en) * | 2022-03-14 | 2022-06-10 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system realized based on domestic FPGA |
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| US7086025B1 (en) * | 2003-10-23 | 2006-08-01 | Adaptec, Inc. | Programmable logic device partitioning method for application specific integrated circuit prototyping |
| CN201465562U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | Two-channel digital radiofrequency storage board |
| CN103020005A (en) * | 2012-12-19 | 2013-04-03 | 北京康拓科技有限公司 | Method and device for data communication and comparison of high-reliability system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7086025B1 (en) * | 2003-10-23 | 2006-08-01 | Adaptec, Inc. | Programmable logic device partitioning method for application specific integrated circuit prototyping |
| CN201465562U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | Two-channel digital radiofrequency storage board |
| CN103020005A (en) * | 2012-12-19 | 2013-04-03 | 北京康拓科技有限公司 | Method and device for data communication and comparison of high-reliability system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114615104A (en) * | 2022-03-14 | 2022-06-10 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system realized based on domestic FPGA |
| CN114615104B (en) * | 2022-03-14 | 2023-11-28 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system based on domestic FPGA |
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