CN104465609A - Packaging structure and packaging method for copper-core ball PoP interconnection - Google Patents

Packaging structure and packaging method for copper-core ball PoP interconnection Download PDF

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Publication number
CN104465609A
CN104465609A CN201410756179.3A CN201410756179A CN104465609A CN 104465609 A CN104465609 A CN 104465609A CN 201410756179 A CN201410756179 A CN 201410756179A CN 104465609 A CN104465609 A CN 104465609A
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China
Prior art keywords
copper
packaging
encapsulation unit
caryosphere
pop
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CN201410756179.3A
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Inventor
陈南南
王宏杰
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN201410756179.3A priority Critical patent/CN104465609A/en
Publication of CN104465609A publication Critical patent/CN104465609A/en
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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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Abstract

The invention relates to a packaging structure and a packaging method for copper-core ball PoP interconnection. The packaging structure comprises a first packaging unit located on an upper layer and one or more second packaging units. The first packaging unit and the second packaging units are sequentially stacked. The first packaging unit is connected with the second packaging units through welding balls, and the adjacent second packaging units are connected through welding balls. The packaging structure and the packaging method are characterized in that the welding balls comprise copper-core balls and plating brazing filler metal covering the surfaces of the copper-core balls in a plating mode. The copper-core balls are of a central symmetric structure or an axial symmetric structure. The copper-core balls are in a ball shape or a cylinder shape or a rectangular pillar shape or an ellipsoid shape. The first packaging unit is of a fan-out type wafer-level packaging structure. The second packaging units are of a flip-chip packaging structure or a lead bonding packaging structure. The second packaging units are connected with the welding balls of the second packaging unit or the first packaging unit on the upper layer. The packaging structure and the packaging method can effectively relieve the phenomenon of collapsing of PoP stacked chips, the technology is simplified, and cost is reduced.

Description

The encapsulating structure that copper caryosphere PoP interconnects and method for packing
Technical field
The present invention relates to encapsulating structure and the method for packing of a kind of copper caryosphere PoP interconnection, belong to technical field of semiconductor encapsulation.
Background technology
As encapsulating highly dense integrated major way at present, PoP(package on package, laminate packaging) more and more paid attention to.Chip stacking be improve Electronic Packaging high densification main path between, PoP design in the industry cycle obtains development and application more widely.
In prior art, adopt the PoP solution of tin ball interconnection, there is certain difficulty and deficiency caving in, in displacement (shift) etc., need cutting, boring etc. to carry out two-layer tin ball stacking, complex process, cost are higher simultaneously.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the encapsulating structure providing a kind of copper caryosphere PoP to interconnect and method for packing, more effectively improve the phenomenon of caving in of PoP stacked die, Simplified flowsheet, reduces costs.
According to technical scheme provided by the invention, the encapsulating structure that described copper caryosphere PoP interconnects, comprise the first encapsulation unit and one or more second encapsulation unit that are positioned at upper strata, first encapsulation unit and the second encapsulation unit stack gradually, and are all connected by soldered ball between the first encapsulation unit and the second encapsulation unit and between the second adjacent encapsulation unit; It is characterized in that: described soldered ball comprises the coating solder of copper caryosphere and copper caryosphere coating surface.
In an embodiment, symmetrical structure or be Axisymmetric Spherical structure centered by described copper caryosphere.
In an embodiment, described copper caryosphere is spherical, cylindrical, rectangle cylindricality or elliposoidal.
In an embodiment, described first encapsulation unit is fan-out-type wafer level packaging structure.
In an embodiment, described second encapsulation unit adopts flip chip packaging structure or wire bond package structure.
In an embodiment, described second encapsulation unit is connected with second encapsulation unit on upper strata or the soldered ball of the first encapsulation unit.
The method for packing that described copper caryosphere PoP interconnects, it is characterized in that, adopt following methods: the first encapsulation unit and one or more second encapsulation unit are carried out stacking, backflow, second encapsulation unit is connected with second encapsulation unit on upper strata or the soldered ball of the first encapsulation unit, forms the encapsulating structure of copper caryosphere PoP interconnection; Described soldered ball comprises the coating solder of copper caryosphere and copper caryosphere coating surface.
In an embodiment, described first encapsulation unit is fan-out-type wafer level packaging structure
In an embodiment, described second encapsulation unit adopts flip chip packaging structure or wire bond package structure.
The encapsulating structure that copper caryosphere PoP of the present invention interconnects and method for packing, more effectively can improve the phenomenon of caving in of PoP stacked die than existing method, Simplified flowsheet, reduces costs; Meanwhile, in the upper and lower packaging interconnection of PoP, copper caryosphere plays good supporting role.
Accompanying drawing explanation
Fig. 1 a is the schematic diagram of described IC disk.
Fig. 1 b is the cutting schematic diagram of described IC disk.
Fig. 1 c is the schematic diagram after the cutting of described IC disk.
Fig. 2 is the schematic diagram making metal level on carrier disk.
Fig. 3 is the schematic diagram making through hole on the metal layer.
Fig. 4 is the schematic diagram of the via bottoms adhering chip at metal level.
Fig. 5 is by metal level, the schematic diagram of chip plastic packaging in capsulation material.
Fig. 6 is the schematic diagram removing carrier disk and adhesive-layer.
Fig. 7 is the schematic diagram obtaining the first dielectric layer.
Fig. 8 is the schematic diagram obtaining figure opening on the dielectric layer.
Fig. 9 is the schematic diagram obtaining again interconnection metal layer.
Figure 10 is the schematic diagram obtaining UBM layer.
Figure 11 a is the schematic diagram of the first embodiment of the first encapsulation unit.
Figure 11 b is the schematic diagram of the second embodiment of the first encapsulation unit.
Figure 11 c is the schematic diagram of the third embodiment of the first encapsulation unit.
Figure 11 d is the schematic diagram of the 4th kind of embodiment of the first encapsulation unit.
Figure 12 a is the schematic diagram of the first embodiment of the second encapsulation unit.
Figure 12 b is the schematic diagram of the second embodiment of the second encapsulation unit.
Figure 12 c is the schematic diagram of the third embodiment of the second encapsulation unit.
Figure 12 d is the schematic diagram of the 4th kind of embodiment of the second encapsulation unit.
Figure 13 is the schematic diagram of the first embodiment of PoP encapsulating structure of the present invention.
Figure 14 is the schematic diagram of the second embodiment of PoP encapsulating structure of the present invention.
Figure 15 is the schematic diagram of the third embodiment of PoP encapsulating structure of the present invention.
Figure 16 is the schematic diagram of the 4th kind of embodiment of PoP encapsulating structure of the present invention.
In figure, sequence number is: the first encapsulation unit 1, second encapsulation unit 1a, soldered ball 2, copper caryosphere 21, coating solder 22, capsulation material 3, chip 4, first metal electrode 5, second metal electrode 6, metal level 7, RDL layer 8, again wiring metal routing layer 9, UBM layer 10, figure opening 11, substrate 12, back side UBM layer 13, end underfill material and salient point layer 14, paster material layer 15, IC disk 100, carrier disk 200, adhesive-layer 300.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in FIG. 13 to 16: the encapsulating structure that described copper caryosphere PoP interconnects comprises the first encapsulation unit 1 and one or more second encapsulation unit 1a that are positioned at upper strata, first encapsulation unit 1 and the second encapsulation unit 1a stack gradually, and are all connected by soldered ball 2 between the first encapsulation unit 1 and the second encapsulation unit 1a and between the second adjacent encapsulation unit 1a; Described soldered ball 2 comprises the coating solder 22 of copper caryosphere 21 and copper caryosphere 21 coating surface, copper caryosphere 21 can strengthen the rigidity of chip stack structure, avoid, by caving in of causing of chip and skew that multilayer tin ball causes, the evenness of whole PoP stacked structure and alignment precision being well controlled; Symmetrical structure centered by described copper caryosphere 21, as spherical; Or be Axisymmetric Spherical structure, as cylindrical, rectangle cylindricality or elliposoidal etc., specifically carry out design modifying according to structural design and function application difference; After backflow, coating solder 22 can realize with the electricity of other chips interconnected; Meanwhile, such copper caryosphere mutual contact mode, can realize more multi-layered PoP encapsulation;
Described first encapsulation unit 1 is fan-out-type wafer level packaging structure (Fan out WLP), specific embodiment is as shown in Figure 11 a, Figure 11 b, Figure 11 c, Figure 11 d, comprise capsulation material 3, chip 4 is set in capsulation material 3, the first metal electrode 5 and the second metal electrode 6 is set in the front of chip 4; Metal level 7 is set in described capsulation material 3, RDL layer 8 is set in the front of capsulation material 3, wiring metal routing layer 9 is again set in RDL layer 8, then interconnection metal layer 9 is formed with the first metal electrode 5 and the second metal electrode 6 and is electrically connected; Described dielectric layer 8 is arranged on UBM layer 10, UBM layer 10 and soldered ball 2 is set;
Described second encapsulation unit 1a adopts flip chip packaging structure or wire bond package structure, and specific embodiment is as shown in Figure 12 a ~ Figure 12 d, and Figure 12 a, Figure 12 c are flip chip packaging structure, and Figure 12 b, Figure 12 d are wire bond package structure; Described second encapsulation unit 2 comprises substrate 12, adopts capsulation material 3 plastic package chip 4 on the substrate 12, arranges UBM layer 10, arrange back side UBM layer 13, UBM layer 10 arranges soldered ball 2 at the back side of substrate 12 in the front of substrate 12; Wherein, Figure 12 a, Figure 12 c chips 4 are arranged on the substrate 12 by end underfill material and salient point layer (under fill+bump) 14; Figure 12 b and Figure 12 d chips 4 are arranged on the substrate 12 by paster material layer (as elargol) 15;
The back side UBM layer 13 of described second encapsulation unit 1a is connected with the soldered ball 2 of the second encapsulation unit 1a on upper strata or the first encapsulation unit 1.
The method for packing that described copper caryosphere PoP interconnects, adopts following steps:
(1) as shown in Figure 1a, the IC disk 100 with chip electrode is got, by thinning for above-mentioned IC the disk 100 and chip 4(cutting into single as shown in Fig. 1 b, Fig. 1 c);
(2) as shown in Figure 2, prepare carrier disk 200, at the upper surface coating adhesive-layer 300 of carrier disk 200, and make metal level 7, metal level 7 adopts the methods such as sputtering, deposition or plating to make, or adopts the mode of pasting metal forming/sheet or metal otter board to make;
(3) as shown in Figure 3, the metal level 7 that step (2) obtains makes through hole, and shape is square or circular, and size is relevant to the size of chip 4, exposes the upper surface of carrier disk 200;
(4) as shown in Figure 4, in the via bottoms coating adhesive-layer of the metal level 7 that step (3) obtains, the face down of chip 4 is pasted on carrier disk 200;
(5) as shown in Figure 5, the metal level 7 in step (4), chip 4 are become an entirety by capsulation material 3 envelope;
(6) as shown in Figure 6, remove carrier disk 200 by methods such as thinning, etchings, adhesive-layer 300 is removed in cleaning, exposes the front of chip 4, spins upside down 180 degree, facing up of chip 4;
(7) as shown in Fig. 7 ~ Fig. 9, in the front surface coated dielectric layer 8 of the capsulation material 3 that step (6) obtains, dielectric layer 8 makes figure opening 11, make single or multiple lift wiring metal routing layer 9 again by the mode of plating, chemical plating or sputtering at figure opening 11 and dielectric layer 8 upper surface, then wiring metal routing layer 9 is for connecting the first metal electrode 5, second metal electrode 6 and UBM layer 10;
(8) as shown in Figure 10, in the upper surface coating dielectric layer of the routing layer of wiring metal again 9 that step (7) obtains, and UBM layer 10 is obtained by the method such as optical mask, etching;
(9) as shown in Figure 11 a, Figure 11 b, Figure 11 c, UBM layer 10 is planted ball backflow, obtains soldered ball 2;
(12) the first encapsulation unit 1 and the second encapsulation unit 1a are carried out stacking, backflow, form the encapsulating structure of copper caryosphere PoP interconnection;
As shown in figure 13, be that the second encapsulation unit 1a of first encapsulation unit 1 of Figure 11 a and Figure 12 a, Figure 12 b is carried out stacking;
As shown in figure 14, be that the second encapsulation unit 1a of first encapsulation unit 1 of Figure 11 d and Figure 12 a, Figure 12 b is carried out stacking;
As shown in figure 15, be undertaken stacking by the second encapsulation unit 1a of first encapsulation unit 1 of Figure 11 b and Figure 12 a, Figure 12 b, wherein, the copper caryosphere 21 in the first encapsulation unit 1 replaces with rectangle cylindricality;
As shown in figure 16, be that the second encapsulation unit 1a of first encapsulation unit 1 of Figure 11 c and Figure 12 c, Figure 12 d is carried out stacking.
The present invention is when PoP chip laminate interconnects, what adopt copper caryosphere plants ball technique, copper caryosphere strengthens the rigidity of chip stack structure, avoids, by caving in of causing of chip and skew that multilayer tin ball causes, the evenness of whole PoP stacked structure and alignment precision being well controlled; Meanwhile, such copper caryosphere mutual contact mode, can realize more multi-layered PoP encapsulation.

Claims (9)

1. the encapsulating structure of a copper caryosphere PoP interconnection, comprise the first encapsulation unit (1) and one or more second encapsulation unit (1a) that are positioned at upper strata, first encapsulation unit (1) and the second encapsulation unit (1a) stack gradually, and are all connected by soldered ball (2) between the first encapsulation unit (1) and the second encapsulation unit (1a) and between adjacent the second encapsulation unit (1a); It is characterized in that: described soldered ball (2) comprises the coating solder (22) of copper caryosphere (21) and copper caryosphere (21) coating surface.
2. the encapsulating structure that interconnects of copper caryosphere PoP as claimed in claim 1, is characterized in that: symmetrical structure or be Axisymmetric Spherical structure centered by described copper caryosphere (21).
3. the encapsulating structure that interconnects of copper caryosphere PoP as claimed in claim 2, is characterized in that: described copper caryosphere (21) is spherical, cylindrical, rectangle cylindricality or elliposoidal.
4. the encapsulating structure of copper caryosphere PoP interconnection as claimed in claim 1, is characterized in that: described first encapsulation unit (1) is fan-out-type wafer level packaging structure.
5. the encapsulating structure of copper caryosphere PoP interconnection as claimed in claim 1, is characterized in that: described second encapsulation unit (1a) adopts flip chip packaging structure or wire bond package structure.
6. the encapsulating structure of copper caryosphere PoP interconnection as claimed in claim 1, is characterized in that: described second encapsulation unit (1a) is connected with second encapsulation unit (1a) on upper strata or the soldered ball (2) of the first encapsulation unit (1).
7. the method for packing of a copper caryosphere PoP interconnection, it is characterized in that, adopt following methods: the first encapsulation unit (1) and one or more second encapsulation unit (1a) are carried out stacking, backflow, second encapsulation unit (1a) is connected with second encapsulation unit (1a) on upper strata or the soldered ball (2) of the first encapsulation unit (1), forms the encapsulating structure of copper caryosphere PoP interconnection; Described soldered ball (2) comprises the coating solder (22) of copper caryosphere (21) and copper caryosphere (21) coating surface.
8. the method for packing of copper caryosphere PoP interconnection as claimed in claim 7, is characterized in that: described first encapsulation unit (1) is fan-out-type wafer level packaging structure.
9. the method for packing of copper caryosphere PoP interconnection as claimed in claim 7, is characterized in that: described second encapsulation unit (1a) adopts flip chip packaging structure or wire bond package structure.
CN201410756179.3A 2014-12-10 2014-12-10 Packaging structure and packaging method for copper-core ball PoP interconnection Pending CN104465609A (en)

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