CN104465352B - The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process - Google Patents
The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process Download PDFInfo
- Publication number
- CN104465352B CN104465352B CN201410714842.3A CN201410714842A CN104465352B CN 104465352 B CN104465352 B CN 104465352B CN 201410714842 A CN201410714842 A CN 201410714842A CN 104465352 B CN104465352 B CN 104465352B
- Authority
- CN
- China
- Prior art keywords
- thickness
- etching
- polycrystalline silicon
- polysilicon gate
- bottom anti
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The invention discloses the methods for eliminating polycrystalline silicon residue in polycrystalline silicon etching process, are related to field of microelectronics.This method is：The thickness H1 of original bottom anti-reflection layer in polysilicon gate is measured using optics line width measuring instrument, and sets first time etch period；First time etching is carried out to polysilicon gate according to the first time etch period of setting, and obtains the thickness H2 of the first etching；According to the thickness H2 that the thickness H1 of original bottom anti-reflection layer and first is etched, it is monitored using process control system and second of etching is carried out to the polysilicon gate.The present invention measures polysilicon bottom anti-reflecting layer thickness before etching polysilicon gate, using optics line width measuring instrument；The thickness of bottom anti-reflection layer is directed to by process control system, using corresponding etch process parameters, constantly feedback modifiers etch period, performs etching polysilicon polysilicon gate, achieve the purpose that eliminate polycrystalline silicon residue in polycrystalline silicon etching process, improves the yield of product.
Description
Technical field
The present invention relates to field of microelectronics more particularly to a kind of methods for eliminating polycrystalline silicon residue.
Background technology
In 65 nanometers and technology below, workspace and shallow plough groove isolation area have certain difference in height, by
It is influenced in by the difference in height, under the conditions of identical photoetching, as shown in Figure 1, the polysilicon gate a light above substrate c
It carves bottom anti-reflective layer thickness and has institute's difference.Under conditions of identical etching is with cleaning, the thicker silicon of bottom anti-reflection layer
Piece etching polysilicon gate has certain polycrystalline silicon residue b, influences overall performance.
It is to eliminate polycrystalline silicon residue technological means used at present：In the process of etching polysilicon bottom anti-reflection layer
In, the case where spectral signal changes in etching process is observed, etching is determined according to the variation tendency of spectral signal in etching process
Time.But there are the problem of have：Spectral signal determines that etch period has certain error, when determining that bottom is anti-by spectral signal
Reflecting layer etching finishes, and actually some bottom anti-reflection layer, which does not etch also, finishes.
Chinese patent (CN 101442001B) discloses a kind of method of etching polysilicon gate, and this method includes completing
The step of polysilicon deposition, completes the step of the step of polysilicon photoetching and completion etching polysilicon；The method further includes clear
The step of washing chip back-side polysilicon, the step complete the process of cleaning chip back-side polysilicon.
The patent is by washing chip back-side polysilicon, to increase the tensile stress of chip, so as to effectively keep away
Exempt from the formation of grid foot, improve wafer property.But there is no solve the problems, such as polycrystalline silicon residue in polycrystalline silicon etching process.
Chinese patent (CN 100383931C) discloses a kind of polysilicon gate that can reduce particle generation in etching technics
Pole etching technics, includes the following steps：Stabilizing step 1, BT steps (hard mask etching step before BT steps (hard mask etching step)
Suddenly), stabilizing step 2, main quarter step 1, main quarter step 2, excessively quarter step 1 and mistake quarter step 2 before main quarter step.
The patent has taken into account etching effect and the aspect of Grain size controlling two, cut off or maintain according to different situations etc. from
Daughter can cut off plasma in BT steps (hard mask etching step) to the main transition for carving step, and in main quarter step to mistake
The transition for carving step and the end for crossing quarter step need to maintain the stabilization build-up of luminance of plasma.The invention can efficiently control
Pollution of the particle of production to silicon chip is reacted, to improve chip yield.But it is more in polycrystalline silicon etching process there is no solving
The problem of crystal silicon remnants.
Invention content
The present invention is to solve the problems, such as polycrystalline silicon residue in polycrystalline silicon etching process, and etching polysilicon work is eliminated to provide
The technical solution of the method for polycrystalline silicon residue in skill.
The method of polycrystalline silicon residue, includes the following steps in elimination polycrystalline silicon etching process of the present invention：
Step 1. measures the thickness H1 of original bottom anti-reflection layer in polysilicon gate using optics line width measuring instrument, and
Set first time etch period；
Step 2. carries out first time etching according to the first time etch period of setting to the polysilicon gate, and obtains the
The thickness H2 of one etching；
The thickness H2 that step 3. is etched according to the thickness H1 of original bottom anti-reflection layer and first controls system using processing procedure
System is monitored carries out second of etching to the polysilicon gate.
Preferably, it is monitored using process control system in step 3 and second of etching is carried out to the polysilicon gate
Detailed process be：
Step 31. process control system is obtained according to the thickness H2 etched of the thickness H1 of original bottom anti-reflection layer and first
Take second of etch period；
Step 32. carries out second to the polysilicon gate according to second of etch period and etches.
Preferably, the detailed process for second of etch period being obtained in step 31 is：
Secondary etch period Time is obtained according to formula (1)：
Time=(H1-H2)/ER (1)
Wherein, ER indicates bottom anti-reflection layer etch rate.
Beneficial effects of the present invention：
The present invention measures polysilicon bottom antireflection thickness before etching polysilicon gate, using optics line width measuring instrument
Degree；The thickness of bottom anti-reflection layer is directed to by process control system, using corresponding etch process parameters, constantly feedback modifiers
Etch period performs etching polysilicon polysilicon gate, has reached the mesh for eliminating polycrystalline silicon residue in polycrystalline silicon etching process
, improve the yield of product.
Description of the drawings
Fig. 1 is the structural schematic diagram of the polycrystalline silicon residue after existing etching polysilicon gate；
Fig. 2 is the method flow diagram of polycrystalline silicon residue in elimination polycrystalline silicon etching process of the present invention；
Fig. 3 is the schematic diagram measured bottom anti-reflection layer using optics line width measuring instrument；
Fig. 4 is the flow chart that second of etching is carried out to polysilicon gate；
Fig. 5 is the polysilicon gate schematic diagram to being obtained after etching polysilicon gate using the present invention；
In attached drawing：A. polysilicon gate；B. polycrystalline silicon residue；C substrates；D. photoresist；E. bottom anti-reflection layer；F. line width；
H1. original bottom anti-reflective layer thickness.
Specific implementation mode
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
As shown in Figures 2 to 4, the method that the present invention provides polycrystalline silicon residue in elimination polycrystalline silicon etching process, including under
State step：
Step 1. measures the thickness H1 of original bottom anti-reflection layer e in polysilicon gate a using optics line width measuring instrument
(as shown in Figure 3), and first time etch period is set, which is shorter than the quarter of polysilicon gate under normal circumstances
Lose the time；
Step 2. carries out first time etching according to the first time etch period of setting to polysilicon gate a, and obtains first
The thickness H2 of etching；
The thickness H2 that step 3. is etched according to the thickness H1 of original bottom anti-reflection layer e and first, is controlled using processing procedure
System is monitored carries out second of etching to polysilicon gate a, and detailed process is：
The thickness H2 that step 31. process control system is etched according to the thickness H1 of original bottom anti-reflection layer e and first
Obtain second of etch period Time：
Secondary etch period Time is obtained according to formula (1)：
Time=(H1-H2)/ER (1)
Wherein, ER indicates bottom anti-reflection layer etch rate；
Step 32. carries out second to polysilicon gate a according to second of etch period and etches, and realizes and is carved per a piece of silicon chip
Accurately control (different per a piece of etch period) of erosion time ensure that each region of every a piece of silicon chip without polycrystalline silicon residue b
(as shown in Figure 5).
Optics line width measuring instrument is used to measure the same of the line width f of polysilicon gate a top photoresist d in the present embodiment
When, in the same database, increase parameter to measure the thickness of polysilicon gate a photoetching bottom anti-reflection layers e, and using first
Into process control system, for the different bottom anti-reflective layer thickness of different silicon chips, different etch process parameters are used respectively,
It constantly feeds back, to eliminate the polycrystalline silicon residue b in polysilicon gate a etching technics.
The process control system that the above is mentioned has been widely used in the technique of etching polysilicon gate.It has strong
The function of big automatic adjustment polysilicon line width, can not only make up the difference of front layer lithographic line width, but also can overcome the disadvantages that etching
The difference of itself.The present invention applies to the etch period for correcting bottom anti-reflection layer by process control system.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (1)
1. the method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process, which is characterized in that include the following steps：
Step 1. measures the thickness H1 of original bottom anti-reflection layer in polysilicon gate using optics line width measuring instrument, and sets
First time etch period；
Step 2. carries out first time etching according to the first time etch period of setting to the polysilicon gate, and obtains for the first quarter
The thickness H2 of erosion；
Step 3. according to the thickness H1 of original bottom anti-reflection layer and first etch thickness H2, using process control system into
Row monitoring carries out second to the polysilicon gate and etches；
The detailed process that second of etching is carried out to the polysilicon gate is monitored in step 3 using process control system
For：
Step 31. process control system obtains the according to the thickness H2 that the thickness H1 of original bottom anti-reflection layer and first is etched
The secondarily etched time；
Step 32. carries out second to the polysilicon gate according to second of etch period and etches；
The detailed process that second of etch period is obtained in step 31 is：
Secondary etch period Time is obtained according to formula (1)：
Time=(H1-H2)/ER (1)
Wherein, ER indicates bottom anti-reflection layer etch rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410714842.3A CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410714842.3A CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465352A CN104465352A (en) | 2015-03-25 |
| CN104465352B true CN104465352B (en) | 2018-09-04 |
Family
ID=52911223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410714842.3A Active CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465352B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109559986A (en) * | 2018-12-03 | 2019-04-02 | 上海华力微电子有限公司 | A kind of method of active area electric leakage in improvement etching polysilicon gate |
| CN112133631B (en) * | 2020-09-25 | 2022-11-18 | 上海华力微电子有限公司 | Method for improving stability of grid etching morphology and etching equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160621A (en) * | 1999-09-30 | 2000-12-12 | Lam Research Corporation | Method and apparatus for in-situ monitoring of plasma etch and deposition processes using a pulsed broadband light source |
| CN1577786A (en) * | 2003-07-07 | 2005-02-09 | 应用材料有限公司 | Interferometric endpoint detection in a substrate etching process |
| CN1708837A (en) * | 2002-10-24 | 2005-12-14 | 朗姆研究公司 | Method and apparatus for detecting endpoint during plasma etching of thin films |
| CN1750237A (en) * | 2004-09-14 | 2006-03-22 | 东京毅力科创株式会社 | Etching method and apparatus |
| CN102881578A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for etching polycrystalline silicon gates |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635573B2 (en) * | 2001-10-29 | 2003-10-21 | Applied Materials, Inc | Method of detecting an endpoint during etching of a material within a recess |
-
2014
- 2014-11-28 CN CN201410714842.3A patent/CN104465352B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160621A (en) * | 1999-09-30 | 2000-12-12 | Lam Research Corporation | Method and apparatus for in-situ monitoring of plasma etch and deposition processes using a pulsed broadband light source |
| CN1708837A (en) * | 2002-10-24 | 2005-12-14 | 朗姆研究公司 | Method and apparatus for detecting endpoint during plasma etching of thin films |
| CN1577786A (en) * | 2003-07-07 | 2005-02-09 | 应用材料有限公司 | Interferometric endpoint detection in a substrate etching process |
| CN1750237A (en) * | 2004-09-14 | 2006-03-22 | 东京毅力科创株式会社 | Etching method and apparatus |
| CN102881578A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for etching polycrystalline silicon gates |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465352A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108054115B (en) | Polymer cleaning method for etching cavity | |
| CN104465352B (en) | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process | |
| KR20210024198A (en) | Three or more states to achieve high aspect ratio dielectric etch | |
| CN102931071A (en) | Method and device for patterning sapphire substrate | |
| CN103915330A (en) | Substrate etching method | |
| WO2012177017A3 (en) | Metal wire etchant liquid and method for manufacturing a liquid crystal display using the etchant | |
| CN107958838B (en) | Method for improving in-plane uniformity of integrated etching process according to radio frequency hours | |
| CN112436040A (en) | Simplified preparation method of anode of silicon-based Micro OLED Micro-display device and pixel definition layer | |
| CN105575762A (en) | Method for eliminating wafer surface defect in wet etching | |
| CN111261555A (en) | Semiconductor device recovery method | |
| CN104900752A (en) | Black silicon layer preparation method and black silicon PIN photoelectric detector preparation method | |
| CN105700076B (en) | A kind of lithographic method of optical waveguide shielded layer | |
| CN108321261A (en) | A kind of preparation method of graphical sapphire substrate | |
| CN101441407B (en) | Photolithography dimension ultra-specification correcting etching method | |
| CN100468698C (en) | Making method for semiconductor part | |
| CN105957792A (en) | Etching method of semiconductor structure | |
| CN104599943A (en) | Tantalum nitride reaction ion etching method | |
| CN104425240A (en) | Substrate etching method | |
| CN106444307B (en) | The photolithography method of flat side compensation alignment in a kind of manufacture for laser chip | |
| CN105097488A (en) | Silicon chip etching method | |
| CN106299031A (en) | A kind of microlayer model etching etching method of solar cell carrying silicon wafers | |
| CN102364700B (en) | Solar cell reactive ion etching (RIE) technology temperature compensation method | |
| TWI538986B (en) | Etching solution and method of surface roughening of silicon substrate | |
| CN105575797A (en) | Photoresist backflow preparation method capable of reducing inclination angle of medium on etched wafer | |
| CN103177955B (en) | A kind of manufacturing method thereof realizing peelable sidewall |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |