CN104425595B - Semiconductor device and its manufacture method - Google Patents
Semiconductor device and its manufacture method Download PDFInfo
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- CN104425595B CN104425595B CN201310368556.1A CN201310368556A CN104425595B CN 104425595 B CN104425595 B CN 104425595B CN 201310368556 A CN201310368556 A CN 201310368556A CN 104425595 B CN104425595 B CN 104425595B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000011159 matrix material Substances 0.000 claims abstract description 32
- 108091006146 Channels Proteins 0.000 description 119
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 230000012447 hatching Effects 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 230000005669 field effect Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 229910015900 BF3 Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a kind of semiconductor device and its manufacture method, wherein, described device includes a substrate, and it has an active region and the field plate region in active region and a matrix area, and wherein matrix area is located at one first side of field plate region.An at least channel grid structure is located in the substrate of matrix area.An at least source doping region is located in the substrate of matrix area, and wherein source doping region is around channel grid structure.One drain doping region is located in the substrate of one second side of field plate region, wherein the second side is relative to the first side, and wherein from the point of view of apparent direction on, the bearing of trend of the length for extending perpendicularly to drain doping region of the length of channel grid structure.
Description
Technical field
The invention relates to a kind of semiconductor device, filled specifically for a kind of semiconductor with channel grid is related to
Put and its manufacture method.
Background technology
High voltage device technology is applied to high voltage and high-power integrated circuit, and traditional power transistor is in order to reach height
Pressure-resistant and high current, the flowing of driving current develops into vertical direction by in-plane.Develop with channel grid at present
Mos field effect transistor (the metal oxide semiconductor field of (trench gate)
Effect transistor, MOSFET), conducting resistance can be effectively reduced, and with larger current disposal ability.
Fig. 1 is the floor map of the existing mos field effect transistor with channel grid.
The mos field effect transistor includes：Substrate 500, drain electrode (drain) doped region in substrate 500
510th, channel grid structure 520 and source electrode (source) doped region 530.Source doping region 530 is located at channel grid structure
520 both sides, and source doping region 530 is connected with each other with channel grid structure 520.Source doping region 530 and plough groove type grid
Pole structure 520 has equal length, and the depth of channel grid structure 520 is more than the depth of source doping region 530.Regarded from above
From the point of view of direction, the bearing of trend of the length of source doping region 530 and channel grid structure 520 is all parallel to drain doping region
The bearing of trend of 510 length.The driving current of the mos field effect transistor is from the court of drain doping region 510
To source doping region 530 and channel grid structure 520 direction flow, and along channel grid structure 520 side wall to
On flow to source doping region 530, therefore from the point of view of upper apparent direction, the grid of the mos field effect transistor leads to
Road width w is the length of channel grid structure 520.
Under fixed gate channels length, the size of driving current is directly proportional to above-mentioned gate channels width.If however,
Gate channels width increases, then can increase the length of channel grid structure 520, and then increase the size of semiconductor device.
Therefore, it is necessary to seek the semiconductor device with channel grid and its manufacture method of a kind of novelty, its energy
Enough solve the problems, such as or improve above-mentioned.
The content of the invention
A kind of semiconductor device, including a substrate are the embodiment of the invention provides, it has an active region and positioned at actively
A field plate region and a matrix area in area, wherein matrix area are located at one first side of field plate region.An at least channel grid structure
In the substrate of matrix area.An at least source doping region is located in the substrate of matrix area, and wherein source doping region is around groove
Formula grid structure.One drain doping region is located in the substrate of one second side of field plate region, wherein the second side is relative to the first side, and
Wherein from the point of view of apparent direction on, the length for extending perpendicularly to drain doping region of the length of channel grid structure is prolonged
Stretch direction.
A kind of manufacture method of semiconductor device is the embodiment of the invention provides, including a substrate is provided, it has a master
Dynamic area and the field plate region in active region and a matrix area, wherein matrix area are located at one first side of field plate region.In matrix
An at least channel grid structure and an at least source doping region are formed in the substrate in area, wherein source doping region is around plough groove type
Grid structure.A drain doping region is formed in the substrate of one second side of field plate region, wherein the second side is relative to the first side, and
Wherein from the point of view of apparent direction on, the length for extending perpendicularly to drain doping region of the length of channel grid structure is prolonged
Stretch direction.
The semiconductor device and its manufacture method of the embodiment of the present invention have advantages below：When the length of channel grid structure
The bearing of trend of degree is essentially perpendicular to the bearing of trend of the length of drain doping region, and semiconductor device gate channels width
For the bottom surface of the strip cylinder of single channel grid structure 1/2 girth when, can be by increasing least a portion of device surface
Product, greatly improves the gate channels width of channel grid structure, and then lift driving current and improve conducting resistance；In addition,
Due to multiple channel grid structures of spaced-apart relation can be formed in semiconductor device, therefore can increase least a portion of
In the case of device area, further improve driving current and improve conducting resistance, and be effectively increased the use of device area
Efficiency；For further, channel grid structure according to embodiments of the present invention, can needed for identical driving current
Under, the size of reduction of gate structure and increase the service efficiency of device area, and then reduce the size of semiconductor device.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, not
Constitute limitation of the invention.In the accompanying drawings：
Fig. 1 is the floor map of the existing mos field effect transistor with channel grid.
Fig. 2A and Fig. 3 A are the floor map of the manufacture method of the semiconductor device according to the embodiment of the present invention.
Fig. 2 B are the generalized section along the hatching line 2B-2B ' in Fig. 2A.
Fig. 2 C are the generalized section along the hatching line 2C-2C ' in Fig. 2A.
Fig. 3 B are the generalized section along the hatching line 3B-3B ' in Fig. 3 A.
Fig. 3 C are the generalized section along the hatching line 3C-3C ' in Fig. 3 A.
Drawing reference numeral explanation：
10 active regions
20 field plate regions
30 matrix areas
50 driving currents
100th, 500 substrate
110 buried oxide layers
120 silicon layers
200th, 520 channel grid structure
210 grooves
220 dielectric layers
230 grid electrode layers
240 field oxides
250 field plate electrodes
300th, 530 source doping region
400th, 510 drain doping region
W, w gate channels width
Specific embodiment
Below explanation the embodiment of the present invention semiconductor device and its manufacture method making with use.However, can be easily
Understand the embodiment of the present invention many suitable inventive concepts are provided and wide variety of specific background is may be implemented in.Disclosed spy
Determine embodiment to be merely illustrative with ad hoc approach making and using the present invention, and be not used to limit to the scope of the present invention.Furthermore,
It is to make the same or analogous part that is denoted by the same reference numerals in the schema and description of the embodiment of the present invention.
Fig. 3 A to Fig. 3 C are below coordinated to illustrate the semiconductor device with channel grid of the embodiment of the present invention, wherein scheming
3A is the floor map of the semiconductor device with channel grid according to the embodiment of the present invention, and Fig. 3 B are along in Fig. 3 A
Hatching line 3B-3B ' generalized section, and Fig. 3 C are the generalized section along the hatching line 3C-3C ' in Fig. 3 A.
Semiconductor device with channel grid includes：One substrate 100, at least a channel grid structure 200, at least
One source doping region 300 and a drain doping region 400.Substrate 100 has an active region 10 and in active region 10 one
The matrix area 30 of field plate (field plate) area 20 and, wherein matrix area 30 are located at one first side of field plate region 20.In this implementation
In example, substrate 100 can be to include one in silicon-on-insulator (silicon on insulator, SOI) substrate, and substrate 100
Buried oxide layer (buried oxide, BOX) 110 and a silicon layer 120 thereon, as shown in Fig. 3 B and Fig. 3 C.In other implementations
Example in, substrate 100 can for monocrystal silicon substrate, extension (epitaxy) silicon base, silicon-Germanium base, compound semiconductor substrate or its
The semiconductor substrate that he commonly uses.In the present embodiment, the conduction type of substrate 100 is N-shaped, but is not limited to this.At other
In embodiment, the conduction type of substrate 100 is alternatively p-type, and can be needed to select its conduction type according to design.
At least a channel grid structure 200 is located in the substrate 100 of matrix area 30, and including a dielectric layer 220 and
Grid electrode layer 230.Dielectric layer 220 is conformally located in the groove 210 in substrate 100, and grid electrode layer 230 is located at
On dielectric layer 220, and groove 210 is filled up, as shown in Fig. 3 B and Fig. 3 C.Dielectric layer 220 may include oxide, nitride, nitrogen oxygen
Compound, its combination or other suitable grid dielectric materials.Grid electrode layer 230 may include silicon, polysilicon (poly
) or other conductive materials silicon.In the present embodiment, channel grid structure 200 is a strip cylinder, and strip
The bottom surface of cylinder has the profile of round rectangle, as shown in Figure 3A.In other embodiments, the length of channel grid structure 200
The bottom surface of strip cylinder can have oval, rectangle or polygonal profile (not illustrating).
Source doping region 300 is located in the substrate 100 of matrix area 30, and wherein source doping region 300 is around channel grid
Structure 200, as shown in Figure 3A.In the present embodiment, the conduction type of source doping region 300 is N-shaped, but is not limited to this.
In other embodiments, the conduction type of source doping region 300 is alternatively p-type, and can be needed to select its conductive-type according to design
Type, for example, source doping region 300 may include p-type dopant (for example, boron or boron fluoride) or n-type dopant (for example, phosphorus or
Arsenic).In the present embodiment, from the point of view of upper apparent direction, the edge of source doping region 300 and the edge of channel grid structure 200
With identical profile, as shown in Figure 3A.In other embodiments, the edge of source doping region 300 and channel grid structure
200 edge can have different profiles (not illustrating).
In one embodiment, the semiconductor device with channel grid may include multiple channel grid structures 200 and
Corresponding multiple source doping regions 300, and the spaced-apart relation of channel grid structure 200.For example, with plough groove type grid
The semiconductor device of pole includes two channel grid structures 200 of spaced-apart relation and corresponding two source doping regions
300, channel grid structure 200 can have identical profile each other, as shown in Figure 3A.In another embodiment, two grooves
Formula grid structure 200 can have different profiles (not illustrating) each other.In other embodiments, more than two channel grids
Can have the channel grid structure 200 of identical or different profile, and adjacent channel grid structure 200 in structure 200
Between can have identical or different spacing.It is understood that channel grid structure 200 and corresponding in Fig. 3 A to Fig. 3 C
The quantity and profile of source doping region 300 only illustrates as example, is not limited to this, channel grid structure 200 and correspondence
Source doping region 300 actual quantity and profile depend on design requirement.
Drain doping region 400 is located in the substrate 100 of one second side of field plate region 20, wherein the second side is relative to first
Side, i.e. drain doping region 400 are located at field respectively with the matrix area 30 with channel grid structure 200 and source doping region 300
The relative both sides in plate area 20.There is identical spacing between each channel grid structure 200 and drain doping region 400.At this
In embodiment, the conduction type of drain doping region 400 is p-type, but is not limited to this.In other embodiments, drain implants
The conduction type in area 400 is alternatively N-shaped, and can be needed to select its conduction type according to design, for example, drain doping region 400 can
Including p-type dopant (for example, boron or boron fluoride) or n-type dopant (for example, phosphorus or arsenic).In the present embodiment, on regarding side
Always see, the bearing of trend (that is, X-direction) of the length of channel grid structure 200 is essentially perpendicular to drain doping region 400
The bearing of trend (that is, Y-direction) of length, as shown in Figure 3A.
In the present embodiment, the semiconductor device with channel grid further includes a field oxide 240 (for example, silicon office
Portion aoxidizes (local oxidation of silicon, LOCOS) structure) and a field plate electrode 250.Field oxide 240
In in the substrate 100 in field plate region 20, and protrude from substrate 100, field plate electrode 250 is located on field oxide 240, and extend
To substrate 100, as shown in Fig. 3 A and Fig. 3 B.
The driving current 50 of the semiconductor device with channel grid passes through field oxide 240 from drain doping region 400
Lower section, and side wall along an at least channel grid structure 200 flows upwardly toward a corresponding at least source doping region 300 (such as
Shown in the arrow of Fig. 3 B).In the present embodiment, the gate channels width W of the semiconductor device with channel grid is groove
1/2 girth of the bottom surface of the strip cylinder of formula grid structure 200, as shown in Figure 3A.
The existing mos field effect transistor with channel grid only has a plough groove type grid
Pole structure 500, and the length of channel grid structure 500 bearing of trend parallel to the length of drain doping region 510 extension
Direction, as shown in Figure 1.This has the gate channels width w of the mos field effect transistor of channel grid
It is the length of channel grid structure 500, if increasing gate channels width w, can increases to equal proportion the face of semiconductor device
Product.
Compared to the existing mos field effect transistor with channel grid, the embodiment of the present invention
Semiconductor device there is the channel grid structure 200 that single channel grid structure 200 or multiple be spaced, and groove
The bearing of trend of the length of formula grid structure 200 is essentially perpendicular to the bearing of trend of the length of drain doping region 400, semiconductor
The gate channels width W of device is then 1/2 girth or multiple of the bottom surface of the strip cylinder of single channel grid structure 200
The summation of 1/2 girth of the bottom surface of the strip cylinder of channel grid structure 200.
It follows that compared to length bearing of trend parallel to drain doping region channel grid structure, in fixation
Device area under, the bearing of trend that channel grid structure is configured to its length is essentially perpendicular to the length of drain doping region
Multiple channel grid structures of spaced-apart relation can be formed during the bearing of trend of degree, in semiconductor device so that grid
Channel width increases the summation of 1/2 girth of the bottom surface of the strip cylinder for multiple channel grid structures, therefore can be effective
Ground lifts driving current using device surface product.
According to embodiments of the present invention, when the bearing of trend of the length of channel grid structure is essentially perpendicular to drain implants
The bearing of trend of the length in area, and semiconductor device gate channels width W be single channel grid structure strip post
During 1/2 girth of the bottom surface of body, the grid of channel grid structure can be greatly improved by increasing least a portion of device area
Channel width, and then lift driving current and improve conducting resistance.Further, since can be formed in semiconductor device being spaced
Multiple channel grid structures of arrangement, therefore can further improve and drive in the case where least a portion of device area is increased
Streaming current and improvement conducting resistance, and it is effectively increased the service efficiency of device area.For further, implemented according to the present invention
The channel grid structure of example, can be under driving current needed for identical, the size and increase device surface of reduction of gate structure
Long-pending service efficiency, and then reduce the size of semiconductor device.
Fig. 2A to Fig. 2 C and Fig. 3 A to Fig. 3 C is below coordinated to illustrate partly the leading with channel grid of the embodiment of the present invention
The manufacture method of body device, wherein Fig. 2A and Fig. 3 A are the semiconductor device with channel grid according to the embodiment of the present invention
Manufacture method floor map, and wherein Fig. 2 B are the generalized section along the hatching line 2B-2B ' in Fig. 2A, and Fig. 2 C are
Along the generalized section of the hatching line 2C-2C ' in Fig. 2A, Fig. 3 B are the generalized section along the hatching line 3B-3B ' in Fig. 3 A,
And Fig. 3 C are the generalized section along the hatching line 3C-3C ' in Fig. 3 A.
Refer to Fig. 2A to Fig. 2 C, there is provided a substrate 100, it has an active region 10 and one in active region 10
The matrix area 30 of plate area 20 and, wherein matrix area 30 are located at one first side of field plate region 20.In the present embodiment, substrate 100 can
It is to include a buried oxide layer 110 and a silicon layer 120 thereon in silicon-on-insulator substrate, and substrate 100, such as Fig. 2 B and figure
Shown in 3C.In other embodiments, substrate 100 can be monocrystal silicon substrate, extension silicon base, silicon-Germanium base, compound semiconductor
Substrate or other conventional semiconductor substrates.In the present embodiment, the conduction type of substrate 100 is N-shaped, but is not limited to
This.In other embodiments, the conduction type of substrate 100 is alternatively p-type, and can be needed to select its conduction type according to design.
The hard mask layer that by depositing operation and Lithography Etching technique, can on the substrate 100 form patterning (is not painted
Show), such as silicon nitride layer, to expose the substrate 100 of field plate region 20.Then, oxidation growing process is carried out, with field plate region 20
Substrate 100 in form field oxide 240 (for example, silicon local oxidation structure), and protrude from substrate 100.
Then, after removal hard mask layer, can be by depositing operation and Lithography Etching technique, shape on the substrate 100
Into another hard mask layer (not illustrating) of patterning, to expose the substrate 100 of the first side of field plate region 20.Then, carry out
Etch process is (for example, dry etching process, wet etching process, plasma etch process, reactive ion etch process or other are conventional
Etch process), field plate region 20 the first side (that is, matrix area 30) substrate 100 in formed an at least groove 210.Citing
For, two grooves 210 are formed in substrate 100.Then, after removal hard mask layer, can be by depositing operation (example
Such as, ald (atomic layer deposition, ALD) technique, chemical vapor deposition (chemical vapor
Deposition, CVD) technique, physical vapour deposition (PVD) (physical vapor deposition, PVD) technique, thermal oxide work
Skill or other suitable techniques), dielectric material is conformally deposited in each groove 210, to be correspondingly formed a dielectric layer
220, as gate dielectric.Dielectric layer 220 may include oxide, nitride, nitrogen oxides, its combination or other suitable grid
Pole dielectric material.
Then, can be by depositing operation (for example, physical gas-phase deposition, chemical vapor deposition method, ald
Technique, sputtering process or coating process), a conductive material is deposited on each dielectric layer 220, and corresponding groove 210 is filled up,
To form grid electrode layer 230, and then two channel grid structures 200, such as Fig. 2 B are formed in the substrate 100 of matrix area 30
And shown in Fig. 2 C.Grid electrode layer 230 may include silicon, polysilicon or other conductive materials.In addition, also can by depositing operation,
A field plate electrode 250 is formed on field oxide 240, and is extended on substrate 100, as shown in Figure 2 A and 2 B.
In the present embodiment, channel grid structure 200 is a strip cylinder, and the bottom surface of strip cylinder has circle
The profile of angular moment shape, as shown in Figure 2 A.In other embodiments, the bottom surface of the strip cylinder of channel grid structure 200 can
With oval, rectangle or polygonal profile (not illustrating).
In one embodiment, the semiconductor device with channel grid may include multiple plough groove types of spaced-apart relation
Grid structure 200.For example, the semiconductor device with channel grid includes two plough groove type grid of spaced-apart relation
Pole structure 200, and channel grid structure 200 can have identical profile each other, as shown in Figure 2 A.In another embodiment,
Two channel grid structures 200 can have different profiles (not illustrating) each other.In other embodiments, more than two ditches
Can have the channel grid structure 200 of identical or different profile, and adjacent channel grid in trench-gate structure 200
There can be identical or different spacing between structure 200.It is understood that channel grid structure 200 in Fig. 2A to Fig. 2 C
Quantity and profile only illustrate that be not limited to this, the actual quantity and profile of channel grid structure 200 depend on as example
In design requirement.
Fig. 3 A to Fig. 3 C are refer to, can be by doping process (for example, ion implantation technology), in the substrate of matrix area 30
Multiple source doping regions 300 are formed in 100, the correspondence of one of source doping region 300 is around a channel grid structure
200, as shown in Figure 3A.In the present embodiment, the conduction type of source doping region 300 is N-shaped, but is not limited to this.At it
In his embodiment, the conduction type of source doping region 300 is alternatively p-type, and can be needed to select its conduction type, example according to design
Such as, work is doped by p-type dopant (for example, boron or boron fluoride), n-type dopant (for example, phosphorus or arsenic) and/or its combination
Skill.In the present embodiment, from the point of view of upper apparent direction, the edge of source doping region 300 has with the edge of channel grid structure 200
There is identical profile, as shown in Figure 3A.In other embodiments, the edge of source doping region 300 and channel grid structure 200
Edge can have different profiles (not illustrating).
Can be formed in the substrate 100 of one second side of field plate region 20 by doping process (for example, ion implantation technology)
One drain doping region 400, wherein the second side is relative to the first side, i.e. drain doping region 400 and has channel grid structure 200
And the matrix area 30 of source doping region 300 is located at the relative both sides in field plate region 20 respectively.In the present embodiment, drain doping region
400 conduction type is p-type, but is not limited to this.In other embodiments, the conduction type of drain doping region 400 also may be used
It is N-shaped, and can be needed to select its conduction type according to design, for example, passes through p-type dopant (for example, boron or boron fluoride), N-shaped
Dopant (for example, phosphorus or arsenic) and/or its combination are doped technique.Each channel grid structure 200 and drain doping region
There is identical spacing between 400.In the present embodiment, from the point of view of upper apparent direction, the length of channel grid structure 200 is prolonged
The bearing of trend (that is, Y-direction) that direction (that is, X-direction) is essentially perpendicular to the length of drain doping region 400 is stretched, such as Fig. 3 A institutes
Show.
The driving current 50 of the semiconductor device with channel grid passes through field oxide 240 from drain doping region 400
Lower section, and side wall along an at least channel grid structure 200 flows upwardly toward a corresponding at least source doping region 300 (such as
Shown in the arrow of Fig. 3 B).In the present embodiment, the gate channels width W of the semiconductor device with channel grid is single
The strip post of 1/2 girth of the bottom surface of the strip cylinder of channel grid structure 200 or multiple channel grid structures 200
The summation of 1/2 girth of the bottom surface of body.
Compared to length bearing of trend parallel to drain doping region channel grid structure, in fixed device area
Under, the bearing of trend that channel grid structure is configured to its length is essentially perpendicular to the extension side of the length of drain doping region
Xiang Shi, can form multiple channel grid structures of spaced-apart relation in semiconductor device so that gate channels width increases
The summation of 1/2 girth of the bottom surface of the strip cylinder of multiple channel grid structures is added as, therefore device can be effectively utilized
Area, and then lift driving current.
According to embodiments of the present invention, when the bearing of trend of the length of channel grid structure is essentially perpendicular to drain implants
The bearing of trend of the length in area, and semiconductor device gate channels width W be single channel grid structure strip post
During 1/2 girth of the bottom surface of body, the grid of channel grid structure can be greatly improved by increasing least a portion of device area
Channel width, and then lift driving current and improve conducting resistance.Further, since can be formed in semiconductor device being spaced
Multiple channel grid structures of arrangement, therefore can further improve and drive in the case where least a portion of device area is increased
Streaming current and improvement conducting resistance, and it is effectively increased the service efficiency of device area.For further, implemented according to the present invention
The channel grid structure of example, can be under driving current needed for identical, the size and increase device surface of reduction of gate structure
Long-pending service efficiency, and then reduce the size of semiconductor device.
The semiconductor device and its manufacture method of the embodiment of the present invention can be applied to LDMOS
Transistor (laterally diffused metal oxide semiconductor, LDMOS), N-type channel insulation grid are double
Various low-voltages, the height such as polar transistor (N-channel insulated gate bipolar transistor, NIGBT)
The element of voltage and very high voltage.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when can change and combine above-mentioned various embodiments.
Claims (12)
1. a kind of semiconductor device, it is characterised in that including：
One substrate, wherein a field plate region and a matrix area with an active region and in the active region, described matrix area
Positioned at one first side of the field plate region；
An at least channel grid structure, in the substrate in described matrix area；
An at least source doping region, in the substrate in described matrix area, wherein an at least source doping region around
An at least channel grid structure；And
One drain doping region, in the substrate of one second side of the field plate region, wherein second side is relative to institute
The first side is stated, and wherein from the point of view of apparent direction on, the bearing of trend of at least length of a channel grid structure is vertical
In the bearing of trend of the length of the drain doping region.
2. semiconductor device according to claim 1, it is characterised in that an at least channel grid structure is a length
Strip cylinder, and a bottom surface of the cylinder has ellipse, round rectangle, rectangle or polygonal profile, and it is wherein described
An at least channel grid structure includes a grid electrode layer, and the gate channels width of the semiconductor device is the bottom surface
1/2 girth.
3. semiconductor device according to claim 1, it is characterised in that the semiconductor device includes multiple plough groove type grid
Pole structure and corresponding multiple source doping regions, and the channel grid structure spaced-apart relation.
4. semiconductor device according to claim 3, it is characterised in that have between the channel grid structure identical
Spacing, and between each channel grid structure and the drain doping region have identical spacing.
5. semiconductor device according to claim 3, it is characterised in that there is difference between the channel grid structure
Spacing, and between each channel grid structure and the drain doping region have identical spacing.
6. semiconductor device according to claim 1, it is characterised in that an at least channel grid structure includes：
One dielectric layer, at least groove in the substrate；And
One grid electrode layer, on the dielectric layer, and fills up an at least groove, and wherein described semiconductor device is more
Including：
One field oxide, in the field plate region；And
One field plate electrode, on the field oxide, and extends on the substrate in described matrix area.
7. a kind of manufacture method of semiconductor device, it is characterised in that including：
A substrate is provided, the substrate has an active region and the field plate region in the active region and a matrix area, its
Described in matrix area be located at the field plate region one first side；
At least a channel grid structure and at least a source doping region, wherein institute are formed in the substrate in described matrix area
An at least source doping region is stated around an at least channel grid structure；And
A drain doping region is formed in the substrate of one second side of the field plate region, wherein second side is relative to institute
The first side is stated, and wherein from the point of view of apparent direction on, the bearing of trend of at least length of a channel grid structure is vertical
In the bearing of trend of the length of the drain doping region.
8. the manufacture method of semiconductor device according to claim 7, it is characterised in that an at least channel grid
Structure is a strip cylinder, and a bottom surface of the cylinder has ellipse, round rectangle, rectangle or polygonal profile,
And a wherein described at least channel grid structure include a grid electrode layer, and the semiconductor device gate channels width
It is 1/2 girth of the bottom surface.
9. the manufacture method of semiconductor device according to claim 7, it is characterised in that the semiconductor device includes many
Individual channel grid structure and corresponding multiple source doping regions, and the channel grid structure spaced-apart relation.
10. the manufacture method of semiconductor device according to claim 9, it is characterised in that the channel grid structure
Between have between identical spacing, and each channel grid structure and the drain doping region have identical spacing.
The manufacture method of 11. semiconductor devices according to claim 9, it is characterised in that the channel grid structure
Between have between different spacing, and each channel grid structure and the drain doping region have identical spacing.
The manufacture method of 12. semiconductor devices according to claim 7, it is characterised in that an at least groove described in being formed
The step of formula grid structure, includes：
An at least groove is formed in the substrate of first side of the field plate region；
A dielectric layer is formed in an at least groove；And
A grid electrode layer is formed on the dielectric layer, to fill up an at least groove, and wherein described semiconductor device
Manufacture method further include：
A field oxide is formed in the field plate region；And
Form a field plate electrode on the field oxide, and extend on the substrate in described matrix area.
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