CN104425014B - List type NAND-type flash memory, flash memory device and its operating method - Google Patents

Abstract

List type NAND-type flash memory, flash memory device and its operating method, it is selected from 8 pin WSON, 24 pin FBGA, 8 pin SOIC and 16 pin SOIC, wherein at least some pressure points encapsulated are the active pressure point of a SPI interface；One NAND-type flash memory array, comprising in a package；Page buffer, comprising in a package and being coupled to NAND-type flash memory array；And control logic, comprising in a package and coupling NAND-type flash memory array and page buffer, instruction being read with corresponding one one data being provided, wherein data are exported to an at least pressure point for the active pressure point of SPI interface by page buffer from NAND-type flash memory array.By the program code map operation to memory, continuously read with enable without postponing.

Description

List type NAND-type flash memory, flash memory device and its operating method

Technical field

The present invention relates to a kind of digital memory device, and particularly with regard to special with entity attribute, reading instruction clock pulse Property and/or read the NAND-type flash memory of output characteristics, and above-mentioned characteristic is compatible with high-effect list type NOR-type flash memory.

Background technology

For general block form NOR-type flash memory, list type NOR-type flash memory becomes more favourable.List type NOR-type Flash memory, which provides several advantages, to be included：Less pressure point number, less encapsulation, better simply printed circuit board (PCB), low-power consumption, can match in excellence or beauty Efficiency and reduce device and system layer cost.Today, list type NOR-type flash memory provide 512- kilobits to 1- kilomegabits Density and the universal tandem perimeter interface (Serial Peripheral Interface, SPI) of use.

Identical element SPI (single-bit SPI) is used for transfer instruction, address and data entry/exit using four pressure points The list type flash memory, i.e.,：Chip selection (Chip select or/CS), clock pulse (Clock or CLK), data input (Data In Or DI), data output (Data Out or DO).More bit SPI (multi-bit SPI) include bifilar mode SPI (Dual SPI), four ray mode SPI (Quad SPI) and four line Peripheral Interfaces (Quad Peripheral Interface or QPI), make With four pressure points of identical, but configuration again, more sequence datas are changed with each clock cycle interior energy.Dual SPI press DI Point and DO pressure points are changed to two-way DIO (Input/Output) pressure point.DI pressure points and DO pressure points are changed into DIO by Quad SPI Pressure point, it is further added by two extra DIO pressure points, that is, a total of four DIO pressure points.When chip selection/CS and clock pulse CLK are examined During worry, then Quad SPI mono- share six pressure points.QPI is identical with Quad SPI, has four DIO pressure points, but even initially referring to It is allowed to perform complete four line (full quad, four DIO pressure points) operation under order.These more bit SPI and increased clock pulse speed With reference to caused change, list type NOR-type flash memory can be permitted by fast procedure code mapping (code-shadowing) extremely Random access memory (Random Access Memory, RAM), for example, referring to US Patent No.7,558, 900issued July 7,2009to Jigour et al.。

The execution of program code mapping techniques, as described below.It is all or part of non-volatile between system startup Data are transferred to system random access memory from the list type NOR-type flash memory.After system start-up, program code maps Also can dynamically perform, wherein, a less RAM can optionally pass through the portion of the larger list type NOR-type flash memory of dynamic mapping It is shared (time-shared) to be divided into the time.

Because how soon system start-up time can be mapped with direct relation with program code, the list type NOR-type The efficiency of flash memory is higher, and the speed that system starts is faster.In general, identical element SPI reading is instructed with initial address (starting address) is together issued, and then data are continuously withdrawn (clock out) until all required journeys Sequence code is transferred to random access memory.When using Quad SPI and frequency is in 104MHz, the list type NOR-type of today Flash memory can reach more than the continual command conversion ratio of 50,000,000 hytes/second (megabytes/second).Such should With, seem DTV, top box of digital machine, PC, DVD player, the network equipment and automatic display be all this should Demonstration, and these applications are indebted to the program code mapping techniques of high speed list type NOR-type flash memory.Using Special controlling device The list type NORSPI on basis is generally read into instruction design to hardware circuit (hard coded, hardcoded) so that start electric power When, all or part of data quickly can be read to RAM to be operated.For example, instruction 03hex Read are Typical hard coded.

Under 256 megabits or higher bit density, the close prices of list type NOR-type flash memory is even more than 512,000,000 The price of single-order memory cell (single level cell, SLC) NAND-type flash memory of position or higher bit density.SLC NAND The density of type flash memory is very big to the advantages of price, because SLC NAND note body techniques use less memory storage Dan Mi Degree so that for manufacturing price of the price of high density nand type flash memory much smaller than manufacture NOR-type flash memory.Unfortunately, typically Used SLC nand flash memories have structural, the characteristic of efficiency and bad block limitation (bad block limitation), The program code for making SLC NAND-type flash memories be difficult support high speed is mapped application by these characteristics.On the contrary, the program generation of high speed Code mapping techniques are well suited for NOR-type flash memory.

List type NOR-type flash memory allowing data can from a specific initial address (seeming address 0) of device by continuous and Taking-up sequentially, and without delay any time between data are removed (clock), it is not required that wait and confirm the device It is whether for ready for or busy (this situation is referred to as " preparation/busy inspection ", Ready/Busy check).On the contrary, NAND Type flash memory has relatively long every paging access time (access times per page), typically, per 2048+64 hytes point The tRD=25 μ S of page.Once the paging is accessed, the data are removed sequentially and quickly, for example, per hyte 25nS, but Paging next time will produce another tRD when accessing.Some NAND-type flash memories provide a cache (cache) and read characteristic, and are somebody's turn to do Cache reads characteristic and permitted when data are accessed from previous paging, and next paging can be accessed.However, this is operated Still need to confirm that the NAND-type flash memory is already prepared to be operated using Ready/Busy check, it will cause slower Program code mapping performance.

Although the NAND-type flash memory of today can preferably reach the reading conversion ratio of million hytes of 25-35/second, but on The reading conversion ratio stated also encodes (error correction code, ECC) program and bad block without by processing error correction Management (bad block management) was counted in the time.These action (error correction coding and defective-area management) will more enter One step reduces the conversion ratio of half, and therefore causes efficiency to be significantly lower than list type NOR-type flash memory.

Typically, each block has 64 pagings, the kilobit of 128 kilobit+4, and NAND-type flash memory allows the area of particular percentile Block (being typically 2%) is bad block and is unsuitable in applying.Typically, these bad blocks can be located at any position of memory array Put, these bad blocks of label so that these bad blocks can be identified and be not used.Some NAND-type flash memories ensure only first Area has been area.Therefore, standard sequentially and continuous program code mapping is insecure because next area for being accessed may It is bad.On the contrary, list type NOR-type flash memory provide exceed entirely can the 100% good memory of memory range of addressing deposit Storage unit.

The data sophistication (data integrity) of NOR-type flash memory is similarly better than NAND-type flash memory.It is in fact, outside Typically it is used together using ECC softwares or the ECC circuit for being made in chip (on-chip) with SLC NAND-type flash memories to determine Position and correcting unit member mistake, or in some instances, position and correct more bit mistake (multi-bit errors).Although can be than being arranged in pairs or groups with external ECC in execution with being made in NAND-type flash memory that ECC circuit in chip arranges in pairs or groups NAND-type flash memory comes fast, it is not intended that the μ s of every paging 100 occurred read delay also it is necessary it is taken into consideration in.

List type NOR-type flash memory can be used for the SPI interface of 4 to 6 active pressure points and can be used in small space effectively in encapsulation, Such as 8-constact WSON, 24-ball BGA, 8-pin and 16-pin SOIC.On the contrary, general run-in index (parallel) it is relatively large that the typically used as 14-22 actives pressure point of NAND-type flash memory, wherein 14-22 actives pressure point are included in one In 48-pin TSOP or 63-Ball BGA packages, and 48-pin TSOP or 63-Ball BGA package can consume up to sequence Twice of printed circuit board space of column NOR-type flash memory；For example, refer to SK Hynix Inc., 1Gbit (128M × 8bit/64M × 16bit) NAND Flash Memory, Rev.1.1, November2005；Micron Technology, Inc.,1Gb NAND Flash Memory,Rev.E,2006.General Sequences formula NAND-type flash memory is described together with SPI；Lift For example, it refer to, Micron Technology, Inc., Get More for Less in Your Embedded Designs with Serial NAND Flash,July 28,2009.However, these General Sequences formula NAND-type flash memories are intended to It is placed in larger encapsulation, such as 63-Ball BGA package, and these larger encapsulation have and the sudden strain of a muscle of General N AND type Deposit identical and perform structure, efficiency and bad block limitation.In addition, commercially, these list type NAND-type flash memories do not provide Instruction that can be compatible with list type NOR-type flash memory.For example, Winbond Electronics Corporation are refer to, W25Q64CV SpiFlash 3V64M-Bit Serial Flash Memory with Dual and Quad SPI, Revision F,May,2012；Winbond Electronics Corporation,W25Q128FV SpiFlash 3V 128M-Bit Serial Flash Memory with Dual/Quad SPI&QPI,Revision D,October 1, 2012。

Although list type NOR-type flash memory should be used to say that welcome solution method for program code mapping, Under higher density compared with NAND-type flash memory, the price of list type NOR-type flash memory is unwelcome.However, list type NAND Type flash memory as preceding introduction, have the shortcomings that to perform framework, efficiency and bad block limitation, and to involve its right for disadvantages mentioned above In it is high-effect sequentially and the mapping of continuous program code practicality, and can not provide compatible with list type NOR-type flash memory Instruction.

The content of the invention

The technical problem to be solved in the present invention is：A kind of list type NAND-type flash memory is provided, it is above-mentioned existing to improve or overcome There are one or more defects in technology.

One embodiment of the invention is that a kind of list type NAND-type flash memory includes：One encapsulation, is encapsulated from a 8-pin WSON, One 24-pin FBGA are encapsulated, and are selected in a colony of 8-pin SOIC encapsulation and 16-pin SOIC encapsulation compositions, its In the encapsulation at least some pressure points be a SPI interface active pressure point；One NAND-type flash memory array, included in the encapsulation In；One page buffer, included in the encapsulation and it is coupled to the NAND-type flash memory array；And a control logic, comprising In the encapsulation and the NAND-type flash memory array and the page buffer are coupled, reading instruction with corresponding one provides a data, Wherein the data are exported at least one pressure of the active pressure point of the SPI interface by the page buffer from the NAND-type flash memory Point.

Another embodiment of the present invention is that a kind of list type NAND-type flash memory device includes：One encapsulation, has 48 squares of millis Rice or less floor space and the active SPI interface with four to six pressure points；One NAND-type flash memory array, is contained in the envelope In dress；One page buffer, included in the encapsulation and couple the NAND-type flash memory array；And a control logic, comprising In the encapsulation and the NAND-type flash memory array and the page buffer are coupled, one provided with corresponding reading instruction is continuous Data, the wherein continuous data are provided to active SPI by the list type NAND-type flash memory device and connect by the page buffer An at least pressure point for mouth；Wherein the continuous data does not have to across paging border and the output of logically adjacent memory location Wait interval.

Another embodiment of the present invention is that a kind of NAND-type flash memory device includes：One interface；One NAND-type flash memory array；One Page buffer, couple the NAND-type flash memory array；One control logic, couple the NAND-type flash memory array and paging buffering Device, read instruction with corresponding one and one continuous data is provided, the wherein continuous data is dodged by the page buffer from the NAND Cryopreservation device is provided to the interface；Wherein the continuous data across paging border and logically adjacent memory location output and Without waiting for interval；And a startup power supply detector, when electric power is opened, the NAND-type flash memory array is initialized to the paging The load of the default paging of the one of buffer.

Another embodiment of the present invention includes for a kind of method for operating a NAND-type flash memory device：Receive one and read and refer to Corresponding high-effect list type quick flashing NOR (the high-performance serial flash NOR of order, the wherein reading instruction Or HPSF-NOR) read instruction and hold with pulse-phase at that time；And to command reception step should be read from the NAND-type flash memory Device provide a continuous data, wherein the continuous data across paging border and logically adjacent memory location output and Without waiting for interval.

Another embodiment of the present invention for a kind of operation with a NAND-type flash memory array and with the NAND-type flash memory battle array The method for showing a memory of a page buffer of pass, including：Select a paging of the NAND-type flash memory array；From this point The Fragmentation data selected in page buffer；ECC is performed to the data in the page buffer to calculate；From the paging Buffer exports the data；And repeat the paging selection, data storage, ECC calculating execution, and data output step and cause Data are across paging border and the output of logically adjacent memory location and without waiting for interval；Wherein, the paging selects Step, is initially included in the default paging of selection one in the NAND-type flash memory array, and rear selection NAND-type flash memory of including The continuous sequentially paging of array；Wherein, the paging selection, data storage and ECC calculating execution steps are initially at the flash memory and opened Performed automatically during dynamic power supply, then correspond to one and read instruction execution；And wherein, the data output step refers to that should read Order performs.

Another embodiment of the present invention includes for a kind of method for operating a NAND-type flash memory：Start in the NAND-type flash memory During power supply, a default paging of a NAND-type flash memory array of the NAND-type flash memory is selected；Start electricity in the NAND-type flash memory During source, the default Paged Memory storage data of the NAND-type flash memory array out of a page buffer；In the storing step Afterwards, ECC is performed to the data for being stored in the page buffer to calculate；Receive one and read instruction；And a continuous data is provided, it is right Command reception step should be read and provide the continuous data from the NAND-type flash memory device by the page buffer, wherein should Continuous data is across paging border and the output of logically adjacent memory location and without waiting for interval.

Another embodiment of the present invention for it is a kind of open with a NAND-type flash memory array type flash memory and with the NAND The method of the electric power of the relevant page buffer of type flash array, including：Set the type flash memory as a continuous read mode or It is a buffering read mode；Paging, which is preset, from the one of the NAND-type flash memory array shifts a paged data to the page buffer； The data of the default paging of the ECC processing in the page buffer, to provide the treated default paged datas of an ECC； After the data transfer step and the ECC processing steps, receive one and read instruction；And when the flash memory is in the continuous reading mould Formula, receive step to instruction should be read and export a continuous data from the flash memory, wherein the continuous data across paging border and Logically adjacent memory location is exported and treated without waiting for interval, and with the ECC in the page buffer Default paged data start together；And when the flash memory is in the buffering read mode, to should read command reception step from The flash memory exports a data, and the data are limited to the data in the page buffer.

Another embodiment of the present invention with a NAND-type flash memory array and couples the NAND-type flash memory for a kind of operation The method of one memory of one page buffer of array, including：Receive one continuously read instruction, including an instruction encoding and One initial address；And provide a continuous data, to should read command reception step and by the page buffer from this NAND-type flash memory device provides the continuous data, and the wherein continuous data is across paging border and logically adjacent memory Position export and without waiting for interval；Wherein, the offer step since the row 00 of the page buffer and with the initial address It is unrelated.

It follows that for list type NAND-type flash memory, what is desired is that maintaining it right in price under high density The advantage of list type NOR-type flash memory, the list type NAND-type flash memory can the compatible reading of receiving sequence formula NOR-type flash memory refer to Order, with the list type NOR controllers of appearance, and can be compatible and with can be dodged with list type NOR-type in encapsulation The execution framework to match in excellence or beauty and performance characteristics are deposited, and can continuously be read with enable by the program code map operation to memory Without postponing.

Brief description of the drawings

Fig. 1 is display timing diagram, to illustrate the instruction EBh of list type NOR-type flash memory.

Fig. 2 is display timing diagram, to illustrate the instruction EBh of the list type NAND-type flash memory under operator scheme.

Fig. 3 is display operational flowchart, list type NAND-type flash memory during illustrating startup power supply and in use.

Fig. 4 is the structural functionality block schematic diagram for showing NAND-type flash memory.

Fig. 5 is the program flow diagram for showing initiating sequence formula NAND-type flash memory.

Fig. 6 is the function block schematic diagram of display buffer function, and wherein the buffer has Data buffer and fast Take buffer, and the startup program wherein shown in Fig. 6 corresponding diagrams 5.

Fig. 7 is the operation sequence flow chart for showing the list type NAND-type flash memory under continuous read mode.

Fig. 8 is the functional block diagram of display buffer function, and wherein the buffer has Data buffer and cache temporary Storage, and the continuous read mode program wherein shown in Fig. 8 corresponding diagrams 7.

Main element label declaration

320~HPSF-NAND, 322~i/o controllers of memory

323~state buffer, 324~continual pages read address register

325~instruction registor, 326~address register

327~LUT, 328~mapping logics of buffer

329~address counter, 330~control logic

331~CPR bad block logic 332~CPR bad block buffers

333~high voltage generator, 334~column decoder

335~startup power supply, 336~row decoder of detector

338~page buffer, 40~NAND-type flash memory array

342~NAND Flash array user-can addressing region 344~unnecessary block areas

346~LUT information areas, 347~buffer mode indicates BUF

348~ECC-E sign 200,210,220 ..., 290 (1)~step

400th, 402 ..., 420~step 510~data/address bus

520~Error-Correcting Circuit, 530~cache buffer

540~Data buffer, 550~NAND Flash array

552~default paging, 554~paging

A, A1, A2, A3, B1, B2, B3~operation

Embodiment

Use high-effect sequence flash memory (the High-Performance-Serial Flash of NOR-type storage array technology NOR, HPSF-NOR) there are some reading characteristics so that and HPSF-NOR types memory can be particularly suitable for being mapped with program code The application (translation performs coding or data, such as parameter, word, image, audio signal etc.) of pass, and these are applied in electronics Device, for example, DTV, top box of digital machine, PC, DVD player, the network equipment show automatically and system in phase When universal.NOR-type flash array technology used in above-mentioned HPSF-NOR, such as it is Winbond Electronics Model W25Q64CV and W25Q128FV described by Corporation of San Jose, California, USA, and on Stating two kinds of models has respective tables of data, e.g. Winbond Electronics Corporation, W25Q64CV SpiFlash 3V 64M-Bit Serial Flash Memory with Dual and Quad SPI,Revision F,May 7,2012 and Winbond Electronics Corporation, W25Q128FV3V 128M-Bit Serial Flash Memory with Dual/Quad SPI&QPI,Revision D,October 1,2012.Illustrated in the lump in this described above Reference data.These read the continuous read action that characteristic is memory, and the continuous read action is referred to across paging Border is read out and logically neighbouring memory location is read out and without waiting for interval.In this use " across Undue page boundary is continuously read " read action of corresponding one reading command is referred to, refer to without any extra reading Make or in the address on paging border, wherein, read action is sequentially handled by memory.Refer in " the waiting interval " that this is used Be any (tRD), ECC processing, defective-area management, preparation/busy condition inspection or other any frameworks are read by paging to hold Postpone needed for row or caused by application and then cause at any interval of data output.In addition, entity space leads to Often it is of great rarity in electronic installation or system, and HPSF-NOR types memory also has some entity attributes, seems low pressure points Amount and small package size, HPSF-NOR types memory can be made particularly to be adapted to electronic installation and system.Use HPSF-NOR types The application Special controlling device of memory can be used for activation system and program code mapping application and be designed to refer to transmitting The ability of order, and above-mentioned instruction meets the instruction input demand of HPSF-NOR type memories, including read instruction clock requirement.Should One or more basic HPSF-NOR can be also designed with special memory controller to read in instruction to hardware circuit (hard coded), So that during startup power supply, all or part of data quickly can be read to RAM to be operated.Hard coded instruction can Including instruction Read command 03h and instruction Fast Read Command 0Bh, and may include it is any it is available it is more- Instruction (Multi-I/O Read command) is read in input/output.The hard coded initial address of controller is usually address 0, But also visual demand uses for other positions.

In described in this, the continuously reading that list type NAND-type flash memory may be designed as with memory is compatible, wherein continuous read Refer to that across paging border is read and logically neighbouring memory location is read, without waiting, but also can Reading with HPSF-NOR instructs compatible on clock pulse so that list type NAND-type flash memory can receive HPSF-NOR and read instruction And the controller with designing to HPSF-NOR type memories is arranged in pairs or groups and used.List type NAND-type flash memory with these compatibilities Can in this be referred to as high-effect list type NAND-type flash memory (high-performance serial flash NAND memory, HPSF-NAND).Because generally have extreme space using the device and system of HPSF-NOR types memory and controller to limit System, in order to more compatible, therefore HPSF-NAND also provides identical entity attribute, seem HPSF-NOR low pressure points and Small package size, or even in some cases, HPSF-NAND can have identical floor space (footprint) and and HPSF- NOR identicals export pressure point, and can be adapted to identical printed circuit board (PCB) without making any change to printed circuit board (PCB). HPSF-NAND enjoy relatively low cost per bit (cost per bit) with it is in its optimum density scope 512Mb or bigger In the range of have relatively low every consumption power.

HPSF-NAND types memory can be compatible with a variety of HPSF-NOR characteristic, including：(1) more-input/output SPI/ QPI interfaces (multi-I/O SPI/QPI interface)；(2) small and low pressure point quantity packing forms are (in density 256Mb Or under bigger density, such as 8x6mm), for example, 8-constact WSON, 16-pin SOIC and 24-ball BGA Deng encapsulation style, there is the elasticity using bigger encapsulation, e.g. VBGA-63 encapsulation, it is typically utilized in traditional parallel Formula and list type NAND-type flash memory；(3) high-frequency operation (being illustrated with 104MHz) and have high-conversion rate (illustrating with 50M/Sec)；(4) To fast procedure code mapping application for, across paging border continuously read and without waiting for interval；(5) it is adjacent in logic to determine The good memory of location by defective-area management, and defective-area management is to external system it will be evident that also will not to the speed of output and Continuity has negative effect；And the numerical value that (6) are specified according to user or supplier specifies determines zero output starting point Location, or other any addresses of the user-can be in addressing space in storage array.Advantageously, in the HPSF- described in this NAND can be used together with existing HPSF-NOR types store controller system, but its price can be with general NAND-type flash memory phase Match in excellence or beauty.

Table 1 provides a summary and compared, and is deposited for general parallel type SLC nand type memories, General Sequences formula NAND The various characteristics of reservoir and HPSF-NOR types memory and HPSF-NOR type memories compare.

The compatible list type quick flashing of clock pulse reads instruction

HPSF-NOR type storage arrangements, seem Winbond Electronics Corporation of San Jose, California, USA W25Q64CV and W25Q128FV models, a variety of SPI instructions can be supported, including a variety of read instructs. Some can support to the reading order illustrated by SPI mode, as shown in table 2.

Instruction Read 03h, which permit one or more set of data bits, sequentially to be read from page buffer 338.In table 2 Hyte 2, hyte 3 and hyte 4 include 24- bit address, for from the memory location read data bit group of addressing.In data Before can be used to, it is 32 that instruction Read 03h, which add clock pulse sum used in address,.After each set of data bits is moved out of, ground As long as location be automatically added next higher address and clock pulse be it is continuous if then allowing data continuous crossfire, pass through drive Dynamic/CS is high potential to complete to instruct Read 03h.Instruct FAST READ0Bh similar to instruction Read 03h, it can be more Operated under high specific frequency, be because after 24- bit address, contain 8 virtual clock pulses.Inside virtual clock pulse permitting apparatus The extra time of circuit is used for setting initial address.Before data can be used to, instruction FAST READ 0Bh are used plus addressing Clock pulse sum be 40.Instruct FAST READ DUAL OUTPUT 3Bh similar to instruction FAST READ 0Bh, except it Data are by two output pressure point IO0 and IO1 outputs, rather than a pressure point.Instruct FAST READ QUAD OUTPUT 6Bh is also similar to instruction FAST READ 0Bh, except its data is defeated by four output pressure points IO0, IO1, IO2 and IO3 Go out.Instruct FAST READ DUAL I/O BBh and instruction FAST READ QUAD I/O EBh and instruction FAST READ DUAL OUTPUT 3Bh and instruction FAST READ QUAD OUTPUT 6Bh are similar, but it is above-mentioned both have the ability each with every clock pulse two The mode of position or every clock pulse four carrys out input address position (Address bit, A23-A0).Instruct FAST READ DUAL I/O BBh and instruction FAST READ QUAD I/O EBh also include 8 mode bit M7-M0 after 24- bit address.

Table 3 lists the reading instruction of some explanations, and these read to instruct and are used for HPSF-NAND type memories, and with Reading instruction shown in table 2 for HPSF-NOR type memories mutually corresponds to and clock pulse is compatible, that is, is respectively used to HPSF-NAND The reading instruction of type memory and HPSF-NOR type memories has identical " address/virtual " cycle or clock pulse.

Comparison sheet 2 and table 3, virtual hyte are used to substitute address or pattern hyte, make the HPSF-NAND readings in table 3 Order is compatible with the HPSF-NOR reading order clock pulses of corresponding table 2.The HPSF-NAND reading orders of table 3 and corresponding table 2 HPSF-NOR reading orders perform identical read functions, as long as and if clock pulse is continuous, then allow identical data continuous Crossfire.And can so ensure when clock pulse input HPSF-NOR read instruction when, data according to HPSF-NOR identicals operation side Formula, it is continuously withdrawn from HPSF-NAND types memory and unrelated with the address that controller is provided.Its difference is in right For HPSF-NAND reading orders, read operation be since the Column 00 of any paging in storage buffer, it is but right For HPSF-NOR, read operation is the ad-hoc location A [23 from any array:0] start.

If desired, HPSF-NAND reads instruction and may specify that address and HPSF-NAND types memory can be from The row of address is specified to start to read.This one realize need in design it is many consider, it is including system clock (relatively slow), some The speed of built-in function, the built-in function such as ECC (relatively fast) and the license initial address in page buffer, thus Time enough can be provided to ensuing operation.The limitation that can be relaxed in design is read since Column 00 and is not had to Sacrifice use of the HPSF-NAND types memory in program code mapping.

For 256Mb or bigger memory density, standard SPI reads instruction and uses extra addressing hyte.Table 4 Some illustrative instructions are shown, corresponding reading order is shown for the HPSF-NOR type memories of big density, and table 5, HPSF-NAND type memories for big density.

Fig. 1 is the instruction FAST READ QUAD I/O timing diagrams for showing HPSF-NOR type memories, and Fig. 2 is display The instruction FAST READ QUAD I/O timing diagrams of HPSF-NAND type memories.More above-mentioned two figure, and two can be had a clear understanding of The clock pulse compatibility of person's instruction.Above two memory is interior all during eight clock pulses (CLK0-7) for the first time to receive instruction EBh. In a period of eight clock pulses (CLK 8-15) are passed through next time, pass through the pressure point IO of HPSF-NOR type memories₀、IO₁、IO₂And IO₃Receive 24- bit address.However, pressure point IO₀、IO₁、IO₂And IO₃State ignored by HPSF-NAND type memories.Above-mentioned two Kind memory corresponds to the virtual clock pulse of two virtual bit tuples in four clock pulses (CLK 16-19) next time.From clock pulse CLK 20 starts, by pressure point IO₀、IO₁、IO₂And IO₃Export continuous data.

Model selection

Although HPSF-NOR is continuously read since the Column 00 of the intrinsic paging in storage buffer, to program Code mapping operation is especially advantageous, however, want to read the row address beyond Column 00, can be by changing HPSF- Nand type memory continuously reads characteristic to reach above-mentioned expectation.In addition, operating in the demand of other patterns be able to can also be lifted, as It is the demand for pattern switching.Pattern switching may be alternatively used for switching a pattern, and the pattern is not supported across paging border Without the continuous reading needed to wait for.Another example is, when HPSF-NAND type memories are wanted to start electricity under HPSF patterns Source, RAM is mapped to program code, but then operate in other patterns for meeting NAND-type flash memory standard, such as Open NAND Flash Interface (ONFI) and in general list type NAND-type flash memory.Or HPSF-NAND type memories pass through it The preset value of his pattern starts, and can switch to continuous read mode.

For example, HPSF-NAND types memory allows hand over (single in continuous read mode and buffering read mode Paging is read) between.Table 6 shows that the instruction Read 03h of explanation are used for the sequential of General Sequences formula NAND-type flash memory, wherein General Sequences formula NAND-type flash memory operates in buffering read mode.General N AND type flash memory establishes other instructions, such as：FAST READ 0Bh、FAST READ DUAL OUTPUT 3Bh、FAST READ QUAD OUTPUT 6Bh、FAST READ DUAL I/O BBh and FAST READ QUAD I/O EBh timing method is similar to instructing Read 03h method.General N AND type The sequential of flash memory is using two hytes to row address C [15:0] and the virtual hyte of row address hyte is followed.Because space limits, The situation for being not depicted in table 6 is described below, and the data flow of the reading instruction of corresponding General Sequences formula NAND-type flash memory is not to terminate In the end of buffer, the initiating terminal of (wrap around) buffer is exactly returned to, until the signal/CS being converted is terminated.It is false Further instruction can be issued by such as wanting the extra paging of reading, be stored yet with preparation/busy inspection and from NAND Device array, which is read, needs the time, therefore this action can have an impact to delay.

During or after Fig. 3 is shown in startup power supply, the model selection declarative procedure of HPSF-NAND type memories, in mistake HPSF-NAND types memory starts according to the preset value of continuous read mode in journey, and in continuous read mode, a variety of readings refer to Order has identical instruction arrangement mode with HPSF-NOR instructions and instructs clock pulse is compatible, is contiguous therewith reading to export phase with it Hold, and after instruction is read, General Sequences formula NAND-type flash memory buffering can switch to according to desired mode and read mould Formula switches to continual pages read mode.Startup power supply (square 200), buffer mode sign BUF are according to default settings 0, and start and be automatically loaded default paging to the buffer (square 210) of list type NAND-type flash memory.Although any build on The paging of NAND-type flash memory can all be used as default paging, and for convenience of explanation, it is paging 0 to preset paging.The default paging of setting Illustrative technique, it is that default page address is stored in a configuration buffer (not shown), manufacturer can be limited to the configuration The access of buffer, or it is open to OEM or user.When default paging accesses beginning, busy sign (BUSY) is set For 1, to avoid default paging access by other instruction breaks.However, instruction can be allowed to be functional in busy period part, Without influenceing buffer mode sign BUF, which part instruction is, for example, instruction Get Feature 05h or instruction Read Status Register 0Fh, in check it is busy sign (BUSY) or instruction JEDEC ID 9Fh, in check fill Stay part (square 220).In busy period, other instructions can be allowed to change buffer mode sign BUF to 1, for example, make With instruction Device Reset FFh (square 230 be and square 240)；Otherwise, mould is buffered for every other instruction Formula is still 0.

Or if it is instruction Device in the first instruction (not shown) that busy sign (BUSY) is returned to after 0 Reset FFh, then buffer mode, which indicates BUF, can be changed to 1.Any other instruction makes state BUF=0 be held with conventional method OK.

After busy period, according to a method, to perform received reading instruction, and this method depends on BUF number Value.If BUF=0, which will then ignore any row address data in instruction and read operation, since row 0x00h and to be extended to Continuous paging, terminated (square 250 (0)) for high potential until as/CS.If BUF=1 then read operation (squares 250 (1)) from the row address [11 in the instruction specified:0] start and because the end of buffer is read or when/CS is high electricity Position and terminate.

Afterwards, memory visual operation needs to use a variety of miscellaneous operations (square 260), procedure operation and smears Division operation (square 270), paging activity (square 280), and read operation (square 290 (0) or square 290 (1)) are loaded into, depending on Depending on BUF numerical value.During general operation, by using instruction Set Feature or Write Status Register 1Fh or 01h writes BUF in state buffer, and buffer mode sign BUF may be set to 0 or 1, and number regards institute Depending on needing.Instruction Device Reset FFh can be used for interrupting any ongoing built-in function.Page is instructed when using During Data Read 13h, paging load operation (square 280) can be initialised, and the instruction permit the data of full paging from NAND Flash array user-can be read in addressing region 342 (as shown in Figure 4) to page buffer 338.(the Byte of hyte 2 2) virtual bit of sequential is included, and hyte 3 and hyte 4 then include page address.Paging activity is loaded into be loaded into paging performing Xx (square 280) receives a reading order afterwards, and reading order is performed according to BUF numerical value.If BUF=0 then ignores in instruction Any row address data and read operation since row 0x00h and continuous paging will be extended to, until being high electricity because of/CS Position and terminate (square 290 (0)).If BUF=1 read operations (square 290 (1)) are from the row address in the instruction specified [11:0] start and because the end of buffer is read or is terminated when/CS is high potential.

List type NAND-type flash memory framework

Fig. 4 is the functional block schematic diagram for the HPSF-NAND types memory 320 for showing explanation, wherein HPSF-NAND Type memory 320 can provide the continuous reading across paging border and the continuous reading of logically adjacent memory location And without waiting for interval.List type NAND-type flash memory 320 includes NAND-type flash memory array 340 and relevant page buffer 338.NAND-type flash memory array 340 includes word (row) line and position (OK) line, and by NAND array user-can addressing region 342, unnecessary block areas 344, and LUT information areas 346 are formed.Any required flash cell technology can be by using extremely The flash memory cell of NAND-type flash memory array 340.List type NAND-type flash memory 320 may include that various other circuits are deposited to support The operation of reservoir configuration processor, erase operation, read operation, seem column decoder 334, row decoder 336, input/output control Device 322, state buffer 323, continual pages read (continuous page read, CPR) address register 324, instruction Buffer 325, address register 326, LUT buffers 327, control logic 330, CPR bad blocks logic 331, CPR bad block buffers 332 and high voltage generator 333.Column decoder 334 (can be in certain embodiments, under the control of the user internally to control Under system) selection user-can addressing region 342 row.Column decoder 334 internally controls the lower unnecessary block areas 344 of selection (redundant block area) and LUT information areas 346 row.Power supply (not shown) passes through power line VCC and GND It is delivered to the circuit of whole list type NAND-type flash memory 320.Although list type NAND-type flash memory 320 can use any desired method Encapsulation and the interface (including General N AND type flash interface) that can have any kenel, but in Fig. 4, control logic 330 is Realized in a manner of SPI/QPI reaches an agreement on (including multi-IO SPI interfaces).On the more of SPI/QPI interfaces and memory The additional detail of kind circuit is exposed in US Patent No.7,558,900issued July 7,2009to Jigour et And publication Winbond Electronics Corporation, W25Q64DW al.,:SpiFlash 1.8V 64M-Bit Serial Flash Memory with Dual/Quad SPI&QPI:Preliminary Revision C,Hsinchu, Entire contents, are incorporated herein by reference by Taiwan, R.O.C., January 13,2011 hereby.

If want pattern switching, it is possible to provide buffer mode indicates BUF 347.If it is so desired, buffering mould can be provided Formula indicates state buffers 323 of the BUF 347 as a smallest number.In offer startup power supply detector in control logic 330 335, to preset the load of paging when initializing the setting of AD HOC and initialization startup power supply.

Page buffer 338 may include a paged data buffer (not shown), a paging cache buffer (not shown) And one paging transmission gate (not shown), with from Data buffer replicate data to cache buffer.Any suitable breech lock Device or memory technology can be used for Data buffer and cache buffer and appoint the suitable lock technology of conjunction to can be used for transmitting lock. Data buffer and cache buffer can be made up of a method the individual sites of any desirable number, for example, should Method is to connect transmission gate and operation transmission lock with line, is transmitted with control data.Data buffer and cache buffer can It is made up of two positions, and according to the transmission gate using respective group come selection operation, wherein transmission gate is by each controlling Line traffic control.The Data buffer and cache buffer of page buffer 338 are operable in conventional method, by applying identical control Signal processed is to respective transmission gate control line, or is operable in another method and passes through the suitable time control signal of application to transmission Lock control line.The realization at two positions is illustrated, a paging is 2K hytes, and a control line can control the half paging of transmission gate (1K) and the controllable transmission gate of other control lines second half paging (1K), thereby by Data buffer and cache buffer group As two near points page position.Because the operation at two positions is commutative, therefore the page buffer 338 that two positions are realized can It is considered as a ping-pong buffers.ECC circuit (not shown) is provided, performed with indicating the content of 348 pairs of cache buffers according to ECC-E ECC is calculated.If it is so desired, ECC-E signs 348 are provided as the state buffer 323 of sub-fraction.On paging Buffer 338, ECC circuit and both other details of operation are exposed in US Patent Application Serial Number 13/464,535 filed 05/04/2012(Gupta et al.,Method and Apparatus for Reading NAND Flash Memory), entire contents are incorporated herein by reference hereby.In continuous point described in this Page reads " continual pages of amendment are read " that can be considered in aforementioned patent.Data buffer and cache buffer form one Partial method and ECC method is performed illustrate use in the part, and other technologies also can be used optionally.

Although NAND-type flash memory 320 is performed various read operations, including continual pages read operation and in monoplane The ECC operation of (on-chip) in chip on NAND architecture, this framework are purposes of discussion.2KB paging size and given zone The example of block (block) size be only illustrate demonstration use, therefore also visual demand and it is different.In addition, the ginseng of particular size Examine and will not correctly be used, because the big I of actual paging changes according to design factor.For example, the paging size It may include that the significant area of 2,048 hyte adds the standby area of extra 64 hyte, standby area is used for storing ECC and other Information, such as descriptive data (meta-data).Identical, the 1KB paging size can be considered the significant area of 1,024 hyte And 32 hyte standby area.But in this narration be to be based on uniplanar structure, so that foregoing teaching can be apparent from this It is equal to application to multilevel structure.When more physical planes in use, these planes can share one or more wordline (word- Lines) so that storage system can simultaneously service composition input/output requirement.Each plane provides the data of a paging, with And each plane includes a corresponding Data buffer of a paging size and a corresponding cache buffer of a paging size.In Technology described by this can be applied to respective plane respectively, consequently, it is possible to which each Data buffer can be by multiple with cache buffer Close part to form, or can apply to composite plane so that any data buffer and cache buffer are a compound paged data A part for buffer and cache buffer.

Fig. 4 shows control signal/CS, CLK for SPI interface, DI, DO ,/WP and/Hold.Standard SPI quick flashings connect Mouthful offer/CS (chip selection-complement, chip select-complement), CLK (clock pulse), DI (sequence data inputs, Serial data-in) and DO (sequence data exports, serial data-out) signal, and along with nonessential signal/WP (write protection-complement, write protect-complement) and/HOLD (maintenance-complement, hold-complement). Although the 1 bit sequence data/address bus (by DI data inputs and by DO data outputs) for standard SPI interface provides letter Single interface and compatible with starting various controller in single SPI mode, but it is limited to be difficult to reach higher reading Throughput (thru-put).Therefore, more bit SPI interfaces are developing progressively extra and support two-wire (2 interfaces) and/or four lines (4 Position interface), to increase reading throughput.Fig. 4 also shows additional data bus signals, to carry out Dual SPI and Quad SP behaviour Make, its alternative redefines four pressure point I/O (0), I/O (1), I/O (2) and I/O (3) function to carry out Dual SPI And Quad SPI operations.

Quad SPI read operations (the Quad SPI read operations for being also applied for other versions) in a version, pass through I/O (0) and 1 standard SPI interface give suitable reading instruction, however, for addressing and data output with rear port Can be that four lines are basic (i.e. four figures is according to bus).Quad SPI read operations number of exportable four in a clock cycle According to a data contrast with the output of standard SPI read operations, Quad SPI read operations can provide four times of higher readings Throughput.But Quad SPI read operations are only used in this as explanation, this explanation is equally applicable for other operator schemes, bag Include Single SPI, Dual SPI, Quad Peripheral Interface (" QPI ") and Double Transfer Rate (" DTR ") read mode, but it is not limited to this.Under QPI agreements, complete interface (instruction, address and data output) Completed under the basis of four.Under DTR agreements, output data is provided as the upper limit and lower limit of CLK pulses, unlike in list Under the operation of one conversion ratio (Single Transfer Rate, STR) read mode, the CLK pulse lower limits for reading data are only provided.

The defective-area management of HPSF-NAND type memories

Because the NAND memory cell relevant with NOR-type memory cell typically has poor stability, thus need to make Use defective-area management.NAND-type flash memory array 340 includes three regions, and NAND Flash array user-can addressing region 342, more Remaining block areas 344 and LUT (Look-Up Table) information area 346.LUT buffers 327 store a look-up table, and are somebody's turn to do Look-up table is in order to carry out defective-area management, and comprising from logical block addresses (logical block address, LBA) to entity The mapping of block address (physical block address, PBA).Assuming that, for example, NAND-type flash memory array 340 has There is a little failure area (failed block).These failure areas are mapped most intimate friend area so that device remains to offer service.It is bad first Area is mapped to unnecessary block areas 344, then map to NAND Flash array user-can addressing region 342 available side Block.Although any mapping method can be used, unnecessary block areas is mapped to first, to maintain complete user as far as possible Can addressing region capacity.In order to effectively carry out defective-area management, look-up table can be built in LUT buffers 327, LUT is temporary Storage 327 can be directly entered control logic 330 and enter mapping logic 328.LUT buffers 327 are with not only small but also fast volatilization Property memory realize, seem SRAM type memory, although LUT buffers 327 can realize in any desired method and one or Some.When chip startup power supply or replacement, by reading LBA and PBA data from LUT information areas 346, LUT is temporary Storage 327 can be automatically loaded information.Defective-area management is described in detail in U.S. patent application case (Michael et al., On-Chip Bad Block Management for NAND Flash Memory), Reference Number 13/530,518, the applying date 06/22/2012, Entire contents are incorporated herein by reference hereby.Read and can be considered in priority patent application in the continual pages of this description " quick continual pages read (fast continuous page read) " being previously mentioned.

Fig. 5 is the program 400 for showing initiating sequence formula NAND-type flash memory, including default paging is read automatically, wherein automatically Default paging reading maps compatible and automatic default paging and read with bad block includes defective-area management.

During startup power supply, initialization BUSY signs are 1 (square 402), initialization buffering sign BUF 347 (Fig. 4) Setting value 0 (square 404) is, establishes look-up table (side in LUT buffers 327 according to the information of LUT information areas 346 Block 406), and default page address is loaded into address register 326 (square 408).Then substitution area's program is performed, it is meaned And searched in LUT buffers 327, to judge whether the regional address part of the address of address register 326 keeps in any in LUT The LBA matchings (square 410) of device 327.This search can be quickly performed without being had a significant impact to reading the access time, Because LUT buffers 327 can be not only small but also fast SRAM, wherein SRAM framework is (on-chip) in chip, therefore SRAM can Local access is carried out by control logic 330.If not finding any matching (square 410- is no), will be preset using LBA Value paging is read to page buffer 338 (square 414).If find matching (square 410- is), it is indicated that substituted bad block And using the PBA in substitution area in address register 326 rather than using LBA (square 412), to read default paging (square 414).ECC programs are performed in the data of page buffer 338, to be optionally set in what is obtained in state buffer 323 ECC positions (square 416).After the completion of ECC programs, BUSY signs are reset to 0 (square 418).

The ECC programs of HPSF-NAND type memories

In order to reach fast procedure code mapping, set (BUF=0) along with continuous read mode after startup power supply Next instruction can be that any general HPSF-NOR types memory reads instruction 03h, 0Bh, 3Bh, 6Bh, BBh and EBh, although referring to Make Fast Read Quad Output 6Bh and instruction Fast Read Quad I/O EBh more suitable, because two instructions Can each cycle export four, to reach highest conversion ratio.Continuous read mode reads instruction, and it ignores any in IA domain Interior instruction, it is seamless to start together with the page address in address register 326 continuously to read number across paging border According to.

If ECC programs are performed according to default paging read operation during startup power supply, except the decoding of instruction, then It can advantageously start to perform order that continuous read mode reads without the factor of any stand-by period, thus startup program 400 perform ECC programs (square 416).Although ECC programs can be performed in whole page buffer 338, if but rattle Buffer is arranged for page buffer 338, and during improving speed that continuous read mode is read, ECC programs then need Only performed on the page buffer 338 of half, the default paging reading required time is completed to reduce.

Fig. 6 aobvious is data/address bus 510 and NAND Flash array 550, is buffered together with the paging including Data buffer 540 The embodiment of device, and the Data buffer 540 is made up of two parts, Data buffer -0 (DR-0) and Data buffer -1 (DR-1).Page buffer also includes a cache buffer 530, is made up of two positions, be cache buffer -0 (CR-0) with And cache buffer -1 (CR-1).Therefore, page buffer can be considered as with include CR-0 and DR-0 a part and With the other parts for including CR-1 and DR-1.In one example, page buffer is divided into for that can have the capacity of 4K hytes The 2K hytes at two formed objects positions.For this situation, each memory capacity DR-0, DR-1, CR-0 and CR-1 are 1K Hyte.DR can be considered as full 2K hytes Data buffer (i.e. DR-0 adds DR-1) use and CR can be considered as full 2K hytes fast Buffer (i.e. CR-0 adds CR-1) is taken to use.Various sizes of page buffer can be used and/or page buffer can divide It is segmented into more than two positions or is divided into unequal position.Two positions of page buffer need two groups of control signals, Unlike not divided page buffer needs one group of control signal.In addition the difference between logical AND entity NAND Flash array Teaching herein is not influenceed.For example, entity array can have two pagings (even number 2KB pagings and odd number in a wordline 2KB pagings) so that wordline can be 4KB NAND positions memory cell.In order to solve clear explanation, description herein and figure Show it is logic-based NAND Flash array.Except, resumed studies extract operation with support company when page buffer is made up of two positions When, it is apparent to change for the user.Procedure operation can be completed with standard page sizes 2KB, and standard is read Operation (for example, after paging read operation is completed, the instruction of paged data is read from cache) also can be with standard paging chi Very little 2KB is completed.For situation using the interior tissue of this page buffer as two positions, read particularly suitable for continual pages Operation, even more so that its inside division is obvious for user.The buffer of NAND type memory array can be suitable Tissue and operation, with the gap of elimination output data during continual pages are read and discontinuously, and continual pages are read Technology it is consistent with the technology described by documents below, U.S. patent application case (Gupta et al., Method and Apparatus for Reading NAND Flash Memory), Application No. 13/464,535, the applying date 05/04/2012, Entire contents are incorporated herein by reference hereby.It can be considered in the continual pages reading of this description and apply institute in priority patent " modification continual pages read (modified continuous page read) " mentioned.

Fig. 6 also shows Error-Correcting Circuit 520, its can logicality be considered as that (region ECC-0 is carried with region ECC-0 For the error correction of memory cache position CR-0 contents) and (region ECC-1 provides memory cache with region ECC-1 The error correction of position CR-1 contents).Various ECC algorithms are all adapted to use, for example, Hamming ECC algorithms, BCH ECC algorithms, Reed-Solomon ECC algorithms and other algorithms.In order to clearly state, although two are patrolled It is to show indivedual interfaces as CR-0 and CR-1 to collect ECC positions ECC-0 and ECC-1, but two entity ECC blocks or list One entity ECC block can be used for the interface as both CR-0 and CR-1.

When Fig. 6 is shown in startup power supply, Data buffer 540 and cache buffer 530 are in the default paging read operation phase Between operation chart.The address of default paging 552 resides in address register 326, and default paging is from NAND Flash battle array Row 550 read out to two the positions DR-0 and DR-1 (operation A) of Data buffer 540.2KB data can be from default paging 552 It is transferred, branching program can be a 2KB transfer or being divided into 1KB is transferred to DR-0 and DR-1.The time of paging read operation (shifting paged data to the time of Data buffer from NAND Flash array) can be 20 μ s, although exact time can be because set Meter factor and change, seem sensing circuit, the kenel (single stage unit multi-level unit) or semiconductor technology of memory cell Design factors such as (seeming 50nm or 35nm).Then, it is transferred to cache in the position DR-0 of Data buffer 540 data The position CR-0 (operation B1) of buffer 530.Perform ECC to calculate, to calculate the position CR-0 of cache buffer 530 data (operation B2), and the data treated by ECC return to the position CR-0 (operation B3) of cache buffer 530.From position DR-0 Be transferred to position CR-0 (it is also same that position DR-1 is transferred to position CR-1) time changes regarding design alternative, but typical range is from big About 1 μ s to 3 μ s.When the time required to Error-Correcting Circuit 520 completely on the selection of ECC algorithms, internal data bus, crystal face Between depending on cycle oscillator and other design factors.Assuming that an entity design gives cache buffer using an ECC circuit square 530 two positions CR-0 and CR-1, and assume that the time for sending CR-0 and CR-1 is transferred to CR-0 and DR- for 20 μ s and DR-0 1 time for being transferred to CR-1 was 2 μ s, and Error-Correcting Circuit may be designed as all 18 μ s or less, if therefore only using single One circuit, then 36 μ s are needed to give position CR-0 and CR-1.Paging, which is read, to be ended without taking out data, even if Data buffer 540 and cache buffer 530 set continuous read mode and read instruction.

Fig. 7 shows read-me, to illustrate that the substantially continuous read mode of continuous read mode 600 instructs, and the instruction Mapping the compatible and instruction with bad block includes defective-area management, and the instruction starts to perform no any stand-by period factor, Except instruction is read in decoding.Fig. 8 is related to Fig. 7, is to show the portion related to Data buffer 540 and cache buffer 530 Divide operation.The primary condition for reading instruction is to propose default paging initial address in address register 326 and buffered in paging Device proposes the treated data of ECC.

Three substantially consistent operations can occur, that is to say, that from first part of buffer, clearly for be The CR-0 positions of cache buffer 530, export (square 630 and bus operation (Bus Operation) A1), buffered in paging The second part of device performs ECC processing, it is clear and definite for be cache buffer 530 CR-1 positions (square 632 and bus Operate A1, A2 and A3), and the data of next paging are read to page buffer, clearly for be Data buffer 540 position DR-0 and DR-1 (square 634 and array processing (Array Operation) A2).Bus operation A1 and slow Punching operation (Buffer Operation) A1, the about the same time in time interval A starts (time 1), but the latter is in the phase The interior operating time is smaller.Likewise, array processing A2 and buffer operation A2, during about the same in time interval A Between start (time 2 is after the time 1), but operating time of the latter within period is smaller.Counted by increasing with the address in chip Address in the relevant address register 326 of number device 329 (Fig. 4), accesses the data of next paging, and then perform substitution Area's program.In addition, it is only necessary to perform substitution area's program when the first paging is accessed and in each block border.In order to The generation of the above situation is detected, circuit can be made to complicate, but even if in order to simplify circuit without detecting the above situation, substitution Area's program can perform harmless in each paging access path.

Then, two substantially consistent operations can occur, that is to say, that from the second part of buffer, clearly come Say be cache buffer 530 CR-1 positions, export (square 640 and bus operation B1), at first of page buffer Part performs ECC processing, it is clear and definite for be cache buffer 530 CR-0 positions (square 642 and buffer operation B1, B2 And B3).Bus operation B1 will take the most time, therefore need not provide extra time to betiding in the bus operation B times Buffer operation B1, B2 and B3.About the same times (time 1) of the bus operation B1 and buffer operation B1 in time interval B Start, but the time that the latter operates within period is very small.

Because the data of present full paging have exported (bus operation A1 and B1) and the ECC in state buffer 323 Position has also been set, therefore executable temporary bad block calculates (square 650).Bad block calculates and is described in detail in United States Patent (USP) Application case (Michael et al., On-chip Bad Block Management for NAND Flash Memory), Shen Please Reference Number 13/530,518, the applying date 06/22/2012, entire contents are incorporated herein by reference hereby.In this description Continual pages read " quick continual pages reading (the fast continuous that can be considered and be previously mentioned in priority patent application page read)”。

Continuous read mode program 600 is repeated to terminate until by any desired method.The technology of one illustrative is used To stop clock signal CLK, wherein, the as little as high transformation of clock signal CLK quilt/CS signals follows so that continuous to read not Restart again, according to the clock signal CLK restarted after interruption.Or continuous read mode can be designed as according to it Signal that he sends and terminate, after one is default or a certain amount of paging is read, or any other designer is thought The method wanted.Ensuing paging is read due to not using extra reading to instruct, therefore the instruction decoding time can be by Avoid.Ping-pong buffers techniques permit ECC processing times and next paging read access time are substantially hidden in continuous data In the time of output.When meeting with the problem of substituting area, in a fast chip LUT buffers it is whole simultaneously, can be from NAND-type flash memory Middle start is read along with the continual pages of defective-area management, but without obvious postpone paging read access time, therefore is more avoided that and is appointed What gap or across paging and discontinuous, the LUT buffers wherein in the fast chip of block border, e.g. Fig. 4's LUT buffers 327, local reading can be carried out by the control logic 330 of control logic, such as Fig. 4.Simultaneous bus behaviour Make A1, paging activity A2 (by the time delay needed for buffer operation A1) and buffer operation A1 and A3 are designed to spend phase The same time, therefore optimize time utilization.For changing and the time of the paged data of output data bus 510 half, about 20 μ s, it is assumed that clock frequency 100MHz, and the time of paging read operation is about 20 μ s, although when any specially designed Between can with various designs may and change.

Although paging read and ECC programs needed for time, about 40 μ s, can be considered initial latency because Element, instruction repertorie is not influenceed during it betides startup power supply and.On the contrary, except the instruction decoding time, mould is continuously read Formula is read without waiting for time factor.Although instruction is read in paging the time may be needed to complete, nearly about 60 μ s, but for Across for the continuous reading on continual pages border, paging is read instruction and only sent once.

Description of the invention includes foregoing application and advantage is illustrative and can't be intended to limit this The scope of invention, it is set forth in claim.In the embodiment of this exposure be alterable and amendment, it is and actual Select with the selections of the Various Components of the present embodiment and it is equivalent will be understood by the those skilled in the art in this area, and can be carried out Without departing from the spirit and scope of the present invention, including claim set forth in the present invention.For example, although being retouched in this State the realization of many nand type memories, but in the portion of techniques described by this, seem startup power supply order, model selection, It is spaced, can be used for without waiting across paging border and from the continuous data output of the continuous memory location of logicality Run-in index nand type memory.

Claims (23)

1. a kind of list type NAND-type flash memory, it is characterised in that the list type NAND-type flash memory includes：

One encapsulation, is encapsulated from a 8-pin WSON, 24-pin FBGA encapsulation, 8-pin SOIC encapsulation and a 16-pin Selected in one colony of SOIC encapsulation compositions, wherein at least some pressure points of the encapsulation are the active pressure point of a SPI interface；

One NAND-type flash memory array, included in the encapsulation；

One page buffer, included in the encapsulation and it is coupled to the NAND-type flash memory array；And

One control logic, included in the encapsulation and the NAND-type flash memory array and the page buffer are coupled, with corresponding one Read instruction and one data are provided, the wherein data are exported to the SPI interface by the page buffer from the NAND-type flash memory An at least pressure point for active pressure point；

Wherein, the control logic also to should read instruction provide a continuous data export, wherein the continuous data output across Undue page boundary and from memory location output neighbouring in logic and without waiting for interval.

2. list type NAND-type flash memory according to claim 1, it is characterised in that the encapsulation includes an output pressure point, and The output pressure point is identical with an output pressure point of the corresponding form of the encapsulation of a high-effect list type NOR-type flash memory.

3. list type NAND-type flash memory according to claim 1, it is characterised in that the corresponding high-effect sequence of reading instruction Column NOR reads instruction, and it is compatible that the control logic also reads instruction clock pulse with the high-effect list type NOR, with to should be efficient Energy list type NOR reading instruction provides continuous data output.

4. list type NAND-type flash memory according to claim 1, it is characterised in that the encapsulation is with 48 square millimeters or more Few floor space.

5. a kind of list type NAND-type flash memory device, it is characterised in that the list type NAND-type flash memory device includes：

One encapsulation, the active SPI interface with 48 square millimeters or less of floor spaces and with four to six pressure points；

One NAND-type flash memory array, is contained in the encapsulation；

One page buffer, included in the encapsulation and couple the NAND-type flash memory array；And

One control logic, included in the encapsulation and the NAND-type flash memory array and the page buffer are coupled, with corresponding one Read instruction and the output of one continuous data be provided, the wherein control logic by the page buffer, by continuous data output by The list type NAND-type flash memory device is provided to an at least pressure point for the active SPI interface；

Wherein continuous data output is across paging border and from memory location neighbouring in logic and without waiting for interval.

6. list type NAND-type flash memory device according to claim 5, it is characterised in that the encapsulation includes an output and pressed Point, and the output pressure point is identical with an output pressure point of the corresponding form of the encapsulation of a high-effect list type NOR-type flash memory.

7. list type NAND-type flash memory device according to claim 5, it is characterised in that this is encapsulated as one 8 pressure points WSON is encapsulated.

8. list type NAND-type flash memory device according to claim 5, it is characterised in that this is encapsulated as one 24 pressure points FBGA is encapsulated.

9. list type NAND-type flash memory device according to claim 5, it is characterised in that the page buffer is a table tennis Buffer.

10. a kind of NAND-type flash memory device, it is characterised in that described NAND-type flash memory device includes：

One interface；

One NAND-type flash memory array；

One page buffer, couple the NAND-type flash memory array；

One control logic, the NAND-type flash memory array and the page buffer are coupled, it is continuous to read instruction offer one with corresponding one The continuous data is exported from the NAND-type flash memory device and provided by data output, the wherein control logic by the page buffer To the interface；

Wherein continuous data output is across paging border and from memory location neighbouring in logic and without waiting for interval； And

One startup power supply detector, in startup power supply, initialize the NAND-type flash memory array to the page buffer one is pre- If the load of paging.

11. NAND-type flash memory device according to claim 10, it is characterised in that described NAND-type flash memory device also wraps Buffer mode sign is included, when electric power is opened, the startup power supply detector sets the buffer mode and is indicated to a continual pages Read mode.

12. NAND-type flash memory device according to claim 11, it is characterised in that the interface includes the SPI of an identical element The SPI interface of interface and bit more than one.

A kind of 13. method for operating a NAND-type flash memory device, it is characterised in that the side of one NAND-type flash memory device of the operation Method includes：

Receive one and read instruction, wherein corresponding one high-effect list type NOR flash memory of reading instruction read instruction and with that time Pulse-phase holds；And

To command reception step should be read continuous data output, the wherein continuous data are provided from the NAND-type flash memory device Output is across paging border and from memory location adjacent in logic and without waiting for interval.

14. the method for one NAND-type flash memory device of operation according to claim 13, it is characterised in that it is one to read instruction Reading instructs (Read command), quick read to instruct (Fast Read command), twice of an output of quick reading to refer to (Fast Read Dual Output command), one is made quickly to read four times of output order (Fast Read Quad Output command), one quickly read twice of input/output instruction (Fast Read Dual I/O command) or one It is quick to read one of four times of input/output instructions (Fast Read Quad I/O command).

15. the method for one NAND-type flash memory device of operation according to claim 13, it is characterised in that the NAND-type flash memory Device includes a NAND-type flash memory array and couples a page buffer of the NAND-type flash memory array, and the wherein offer Step includes：

From the data of the NAND-type flash memory array one paging of reading to the page buffer；

ECC processing data programs are performed in page buffer, to produce the treated data of ECC；And

The data treated from page buffer output ECC；

Wherein, the time of the paging read step and execution ECC processing data program steps is included in output ECC processing In the time for the data step crossed.

16. the method for one NAND-type flash memory device of operation according to claim 15, it is characterised in that use defective-area management To perform the paging read step.

17. a kind of operate with a NAND-type flash memory array and a page buffer relevant with the NAND-type flash memory array The method of one memory, it is characterised in that methods described includes：

Select a paging of the NAND-type flash memory array；

The data from the selected paging are stored into the page buffer；

ECC is performed to the data in the page buffer to calculate；

The data are exported from the page buffer；And

Paging selection is repeated, data storage, ECC, which is calculated, to be performed, and data output step make it that data output is continuous And across paging border and from memory location adjacent in logic and without waiting for interval；

Wherein, paging selection step is initially included in the default paging of selection one in the NAND-type flash memory array, and wraps afterwards Include the multiple continuous sequentially pagings for selecting the NAND-type flash memory array；

Wherein, it is automatic during the paging selects, data storage, and ECC calculating execution steps are initially at the flash memory startup power supply Perform, then correspond to one and read instruction execution；And

Wherein, the data output step is performed to instruction should be read.

A kind of 18. method for operating a NAND-type flash memory, it is characterised in that methods described includes：

During the NAND-type flash memory startup power supply, one default point of a NAND-type flash memory array of the NAND-type flash memory is selected Page；

During the NAND-type flash memory startup power supply, store and preset the data of paging to a page buffer from this；

After the data storage step, ECC is performed to the data for being stored in the page buffer and calculated；

Receive one and read instruction；And

Continuous data output is provided from the NAND-type flash memory by the page buffer to command reception step should be read, its In the continuous data output across paging border and from memory location adjacent in logic and without waiting for interval.

19. a kind of flash memory opened with a NAND-type flash memory array and a paging relevant with the NAND-type flash memory array are delayed The method for rushing the electric power of device, it is characterised in that it is described open with a NAND-type flash memory array flash memory and with the NAND The method of the electric power of the relevant page buffer of flash array includes：

It is a continuous read mode or a buffering read mode to set the flash memory；

Paging, which is preset, from the one of the NAND-type flash memory array shifts a paged data to the page buffer；

ECC processing is performed to the data of the default paging in the page buffer, to provide the treated default pagings of an ECC Data；

After the data transfer step and the ECC processing steps, receive one and read instruction；And

When the flash memory is in the continuous read mode, to should read instruction receive step from the flash memory export a continuous data it is defeated Go out, wherein continuous data output across paging border and from memory location adjacent in logic and without waiting for interval, And initiate from the default paged data that the ECC in the page buffer is treated；And

When the flash memory is in the buffering read mode, a data are exported from the flash memory to command reception step should be read, and institute is defeated The data gone out are the data in the page buffer.

20. it is according to claim 19 open with a NAND-type flash memory array flash memory and with the NAND-type flash memory battle array The method for showing the electric power of a page buffer of pass, it is characterised in that described to open the sudden strain of a muscle with a NAND-type flash memory array Deposit and the method for the electric power of a page buffer relevant with the NAND-type flash memory array also includes, in the control of a manufacturer Under establish the default paging.

21. it is according to claim 19 open with a NAND-type flash memory array flash memory and with the NAND-type flash memory battle array The method for showing the electric power of a page buffer of pass, it is characterised in that described to open the sudden strain of a muscle with a NAND-type flash memory array Deposit and the method for the electric power of a page buffer relevant with the NAND-type flash memory array also includes, in the control of a user Under establish the default paging.

22. a kind of operate the one of the page buffer for having a NAND-type flash memory array and coupling the NAND-type flash memory array The method of memory, it is characterised in that the operation has a memory of a NAND-type flash memory array and couples the NAND The method of one page buffer of type flash array includes：

Receive one and continuously read instruction, including an instruction encoding and an initial address；And

It is defeated by one continuous data of NAND-type flash memory array offer by the page buffer to command reception step should be read Go out, wherein continuous data output is across paging border and from memory location adjacent in logic and without waiting for interval；

Wherein, the offer step is since the initial row of the page buffer and unrelated with the initial address.

23. operation according to claim 22 is with a NAND-type flash memory array and couples the NAND-type flash memory array The method of one memory of one page buffer, it is characterised in that the reading instruction for one read instruct (Read command), One quick reads instructs (Fast Read command), one quickly to read twice of output order (Fast Read Dual Output command), one quickly read four times of output orders (Fast Read Quad Output command), one quick Read twice of input/output instruction (Fast Read Dual I/O command) or four times of input/output of quick reading refer to Make one of (Fast Read Quad I/O command).