CN104392995A - Transistor, drive circuit and drive method thereof and display device - Google Patents

Transistor, drive circuit and drive method thereof and display device Download PDF

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Publication number
CN104392995A
CN104392995A CN201410597286.6A CN201410597286A CN104392995A CN 104392995 A CN104392995 A CN 104392995A CN 201410597286 A CN201410597286 A CN 201410597286A CN 104392995 A CN104392995 A CN 104392995A
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transistor
grid
connects
source electrode
current
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CN201410597286.6A
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Chinese (zh)
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CN104392995B (en
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王博
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京东方科技集团股份有限公司
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Abstract

The embodiment of the invention provides a transistor, a drive circuit and a drive method thereof and a display device, and relates to the technical field of display. Size of output current of the transistor can be enhanced without increasing the size of the transistor. The transistor comprises a P-type semiconductor substrate, a base electrode which is arranged on a first region and composed of a P-type ion layer doped by positive charges, and a source electrode and a drain electrode which are arranged on a second region and composed of a first N-type ion layer doped by negative charges and a second N-type ion layer doped by the negative charges respectively. Doping concentration of the first N-type ion layer, the second N-type ion layer and the P-type ion layer is greater than that of the P-type semiconductor substrate. The transistor also comprises a gate electrode which is mutually insulated with the source electrode and the drain electrode via a gate insulating layer. The source electrode acts as an emitting electrode, and the drain electrode acts as a collecting electrode. The invention is used for the transistor and preparation of the drive circuit comprising the transistor.

Description

A kind of transistor, drive circuit and driving method thereof, display unit

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of transistor, drive circuit and driving method thereof, display unit.

Background technology

Core component in organic electroluminescence display device and method of manufacturing same (OLED) is light-emitting component, i.e. OLED, its brightness is proportional to the size of current of input, therefore, in order to improve the display effect of OLED display, usually need the output current increasing the transistor driving its luminescence.

As shown in Figure 1, prior art mainly improves the ducting capacity of transistor by the breadth length ratio (W/L) increasing the region (channel region namely under transistor turns state) relative with drain electrode 22 with source electrode in active layer 50 overlay region 21 of grid 40 in transistor, thus the size of current exported after improving transistor turns.Be limited to the impact of the factors such as patterning processes, normally when not changing L numerical value, the numerical value of W increased with the ratio improving W/L, the increase of transistor overall dimensions will inevitably be caused like this, cause the aperture opening ratio of display unit to decline, affecting display quality.

Summary of the invention

Given this, for solving the problem of prior art, embodiments of the invention provide a kind of transistor, drive circuit and driving method thereof, display unit, can improve the size of transistor output current without the need to increasing transistor size.

For achieving the above object, embodiments of the invention adopt following technical scheme:

On the one hand, embodiments provide a kind of transistor, comprise, P type semiconductor substrate, described P type semiconductor substrate comprises first area and second area; Be positioned at the base stage on described first area, the P type sheath that described base stage is adulterated by positive charge is formed; Be positioned at the source electrode on described second area and drain electrode, the first N-type sheath that described source electrode and described drain electrode are adulterated by negative electrical charge respectively and the second N-type sheath that negative electrical charge adulterates are formed; The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate; Also comprise the grid by gate insulation layer and described source electrode, the mutually insulated that drains; Wherein, described source electrode is simultaneously as emitter, and described drain electrode is simultaneously as collector electrode.

Optionally, described P type semiconductor substrate comprises any one in P-type silicon substrate, P type germanium substrate, P-type silicon germanium substrate.

The embodiment of the present invention additionally provides a kind of drive circuit, comprises, the first transistor, and the grid of described the first transistor connects sweep signal, and the source electrode of described the first transistor connects the first data-signal; Transistor seconds, described transistor seconds is the transistor described in claim 1 or 2, the grid of described transistor seconds connects the drain electrode of described the first transistor, the drain electrode of described transistor seconds connects the output of collector voltage, the source electrode of described transistor seconds connects the output of output current, and the base stage of described transistor seconds connects source electrode and the drain electrode of described transistor seconds respectively; Third transistor, the source electrode of described third transistor connects the base stage of described transistor seconds, and the drain electrode of described third transistor connects base voltage; 4th transistor, the grid of described 4th transistor connects sweep signal, and the source electrode of described 4th transistor connects the second data-signal, and the drain electrode of described 4th transistor connects the grid of described third transistor.

Optionally, described drive circuit also comprises the first electric capacity, and one end of described first electric capacity connects the grid of described transistor seconds, the other end ground connection of described first electric capacity.

Optionally, described drive circuit also comprises the second electric capacity, and one end of described second electric capacity connects the grid of described third transistor, the other end ground connection of described second electric capacity.

The embodiment of the present invention additionally provides a kind of driving method of above-mentioned drive circuit, comprise, by sweep signal, the first data-signal and the second data-signal conducting the first transistor and the 4th transistor respectively, described first data-signal and described second data-signal are write respectively and remains on the grid of transistor seconds and the grid of third transistor; Collector voltage is write and remains on the drain electrode of described transistor seconds; By regulating the voltage swing of described first data-signal of the grid of the described transistor seconds of write, writing the voltage swing of described second data-signal of the grid of described third transistor, the size of the base current of the size controlling the On current of described transistor seconds respectively and the base stage being input to described transistor seconds, derives output current by the source electrode of described transistor seconds; Wherein, described output current and described On current, described base current meet default functional relation, and the independent variable of described functional relation is the size of described On current and the size of described base current, and dependent variable is the size of described On current.

On the other hand, the embodiment of the present invention additionally provides another kind of transistor, comprises, N type semiconductor substrate, and described N type semiconductor substrate comprises first area and second area; Be positioned at the base stage on described first area, the N-type sheath that described base stage is adulterated by positive charge is formed; Be positioned at the source electrode on described second area and drain electrode, the P type sheath that described source electrode and described drain electrode are adulterated by negative electrical charge respectively and the 2nd P type sheath that negative electrical charge adulterates are formed; The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate; Also comprise the grid by gate insulation layer and described source electrode, the mutually insulated that drains; Wherein, described drain electrode is simultaneously as emitter, and described source electrode is simultaneously as collector electrode.

Optionally, described N type semiconductor substrate comprises any one in N-type silicon substrate, N-type germanium substrate, N-type silicon-Germanium substrate.

The embodiment of the present invention additionally provides another kind of drive circuit, comprises, the first transistor, and the grid of described the first transistor connects sweep signal, and the source electrode of described the first transistor connects the first data-signal; Transistor seconds, described transistor seconds is the transistor described in claim 3 or 4, the grid of described transistor seconds connects the drain electrode of described the first transistor, the source electrode of described transistor seconds connects the output of collector voltage, the drain electrode of described transistor seconds connects the output of output current, and the base stage of described transistor seconds connects source electrode and the drain electrode of described transistor seconds respectively; Third transistor, the source electrode of described third transistor connects the base stage of described transistor seconds, and the drain electrode of described third transistor connects base voltage; 4th transistor, the grid of described 4th transistor connects sweep signal, and the source electrode of described 4th transistor connects the second data-signal, and the drain electrode of described 4th transistor connects the grid of described third transistor.

Optionally, described drive circuit also comprises the first electric capacity, and one end of described first electric capacity connects the grid of described transistor seconds, the other end ground connection of described first electric capacity.

Optionally, described drive circuit also comprises the second electric capacity, and one end of described second electric capacity connects the grid of described third transistor, the other end ground connection of described second electric capacity.

The embodiment of the present invention additionally provides a kind of driving method of above-mentioned drive circuit, comprise, by sweep signal, the first data-signal and the second data-signal conducting the first transistor and the 4th transistor respectively, described first data-signal and described second data-signal are write respectively and remains on the grid of transistor seconds and the grid of third transistor; Collector voltage is write and remains on the drain electrode of described transistor seconds; By regulating the voltage swing of described first data-signal of the grid of the described transistor seconds of write, writing the voltage swing of described second data-signal of the grid of described third transistor, the size of the base current of the size controlling the On current of described transistor seconds respectively and the base stage being input to described transistor seconds, derives output current by the drain electrode of described transistor seconds; Wherein, described output current and described On current, described base current meet default functional relation, and the independent variable of described functional relation is the size of described On current and the size of described base current, and dependent variable is the size of described On current.

One side, the embodiment of the present invention additionally provide a kind of display unit again, comprise above-mentioned described drive circuit.

Optionally, described display unit comprises organic electroluminescence display device and method of manufacturing same.

The above-mentioned transistor that the embodiment of the present invention provides, as the base current Ib being greater than zero to described base stage input, to the grid voltage Vg that described grid input is greater than zero, and when being greater than the collector voltage Vc of zero to described drain electrode input, described source electrode is simultaneously as emitter (Emitter), and described drain electrode is simultaneously as collector electrode (Collector); Therefore, transistor has now had the function of MOSFET pipe and BJT pipe concurrently simultaneously, under being operated in the admixture of MOSFET-BJT, the electric current I (out) exported from above-mentioned transistor changes along with the change of grid voltage Vg and base current Ib, namely increase the size of output current I (out) compared with the transistor provided with prior art by introducing Ib, thus the size achieved without the need to increasing transistor can improve the ability of transistor output current.

In addition, owing to working as Vg<0, during Ib>0, namely time MOSFET pipe does not have a conducting conducting BJT pipe, above-mentioned transistor has had certain electric current to output (namely being determined by Ib), thus adds the scope being regulated transistor electric current by grid voltage Vg.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

The structural representation of a kind of transistor that Fig. 1 provides for prior art;

The structural representation one of a kind of transistor that Fig. 2 provides for the embodiment of the present invention;

The operation principle schematic diagram that Fig. 3 is the transistor shown in Fig. 2;

The different operating state vs table of a kind of transistor that Fig. 4 provides for the embodiment of the present invention;

A kind of transistor that Fig. 5 provides for the embodiment of the present invention contrasts schematic diagram with the electric current curve of output of the transistor of prior art under hybrid working state;

The structural representation two of a kind of transistor that Fig. 6 provides for the embodiment of the present invention;

The operation principle schematic diagram that Fig. 7 is the transistor shown in Fig. 6;

The structural representation one of a kind of drive circuit that Fig. 8 provides for the embodiment of the present invention;

The structural representation two of a kind of drive circuit that Fig. 9 provides for the embodiment of the present invention.

Reference numeral:

10-P type Semiconductor substrate; 11-N type Semiconductor substrate; 101/111-first area; 102/112-second area; 20-base stage; 21-source/emitter; 22-drain/collector; 30-gate insulation layer; 40-grid; 50-active layer.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Embodiments provide a kind of transistor, as shown in Figure 2, described transistor comprises: P type semiconductor substrate 10, and described P type semiconductor substrate 10 comprises first area 101 and second area 102; Be positioned at the base stage 20 on described first area 101, the P type sheath that described base stage 20 is adulterated by positive charge is formed; Be positioned at the source electrode 21 on described second area 102 and drain electrode 22, the first N-type sheath that described source electrode 21 and described drain electrode 22 are adulterated by negative electrical charge respectively and the second N-type sheath that negative electrical charge adulterates are formed; The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate 10; Described transistor also comprises by the grid 40 of gate insulation layer 30 with described source electrode 21,22 mutually insulateds that drain.

Wherein, described source electrode 21 is simultaneously as emitter (Emitter), and described drain electrode 22 is simultaneously as collector electrode (Collector).

It should be noted that, the first, when described transistor, the electric current being greater than zero inputted to described base stage 20 is called base current (being hereinafter all labeled as Ib), the voltage being greater than zero to described grid 40 input is called grid voltage (being hereinafter all labeled as Vg), to described drain electrode 22, the voltage being greater than zero namely simultaneously inputted as described collector electrode is called collector voltage (being hereinafter all labeled as Vc).

The second, the method for diffusion technology or ion implantation can be utilized to form at P type semiconductor substrate Epitaxial growth the source electrode 21 and drain electrode 22 that the second N-type sheath that base stage 20, the first N-type sheath adulterated by negative electrical charge respectively and negative electrical charge that the P type sheath that adulterated by positive charge forms adulterate forms.Wherein, the concrete doping content of described first N-type sheath, described second N-type sheath and described P type sheath is not construed as limiting, as long as the doping content meeting described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate 10.Here, shown in figure 1, " P+ " represents that positive charge adulterates, and " N+ " represents that negative electrical charge adulterates.

Further as shown in Figure 4, the above-mentioned transistor that the embodiment of the present invention provides, by giving grid 40, base stage 20 and source electrode 21 port suitable voltage, make above-mentioned transistor can be operated in bipolar junction transistor (BJT respectively, Bipolar Junction Transistor) mode of operation, mos field effect transistor (Metal Oxide Silicon FieldEffect Transistor, be called for short MOSFET) under mode of operation and the blend modes of operation of the two, described in specific as follows:

Work as Vg<0, during Ib<0, transistor cannot conducting, now, the electric current (being hereinafter all labeled as I (out)) that described transistor exports is zero, namely with this understanding, described transistor does not have conducting, does not carry out work.

Work as Vg<0, during Ib>0, base stage 20, source electrode 21, drain electrode 22 and P type semiconductor substrate 10 are equivalent to constitute a BJT pipe; Wherein, source electrode 21 is equivalent to emitter (Emitter), and drain electrode 22 is equivalent to collector electrode (Collector).Namely, described transistor equivalent is managed in a BJT with this understanding, due to the collector voltage Vc that 22 accesses that drain are greater than zero, therefore, the direction of the On current I (BJT) in BJT pipe is as pointed to source electrode 21 (i.e. collector electrode Collector) in Fig. 3.

Here, because the numerical value of collector voltage Vc is relevant with the size model of transistor, does not do concrete restriction at this, such as, can be a few volt ~ tens volt.

Work as Vg>0, during Ib<0, grid 40, source electrode 21, drain electrode 22 and P type semiconductor substrate 10 are equivalent to constitute a MOSFET pipe; Namely, described transistor equivalent is managed in a BJT with this understanding, due to the collector voltage Vc that 22 accesses that drain are greater than zero, therefore, On current in the MOSFET pipe determined by grid voltage Vg, namely the direction of the channel current I (MOSFET channel) of MOSFET pipe is as pointed out from source electrode 21 in Fig. 3.

Work as Vg>0, during Ib>0, due to the collector voltage Vc that 22 accesses that drain are greater than zero, source electrode 21 is simultaneously also as emitter, drain electrode 22 is simultaneously also as collector electrode, and namely now, the above-mentioned transistor be made up of base stage 20, source electrode 21, drain electrode 22, grid 40 and P type semiconductor substrate 10 has had the function of MOSFET pipe and BJT pipe concurrently simultaneously, therefore, this operating state is called MOSFET-BJT hybrid mode (i.e. hybrid working state).In the case, due to MOSFET pipe and all conductings simultaneously of BJT pipe, the electric current I namely exported from above-mentioned transistor (out) is relevant with collector current Ib with grid voltage Vg.

Wherein, when above-mentioned transistor is in MOSFET-BJT hybrid state, the large I of output current I (out) is drawn by following formula:

I (BJT)=(1+ β) Ib; Formula (1)

I (out)=I (MOSFETchannel)+I (BJT); Formula (2)

I (out)=I (MOSFETchannel)+(1+ β) Ib; Formula (3)

Wherein, β is amplification coefficient, and it is defined as the ratio of emitter current and base current, i.e. Ie/Ib.Because magnificationfactorβ is relevant with the size model of transistor, does not do concrete restriction at this, such as, can be tens ~ hundreds of.

For the transistor that the parameters such as size model are given, magnificationfactorβ is a positive definite value.Therefore, from formula (3), when above-mentioned transistor is in MOSFET-BJT hybrid state, the size of output current I (out) is determined by I (MOSFET channel) and Ib, is equivalent in output current, introduce Ib electric current.Shown in further Fig. 5, can find out, in the curve of the output current I (out) under MOSFET-BJT hybrid operating state and figure, the curve of the output current I (out) of the transistor (as MOSFET manages) of the prior art of bottom is similar, output current I (out) just under MOSFET-BJT hybrid operating state becomes large due to the introducing of I (BJT) electric current, and I (BJT) electric current being equivalent to introduce has raised the integrated curved value of output current I (out).And, work as Vg<0, during Ib>0, namely time MOSFET pipe does not have a conducting conducting BJT pipe, above-mentioned transistor has had certain electric current to output (namely being determined by Ib), thus adds the scope being regulated transistor electric current by grid voltage Vg.

Based on this, the above-mentioned transistor that the embodiment of the present invention provides, as the base current Ib being greater than zero to described base stage 20 input, to the grid voltage Vg that described grid 40 input is greater than zero, and when being greater than the collector voltage Vc of zero to described drain electrode 22 input, described source electrode 21 is simultaneously as emitter (Emitter), and described drain electrode 22 is simultaneously as collector electrode (Collector); Namely transistor has now had the function of MOSFET pipe and BJT pipe concurrently simultaneously, under being operated in the admixture of MOSFET-BJT, thus the electric current I (out) exported from above-mentioned transistor is changed along with the change of grid voltage Vg and base current Ib, namely increase the size of output current I (out) compared with the transistor provided with prior art by introducing Ib, thus the size achieved without the need to increasing transistor can improve the ability of transistor output current.

In addition, owing to working as Vg<0, during Ib>0, namely time MOSFET pipe does not have a conducting conducting BJT pipe, above-mentioned transistor has had certain electric current to output (namely being determined by Ib), thus adds the scope being regulated transistor electric current by grid voltage Vg.

Preferred on the basis of the above, described P type semiconductor substrate comprises any one in P-type silicon substrate, P type germanium substrate, P-type silicon germanium substrate.

Here, described P type semiconductor substrate 10 refers to the substrate formed by mixing micro-P type ion in the semiconductor substrate; Wherein, P type ion can by trivalent cation (M such as boron ion (B), indium ion (In), gallium ion (Ga) and aluminium ions (Al) 3+) in one or more.

Semiconductor substrate can be directly made up of any one in silicon substrate (Si), germanium substrate (Ge), silicon-Germanium substrate, also can by SOI substrate (Silicon-On-Insulator, namely be formed at isolate supports substrate), GOI substrate (Germanium-On-Insulator, namely be formed at the germanium substrate on insulator), SGOI substrate (Silicon-Germanium-On-Insulator, namely be formed at isolate supports germanium substrate) in any one, and to be not limited thereto.

The embodiment of the present invention additionally provides another kind of transistor, and as shown in Figure 6, described transistor comprises: N type semiconductor substrate 11, and described N type semiconductor substrate 11 comprises first area 111 and second area 112; Be positioned at the base stage 20 on described first area 111, the N-type sheath that described base stage 20 is adulterated by positive charge is formed; Be positioned at the source electrode 21 on described second area 112 and drain electrode 22, the P type sheath that described source electrode 21 and described drain electrode 22 are adulterated by negative electrical charge respectively and the 2nd P type sheath that negative electrical charge adulterates are formed; The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate; Described transistor also comprises by the grid 40 of gate insulation layer 30 with described source electrode 21,22 mutually insulateds that drain.

Wherein, described drain electrode 22 is simultaneously as emitter (Emitter), and described source electrode 21 is simultaneously as collector electrode (Collector).

Here, as shown in Figure 7, concrete principle see above to the elaboration of Fig. 3, can not repeat them here the operation principle of above-mentioned transistor.

Preferred further, described N type semiconductor substrate 11 comprises any one in N-type silicon substrate, N-type germanium substrate, N-type silicon-Germanium substrate.

Here, described N type semiconductor substrate 10 refers to the substrate formed by mixing micro-N-type ion in the semiconductor substrate; Wherein, N-type ion can group Ⅴ element as pentavalent anion (N such as phosphorus (P), arsenic (As), antimony (Sb) 5-) in one or more.

Semiconductor substrate can be directly made up of any one in silicon substrate (Si), germanium substrate (Ge), silicon-Germanium substrate, also can by SOI substrate (Silicon-On-Insulator, namely be formed at isolate supports substrate), GOI substrate (Germanium-On-Insulator, namely be formed at the germanium substrate on insulator), SGOI substrate (Silicon-Germanium-On-Insulator, namely be formed at isolate supports germanium substrate) in any one, and to be not limited thereto.

On the basis of the above, the embodiment of the present invention additionally provides a kind of drive circuit, and as shown in Figure 8, described drive circuit comprises:

The first transistor T1, the grid G 1 of described the first transistor T1 connects sweep signal Scan, and the source S 1 of described the first transistor T1 connects the first data-signal Data-1.

Transistor seconds T2, described transistor seconds T2 is transistor described in reference diagram 2, the grid 40 of described transistor seconds T2 connects the drain D 1 of described the first transistor T1, the drain electrode 22 of described transistor seconds T2 connects the output of collector voltage Vc, the source electrode 21 of described transistor seconds T2 connects the output of output current I (out), and the base stage 20 of described transistor seconds T2 connects the source electrode 21 of described transistor seconds T2 and drain electrode 22 respectively.

The source S 3 of third transistor T3, described third transistor T3 connects the base stage 20 of described transistor seconds T2, and the drain D 3 of described third transistor T3 connects base voltage Vb.

4th transistor T4, the grid G 4 of described 4th transistor T4 connects sweep signal Scan, and the source S 4 of described 4th transistor T4 connects the second data-signal Data-2, and the drain D 4 of described 4th transistor T4 connects the grid G 3 of described third transistor T3.

Further, shown in figure 8, described drive circuit also can comprise the first electric capacity C1, and one end of described first electric capacity C1 connects the grid 40 of described transistor seconds T2, other end ground connection.

Further, shown in figure 8, described drive circuit also can comprise the second electric capacity C2, and one end of described second electric capacity C2 connects the grid 40 of described third transistor T3, other end ground connection.

Wherein, the effect of described first electric capacity C1 and described second electric capacity C2 is maintain and stabilize the grid 40 of described transistor seconds T2 and the voltage in the grid G 3 of described third transistor T3 respectively.

The embodiment of the present invention additionally provides a kind of driving method for above-mentioned drive circuit as shown in Figure 8, comprising:

S11, by sweep signal Scan, the first data-signal Data-1 and the second data-signal Data-2 respectively conducting the first transistor T1 and the 4th transistor T4, described first data-signal Data-1 and described second data-signal Data-2 is write respectively and remains on the grid 40 of transistor seconds T2 and the grid G 3 of third transistor T3.

S12, collector voltage Vc write and remains on the drain electrode 22 of described transistor seconds T2.

S13, by regulating the voltage swing of the described first data-signal Data-1 of the grid 40 of the described transistor seconds T2 of write, writing the voltage swing of the described second data-signal Data-2 of the grid G 3 of described third transistor T3, the size of the base current of the size controlling the On current I (MOSFET channel) of described transistor seconds T2 respectively and the base stage 20 being input to described transistor seconds T2, derives output current I (out) by the source electrode 21 of described transistor seconds T2.

Wherein, described output current I (out) and described On current I (MOSFET channel), described base current Ib meet default functional relation, that is:

I (out)=I (MOSFETchannel)+(1+ β) Ib; Formula (3)

Wherein, the independent variable of described functional relation be described On current I (MOSFETchannel), size and the size of described base stage Ib electric current, dependent variable is the size of described On current I (out).

Seen from the above description, the electric current I (out) exported from transistor seconds T2 changes along with the change of grid voltage Vg and base current Ib, the size of output current I (out) is provided by introducing Ib compared with the transistor namely provided with prior art, thus the size achieved without the need to increasing transistor can improve the ability of transistor output current, just can control by the size controlling the first data line signal Data-1 and the second data line signal Data-2 the total current Iout driving light-emitting component (as OLED element); Due to the introducing of above-mentioned I (BJT) electric current, the more common transistor of output current I (out) is improved a lot, thus significantly improves the luminous intensity of light-emitting component, strengthen display effect.

Further, the embodiment of the present invention additionally provides another kind of drive circuit, and as shown in Figure 9, described drive circuit comprises:

The first transistor T1, the grid G 1 of described the first transistor T1 connects sweep signal Scan, and the source S 1 of described the first transistor T1 connects the first data-signal Data-1.

Transistor seconds T2, described transistor seconds T2 is transistor as shown in Figure 6, the grid 40 of described transistor seconds T2 connects the drain D 1 of described the first transistor T1, the source electrode 21 of described transistor seconds T2 connects the output of collector voltage Vc, the drain electrode 22 of described transistor seconds T2 connects the output of output current I (out), and the base stage 20 of described transistor seconds T2 connects source electrode 21 and drain electrode 22 respectively.

The source S 3 of third transistor T3, described third transistor T3 connects the base stage 20 of described transistor seconds T2, and the drain D 3 of described third transistor T3 connects base voltage Vb.

The grid g4 of the 4th transistor T4, described 4th transistor T4 connects sweep signal Scan, and the source S 4 of described 4th transistor T4 connects the second data-signal Data-2, and the drain D 4 of described 4th transistor T4 connects the grid G 3 of described third transistor T3.

Further, above-mentioned drive circuit also comprises the first electric capacity C1, and one end of described first electric capacity C1 connects the grid 40 of described transistor seconds T2, other end ground connection.

Further, above-mentioned drive circuit also comprises the second electric capacity C2, and one end of described second electric capacity C2 connects the grid G 3 of described third transistor T3, other end ground connection.

On the basis of the above, the embodiment of the present invention additionally provides a kind of driving method for above-mentioned drive circuit, comprising:

S21, by sweep signal Scan, the first data-signal Data-1 and the second data-signal Data-2 respectively conducting the first transistor T1 and the 4th transistor T4, described first data-signal Data-1 and described second data-signal Data-2 is write respectively and remains on the grid 40 of transistor seconds T2 and the grid G 3 of third transistor T3.

S22, collector voltage Vc write and remains on the drain electrode 22 of described transistor seconds T2.

S23, by regulating the voltage swing of the described first data-signal Data-1 of the grid 40 of the described transistor seconds T2 of write, writing the voltage swing of the described second data-signal Data-2 of the grid G 3 of described third transistor T3, the size of the base current Ib of the size controlling the On current I (MOSFET channel) of described transistor seconds T2 respectively and the base stage 20 being input to described transistor seconds T2, derives output current I (out) by the drain electrode 22 of described transistor seconds T2.

Wherein, described output current I (out) and described On current I (MOSFET channel), described base current Ib meet default functional relation, that is:

I (out)=I (MOSFETchannel)+(1+ β) Ib; Formula (3)

Wherein, the independent variable of described functional relation be described On current I (MOSFETchannel), size and the size of described base stage Ib electric current, dependent variable is the size of described On current I (out).

Seen from the above description, the electric current I (out) exported from transistor seconds T2 changes along with the change of grid voltage Vg and base current Ib, the size of output current I (out) is provided by introducing Ib compared with the transistor namely provided with prior art, thus the size achieved without the need to increasing transistor can improve the ability of transistor output current, just can control by the size controlling the first data line signal Data-1 and the second data line signal Data-2 the total current Iout driving light-emitting component (as OLED element); Due to the introducing of above-mentioned I (BJT) electric current, the more common transistor of output current I (out) is improved a lot, thus significantly improves the luminous intensity of light-emitting component, strengthen display effect.

On the basis of the above, the embodiment of the present invention additionally provides a kind of current-driven display, comprises above-mentioned drive circuit.Described display unit can comprise organic electroluminescence display device and method of manufacturing same.

It should be noted that, institute of the present invention drawings attached is the simple schematic diagram of above-mentioned transistor and drive circuit, only for the clear this programme that describes embodies the structure relevant to inventive point, the structure irrelevant with inventive point for other is existing structure, in the accompanying drawings not embodiment or only realizational portion.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.

Claims (14)

1. a transistor, is characterized in that, comprises,
P type semiconductor substrate, described P type semiconductor substrate comprises first area and second area;
Be positioned at the base stage on described first area, the P type sheath that described base stage is adulterated by positive charge is formed;
Be positioned at the source electrode on described second area and drain electrode, the first N-type sheath that described source electrode and described drain electrode are adulterated by negative electrical charge respectively and the second N-type sheath that negative electrical charge adulterates are formed;
The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate;
Also comprise the grid by gate insulation layer and described source electrode, the mutually insulated that drains;
Wherein, described source electrode is simultaneously as emitter, and described drain electrode is simultaneously as collector electrode.
2. transistor according to claim 1, is characterized in that, described P type semiconductor substrate comprises any one in P-type silicon substrate, P type germanium substrate, P-type silicon germanium substrate.
3. a transistor, is characterized in that, comprises,
N type semiconductor substrate, described N type semiconductor substrate comprises first area and second area;
Be positioned at the base stage on described first area, the N-type sheath that described base stage is adulterated by positive charge is formed;
Be positioned at the source electrode on described second area and drain electrode, the P type sheath that described source electrode and described drain electrode are adulterated by negative electrical charge respectively and the 2nd P type sheath that negative electrical charge adulterates are formed;
The doping content of described first N-type sheath, described second N-type sheath and described P type sheath is all greater than the doping content of described P type semiconductor substrate;
Also comprise the grid by gate insulation layer and described source electrode, the mutually insulated that drains;
Wherein, described drain electrode is simultaneously as emitter, and described source electrode is simultaneously as collector electrode.
4. transistor according to claim 3, is characterized in that, described N type semiconductor substrate comprises any one in N-type silicon substrate, N-type germanium substrate, N-type silicon-Germanium substrate.
5. a drive circuit, is characterized in that, comprises,
The first transistor, the grid of described the first transistor connects sweep signal, and the source electrode of described the first transistor connects the first data-signal;
Transistor seconds, described transistor seconds is the transistor described in claim 1 or 2, the grid of described transistor seconds connects the drain electrode of described the first transistor, the drain electrode of described transistor seconds connects the output of collector voltage, the source electrode of described transistor seconds connects the output of output current, and the base stage of described transistor seconds connects source electrode and the drain electrode of described transistor seconds respectively;
Third transistor, the source electrode of described third transistor connects the base stage of described transistor seconds, and the drain electrode of described third transistor connects base voltage;
4th transistor, the grid of described 4th transistor connects sweep signal, and the source electrode of described 4th transistor connects the second data-signal, and the drain electrode of described 4th transistor connects the grid of described third transistor.
6. drive circuit according to claim 5, is characterized in that, also comprises, the first electric capacity, and one end of described first electric capacity connects the grid of described transistor seconds, the other end ground connection of described first electric capacity.
7. drive circuit according to claim 5, is characterized in that, also comprises, the second electric capacity, and one end of described second electric capacity connects the grid of described third transistor, the other end ground connection of described second electric capacity.
8. a driving method for the drive circuit as described in any one of claim 5 to 7, is characterized in that, comprises,
By sweep signal, the first data-signal and the second data-signal conducting the first transistor and the 4th transistor respectively, described first data-signal and described second data-signal are write respectively and remains on the grid of transistor seconds and the grid of third transistor;
Collector voltage is write and remains on the drain electrode of described transistor seconds;
By regulating the voltage swing of described first data-signal of the grid of the described transistor seconds of write, writing the voltage swing of described second data-signal of the grid of described third transistor, the size of the base current of the size controlling the On current of described transistor seconds respectively and the base stage being input to described transistor seconds, derives output current by the source electrode of described transistor seconds;
Wherein, described output current and described On current, described base current meet default functional relation, and the independent variable of described functional relation is the size of described On current and the size of described base current, and dependent variable is the size of described On current.
9. a drive circuit, is characterized in that, comprises,
The first transistor, the grid of described the first transistor connects sweep signal, and the source electrode of described the first transistor connects the first data-signal;
Transistor seconds, described transistor seconds is the transistor described in claim 3 or 4, the grid of described transistor seconds connects the drain electrode of described the first transistor, the source electrode of described transistor seconds connects the output of collector voltage, the drain electrode of described transistor seconds connects the output of output current, and the base stage of described transistor seconds connects source electrode and the drain electrode of described transistor seconds respectively;
Third transistor, the source electrode of described third transistor connects the base stage of described transistor seconds, and the drain electrode of described third transistor connects base voltage;
4th transistor, the grid of described 4th transistor connects sweep signal, and the source electrode of described 4th transistor connects the second data-signal, and the drain electrode of described 4th transistor connects the grid of described third transistor.
10. drive circuit according to claim 9, is characterized in that, also comprises, the first electric capacity, and one end of described first electric capacity connects the grid of described transistor seconds, the other end ground connection of described first electric capacity.
11. drive circuits according to claim 9, is characterized in that, also comprise, the second electric capacity, and one end of described second electric capacity connects the grid of described third transistor, the other end ground connection of described second electric capacity.
The driving method of 12. 1 kinds of drive circuits as described in any one of claim 9 to 11, is characterized in that, comprises,
By sweep signal, the first data-signal and the second data-signal conducting the first transistor and the 4th transistor respectively, described first data-signal and described second data-signal are write respectively and remains on the grid of transistor seconds and the grid of third transistor;
Collector voltage is write and remains on the drain electrode of described transistor seconds;
By regulating the voltage swing of described first data-signal of the grid of the described transistor seconds of write, writing the voltage swing of described second data-signal of the grid of described third transistor, the size of the base current of the size controlling the On current of described transistor seconds respectively and the base stage being input to described transistor seconds, derives output current by the drain electrode of described transistor seconds;
Wherein, described output current and described On current, described base current meet default functional relation, and the independent variable of described functional relation is the size of described On current and the size of described base current, and dependent variable is the size of described On current.
13. 1 kinds of display unit, is characterized in that, comprise as any one of claim 5 to 7, or the drive circuit described in any one of claim 9 to 11.
14. display unit according to claim 13, is characterized in that, described display unit comprises organic electroluminescence display device and method of manufacturing same.
CN201410597286.6A 2014-10-30 2014-10-30 A kind of transistor, drive circuit and its driving method, display device CN104392995B (en)

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Publication number Priority date Publication date Assignee Title
US20040155300A1 (en) * 2003-02-10 2004-08-12 Michael Baird Low voltage NMOS-based electrostatic discharge clamp
CN1536667A (en) * 2003-04-07 2004-10-13 三洋电机株式会社 Semiconductor device
US20100213504A1 (en) * 2009-02-20 2010-08-26 Ching-Chung Ko Lateral bipolar junction transistor
US20100252860A1 (en) * 2009-04-07 2010-10-07 Ming-Tzong Yang Lateral bipolar junction transistor with reduced base resistance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155300A1 (en) * 2003-02-10 2004-08-12 Michael Baird Low voltage NMOS-based electrostatic discharge clamp
CN1536667A (en) * 2003-04-07 2004-10-13 三洋电机株式会社 Semiconductor device
US20100213504A1 (en) * 2009-02-20 2010-08-26 Ching-Chung Ko Lateral bipolar junction transistor
US20100252860A1 (en) * 2009-04-07 2010-10-07 Ming-Tzong Yang Lateral bipolar junction transistor with reduced base resistance

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