CN104201165B - Double-ring silicon through silicon via structure and manufacturing method thereof - Google Patents
Double-ring silicon through silicon via structure and manufacturing method thereof Download PDFInfo
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- CN104201165B CN104201165B CN201410468354.9A CN201410468354A CN104201165B CN 104201165 B CN104201165 B CN 104201165B CN 201410468354 A CN201410468354 A CN 201410468354A CN 104201165 B CN104201165 B CN 104201165B
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Abstract
The invention relates to a double-ring silicon through silicon via structure and a manufacturing method thereof. The double-ring silicon through silicon via structure comprises a semiconductor substrate, a first dielectric layer, a first metal ring, a second dielectric layer, a second metal ring and a dielectric core layer sequentially from outside to inside. The manufacturing method of the double-ring silicon through silicon via structure includes: (1) forming a through via in the semiconductor substrate by etching; (2) preparing the first dielectric layer on the inner surface of the through via; (3) preparing the first metal ring on the surface of the first dielectric layer; (4) preparing the second dielectric layer on the surface of the first metal ring; (5) preparing the second metal ring on the surface of the second dielectric layer; (6) preparing the dielectric core layer on the surface of the second metal ring until fullness is achieved; (7) performing chemical mechanical polishing on the upper surfaces of the semiconductor substrate and the through silicon via. By adoption of the first metal ring which is arranged outside and grounded, a function of shielding noise signals is realized, and high integrity of high-frequency signals is achieved; by adoption of the second metal ring arranged inside, thermal stress is reduced, and thermo-mechanical property is improved.
Description
Technical field
The invention belongs to towards the three dimensional integrated circuits field of frequency applications, being related to through-silicon via structure and its manufacture method,
Specifically related to a kind of bicyclic through-silicon via structure and its manufacture method.
Background technology
In the decades in past, Size of Microelectronic Devices persistently reduces according to Moore's Law, and electronic product performance obtains sky
Front raising.But after semiconductor fabrication process size reduction to 16nm, Technology progressivelyes reach physics limit, and quantum is imitated
Should, the small-size effect such as short-channel effect increasingly highlight, become the bottleneck that Moore's Law continues development.Three dimensional integrated circuits is not
Another taste pursues small size, but to improve level of integrated system by the way of three-dimensional stacked, by silicon hole (Through-
Silicon-Via, abbreviation TSV) realize interlayer perpendicular interconnection, effectively shorten interconnection length, drastically increase circuit
Circuit power consumption and can be reduced, and the isomery collection of multiple difference in functionality module such as simulation, radio frequency, logic circuit can be realized
Become, also decrease with respect to device generations technical costss.Therefore, industry is become based on the three dimensional integrated circuits of silicon hole public
Recognize the future thrust of integrated circuit technique, be also the strong guarantee of Moore's Law continuous and effective.
But, in the manufacturing process of silicon hole, silicon hole and whole Semiconductor substrate need experience thermal cycle many times,
Last annealing (275 DEG C) and be cooled to room temperature (25 DEG C) process and can bring huge temperature load (- 250 to total
℃).Thermal coefficient of expansion due to metal material (especially copper) and Semiconductor substrate mismatches, and can the silicon around silicon hole serve as a contrast
Very big thermal stress is introduced, thus affecting carrier mobility and device performance and reliability in bottom.On the other hand, with collection
The continuous improvement of Cheng Du, silicon hole density increases considerably, and the coupling between signalling channel, crosstalk are consequently increased；With three
The raising of dimension operating frequency of integrated circuit, when being especially operated in millimeter wave or even submillimeter region, the parasitic ginseng of silicon hole itself
Amount impact, enough to flood whole signal transmission, has a strong impact on the signal integrity of signalling channel.
Existing through-silicon via structure can be divided into column type silicon hole, tapered silicon hole, ring-like silicon hole and coaxial at present
Silicon hole four type, wherein column type silicon hole, tapered silicon hole and ring-like silicon hole, due to the restriction in structure, do not have
The function of standby shielded signal noise, is only applicable to the situation of low frequency；And coaxial through-silicon via is due to the presence of outer ground becket,
Thus there are superior high frequency Charge Transport Properties, but introduce relatively in Semiconductor substrate around because metal proportion is bigger than normal
Big thermal stress.
Therefore, for the problems referred to above it is necessary to propose a kind of good thermomechanical property and high frequency signal integrity of having concurrently
Through-silicon via structure.
Content of the invention
Goal of the invention：The problem that the present invention is directed to above-mentioned prior art presence makes improvement, i.e. the first of the present invention mesh
For providing a kind of bicyclic through-silicon via structure.Second object of the present invention is to provide a kind of preparation side of bicyclic silicon hole
Method.Bicyclic silicon hole is reducing while thermal stress improves thermomechanical property it is ensured that superior high frequency signal integrity.
Technical scheme：A kind of bicyclic through-silicon via structure, be followed successively by from outside to inside quasiconductor liner body, first medium layer, first
Becket, second dielectric layer, the second becket and medium sandwich layer,
Described first medium layer is one of silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, described first medium layer
Thickness be 0.1～1 μm；
The thickness of described first becket is 1～3 μm；
Described second dielectric layer is one of silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, described second dielectric layer
Thickness be 1～3 μm；
The thickness of described second becket is 1～3 μm；
Described medium sandwich layer is silicon dioxide sandwich layer, one of nitridation silicon core layer, silicon oxynitride sandwich layer, described dielectric core
The radius of layer is 2～5 μm.
As a kind of preferred version of bicyclic through-silicon via structure a kind of in the present invention：Described quasiconductor liner body is silicon substrate.
As a kind of preferred version of bicyclic through-silicon via structure a kind of in the present invention：Described first becket is copper ring or aluminum
Ring.
As a kind of preferred version of bicyclic through-silicon via structure a kind of in the present invention：Described first becket ground connection, its work
With for shielding noise signal.
As a kind of preferred version of bicyclic through-silicon via structure a kind of in the present invention：Described second becket is copper ring or aluminum
Ring.Second becket is used for signal transmission, instead of the metal column within conventional coaxial silicon hole, decreases metal institute accounting
Weight, thus reducing silicon hole in the thermal mismatching of surrounding semiconductor substrate, reducing thermal stress, improve thermomechanical property.
A kind of manufacture method of bicyclic silicon hole, including：
(1) etching through hole by way of reactive ion on a semiconductor substrate, described through-hole aperture is 5.1～15 μm；
(2) inner surface in the described through hole of step (1) prepares first medium layer by CVD (Chemical Vapor Deposition) method；
(3) in the surface of the described first medium layer of step (2), the first becket is prepared by physical vapor deposition；
(4) in the surface of step (3) described first becket, second dielectric layer is prepared by CVD (Chemical Vapor Deposition) method；
(5) in the surface of the described second dielectric layer of step (4), the second becket is prepared by physical vapor deposition；
(6) in the surface of step (5) described second becket, medium sandwich layer is prepared by CVD (Chemical Vapor Deposition) method, until complete
Till entirely filling up；
(7) upper surface in described Semiconductor substrate and described silicon hole is chemically-mechanicapolish polished, and partly leads until described
Till after the upper surface of body substrate and described silicon hole is smooth.
Beneficial effect：The through-silicon via structure of the present invention, compared with other through-silicon via structures, has the beneficial effects that：Using outer layer
Earthing metal ring, realizes the effect of shielding noise signal, reaches higher high frequency signal integrity；Replaced using inner metal ring
Metal column within conventional coaxial silicon hole, reduces thermal stress, improves thermomechanical property.
Brief description
Fig. 1 is a kind of preparation flow figure of bicyclic silicon hole disclosed by the invention；
Fig. 2 is a kind of bicyclic through-silicon via structure schematic diagram disclosed by the invention；
Fig. 3～Fig. 9 is the AA ' profile in a kind of bicyclic through-silicon via structure manufacture process disclosed by the invention；
Wherein：
1- Semiconductor substrate 2- first medium layer
3- the first becket 4- second dielectric layer
5- the second becket 6- medium sandwich layer
Specific embodiment：
Below in conjunction with the accompanying drawings, the specific embodiment of the present invention is described in further detail.
Specific embodiment 1
As shown in Fig. 1 and Fig. 3～9, a kind of manufacture method of bicyclic silicon hole, including the following steps：
(1) etching through hole by way of reactive ion on semiconductor substrate 1, Semiconductor substrate 1 is silicon substrate, and it is high
Spend for 50 μm, length and width is 5mm；Through-hole aperture is 5.1 μm；The technique bar of reactive ion etching through hole in step (1)
Part is：Using fluoride or chloride gas, glow discharge decomposites fluorine atom or chlorine atom, reacts with surface silicon atoms
Generate gaseous products, reach the purpose of etching；Reacting gas pressure is 15～30 Pascals, reaction gas flow 10～40 milli
Liter/min, 200～350 watts of radio frequency power range.Meanwhile, heat exchanger and silicon chip back side helium gas cooling technology enter trip temperature control
System is it is ensured that whole temperature in etching process for the silicon chip is uniform, and stablizes at 150 DEG C about；
(2) inner surface in step (1) through hole prepares first medium layer 2, first medium layer 2 by CVD (Chemical Vapor Deposition) method
Using earth silicon material, its thickness be 0.1 μm, its act as between Semiconductor substrate 1 and silicon hole metal realize electricity every
From；In step (2), CVD (Chemical Vapor Deposition) method using the preferable high-density plasma chemical vapor deposition of step coverage or waits
Gas ions strengthen chemical vapor deposition, and its process conditions is, 300～400 DEG C of Process temperature ranges, and radio frequency power range 400～
550 watts, reacting gas flow velocity 200～300 ml/min；Plasma pressure is 60～133 Pascals；
(3) in the surface of step (2) first medium layer 2, first becket 3, the first gold medal are prepared by physical vapor deposition
Belong to ring 3 and adopt copper product, its thickness is 1 μm；First becket 3 is grounded, for shielding noise jamming, to obtain at high frequencies
To preferable signal integrity；In step (3), physical vapor deposition adopts ionized physical vapor deposition, its process conditions
For, 230～300 DEG C of temperature range, rf bias generator operation frequency is 1～100 megahertz, inert gas pressure is 4～
17 Pascals, reactant gas partial pressure is 0～7 Pascal；
(4) in the surface of step (3) first becket 3, second dielectric layer 4, second Jie are prepared by CVD (Chemical Vapor Deposition) method
Matter layer 4 is used for isolating double layer of metal ring；The process conditions of step (4) are identical with the process conditions of step (2)；
(5) in the surface of step (4) second dielectric layer 4, second becket 5, the second gold medal are prepared by physical vapor deposition
Belong to ring 5 and adopt copper product, its thickness is 1 μm, it is used for transmission signal, realizes three dimensional integrated circuits function；The technique of step (5)
Condition is identical with the process conditions of step (3)；
(6) in the surface of step (5) second becket 5, medium sandwich layer 6 is prepared by CVD (Chemical Vapor Deposition) method, until completely
Till filling up, medium sandwich layer 6 adopts earth silicon material, and its thickness is 2 μm；Medium sandwich layer 6 replacement conventional coaxial silicon hole
Metal part, reduces the thermal stress that silicon hole introduces, to improve the thermomechanical property of whole silicon hole；The technique bar of step (6)
Part is identical with the process conditions of step (2)；
(7) upper surface in Semiconductor substrate 1 and silicon hole is chemically-mechanicapolish polished, until Semiconductor substrate 1 and silicon
(not shown) till after the upper surface of through hole is smooth；Chemically mechanical polishing is divided into rough polishing, fine polishing and three steps of finishing polish,
Wherein：
The polishing condition of rough polishing is：Polish temperature：28～33 DEG C, polishing fluid pH value be：10.5～11.0；
The polishing condition of fine polishing is：Polish temperature：28～32 DEG C, polishing fluid pH value be：10.5～11.0；
The polishing condition of finishing polish is：Polish temperature：26～30 DEG C, polishing fluid pH value be：9.0～10.5.
A kind of through-silicon via structure having good thermomechanical property and high frequency signal integrity concurrently proposed by the present invention, such as Fig. 2
Shown, from inside to outside include quasiconductor liner body, first medium layer 2, the first becket 3, second dielectric layer 4, the second metal successively
Ring 5 and medium sandwich layer 6, wherein AA ' represents a hatching.
In sum, the present invention carries out signal transmission using the second becket 5 replacement conventional metals post, improves thermomechanical
Performance；First becket 3 ground connection plays the effect of shielding noise, improves high frequency signal integrity.
The through-silicon via structure of the present invention has good thermomechanical property, has data below as evidence：
In the present embodiment, bicyclic silicon hole maximum thermal stress introduced in Semiconductor substrate 1 around is 312MPa,
The conventional coaxial silicon hole being 5.1 μm of same material fillings than total radius reduces 74MPa, more same packing material than same radius
Traditional column type silicon hole reduce 147MPa, led to can not the region of making devices (stop because thermal stress is excessive
Area) it is 7.2 μm, reduce 1.6 μm (22.2%) than coaxial through-silicon via, reduce 2.4 μm (33.3%) than column type silicon hole.
The through-silicon via structure of the present invention has higher frequency signal integrity, has data below as evidence：
In the present embodiment, bicyclic silicon hole transmission coefficient (S21) is 5.1 μm when operating frequency is for 5GHz than total radius
Traditional column type silicon hole of same material filling improves 93%, improves 60% in operating frequency for 20GHz.
Specific embodiment 2
Preparation process is roughly the same with specific embodiment 1, and difference is that in step (1), through-hole aperture is 15 μm；
A kind of bicyclic through-silicon via structure, be followed successively by from outside to inside quasiconductor liner body, first medium layer 2, the first becket 3,
Second dielectric layer 4, the second becket 5 and medium sandwich layer 6,
First medium layer 2 is silicon nitride layer, and the thickness of first medium layer 2 is 1 μm；
The thickness of the first becket 3 is 3 μm；
Second dielectric layer 4 is silicon nitride layer, and the thickness of second dielectric layer 4 is 3 μm；
The thickness of the second becket 5 is 3 μm；
Medium sandwich layer 6 is nitridation silicon core layer, and the radius of medium sandwich layer 6 is 5 μm.
In the present embodiment, quasiconductor liner body is silicon substrate.
In the present embodiment, the first becket 3 is aluminium ring.
In the present embodiment, the first becket 3 is grounded, and it act as shielding noise signal.
In the present embodiment, the second becket 5 is aluminium ring.Second becket 5 is used for signal transmission, instead of conventional coaxial silicon
Metal column within through hole, decreases metal proportion, thus reducing silicon hole in the thermal mismatching of surrounding semiconductor substrate 1,
Reduce thermal stress, improve thermomechanical property.
Specific embodiment 3
Preparation process is roughly the same with specific embodiment 1, and difference is that in step (1), through-hole aperture is 9.5 μm；
A kind of bicyclic through-silicon via structure, be followed successively by from outside to inside quasiconductor liner body, first medium layer 2, the first becket 3,
Second dielectric layer 4, the second becket 5 and medium sandwich layer 6,
First medium layer 2 is silicon oxynitride layer, and the thickness of first medium layer 2 is 0.5 μm；
The thickness of the first becket 3 is 2 μm；
Second dielectric layer 4 is silicon oxynitride layer, and the thickness of second dielectric layer 4 is 2 μm；
The thickness of the second becket 5 is 2 μm；
Medium sandwich layer 6 is silicon oxynitride sandwich layer, and the radius of medium sandwich layer 6 is 3 μm.
In the present embodiment, quasiconductor liner body is silicon substrate.
In the present embodiment, the first becket 3 is aluminium ring.
In the present embodiment, the first becket 3 is grounded, and it act as shielding noise signal.
In the present embodiment, the second becket 5 is aluminium ring.Second becket 5 is used for signal transmission, instead of conventional coaxial silicon
Metal column within through hole, decreases metal proportion, thus reducing silicon hole in the thermal mismatching of surrounding semiconductor substrate 1,
Reduce thermal stress, improve thermomechanical property.
Above are only the preferred embodiments of the present invention, and be not used to limit the scope of patent protection of the present invention.Any
Person of ordinary skill in the field, in the range of without departing from technical solution of the present invention, to the invention discloses technical scheme
Make any type of equivalent or modification etc. with technology contents to change, all belong to the content without departing from technical solution of the present invention, still
Belong within protection scope of the present invention.
Claims (1)
1. a kind of manufacture method of bicyclic silicon hole, comprises the following steps：
(1) etching through hole by way of reactive ion on a semiconductor substrate, described through-hole aperture is 5.1～15 μm, wherein
The process conditions of etching through hole are：Using fluoride or chloride gas, glow discharge decomposites fluorine atom or chlorine atom,
React generation gaseous products with surface silicon atoms, reach the purpose of etching；Reacting gas pressure is 15～30 Pascals, reaction gas
Body flow 10～40 ml/min, 200～350 watts of radio frequency power range；
(2) inner surface in the described through hole of step (1) prepares first medium layer by CVD (Chemical Vapor Deposition) method, its process conditions
For：300～400 DEG C of Process temperature ranges, 400～550 watts of radio frequency power range, reacting gas flow velocity 200～300 ml/min
Clock, plasma pressure is 60～133 Pascals；
(3) in the surface of the described first medium layer of step (2), the first becket, its technique bar are prepared by physical vapor deposition
Part is：230～300 DEG C of temperature range, rf bias generator operation frequency is 1～100 megahertz, and inert gas pressure is 4
～17 Pascals, reactant gas partial pressure is 0～7 Pascal；
(4) in the surface of step (3) described first becket, second dielectric layer, its technique bar are prepared by CVD (Chemical Vapor Deposition) method
Part is：300～400 DEG C of Process temperature ranges, 400～550 watts of radio frequency power range, 200～300 milliliters of reacting gas flow velocity/
Minute, plasma pressure is 60～133 Pascals；
(5) in the surface of the described second dielectric layer of step (4), the second becket, its technique bar are prepared by physical vapor deposition
Part is：230～300 DEG C of temperature range, rf bias generator operation frequency is 1～100 megahertz, and inert gas pressure is 4
～17 Pascals, reactant gas partial pressure is 0～7 Pascal；
(6) in the surface of step (5) described second becket, medium sandwich layer is prepared by CVD (Chemical Vapor Deposition) method, until filling out completely
Till full, its process conditions is：300～400 DEG C of Process temperature ranges, 400～550 watts of radio frequency power range, reacting gas stream
Fast 200～300 ml/min, plasma pressure is 60～133 Pascals；
(7) upper surface in described Semiconductor substrate and described silicon hole is chemically-mechanicapolish polished, until described quasiconductor lining
Till after the upper surface of bottom and described silicon hole is smooth, wherein：
Chemically mechanical polishing is divided into rough polishing, fine polishing and three steps of finishing polish, wherein：
The polishing condition of rough polishing is：Polish temperature：28～33 DEG C, polishing fluid pH value be：10.5～11.0；
The polishing condition of fine polishing is：Polish temperature：28～32 DEG C, polishing fluid pH value be：10.5～11.0；
The polishing condition of finishing polish is：Polish temperature：26～30 DEG C, polishing fluid pH value be：9.0～10.5；
The bicyclic through-silicon via structure obtaining is followed successively by quasiconductor liner body, first medium layer, the first becket, second Jie from outside to inside
Matter layer, the second becket and medium sandwich layer,
Described first medium layer is one of silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, the thickness of described first medium layer
Spend for 0.1 μm；
The thickness of described first becket is 1 μm；
Described second dielectric layer is one of silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, the thickness of described second dielectric layer
Spend for 1 μm；
The thickness of described second becket is 1 μm；
Described medium sandwich layer is silicon dioxide sandwich layer, one of nitridation silicon core layer, silicon oxynitride sandwich layer, described medium sandwich layer
Radius is 2 μm；Wherein：
Described quasiconductor liner body is silicon substrate；
Described first becket is copper ring or aluminium ring；
Described first becket ground connection；
Described second becket is copper ring or aluminium ring.
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| CN104965955B (en) * | 2015-07-15 | 2017-12-08 | 西安电子科技大学 | Static Timing Analysis Methodology containing silicon hole thermal stress circuit |
| CN108964627B (en) * | 2018-06-06 | 2022-03-15 | 杭州电子科技大学 | RC passive equalizer structure for shielding differential silicon through hole and design method thereof |
| CN112397444A (en) * | 2020-11-16 | 2021-02-23 | 西安电子科技大学 | Low-crosstalk silicon through hole structure and manufacturing method thereof |
| CN115602643A (en) * | 2021-07-07 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Heat dissipation structure, forming method of heat dissipation structure and semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554824A (en) * | 1992-01-07 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | IC package and packaging method for the same |
| CN102598245A (en) * | 2009-10-28 | 2012-07-18 | 国际商业机器公司 | Coaxial through-silicon via |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554824A (en) * | 1992-01-07 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | IC package and packaging method for the same |
| CN102598245A (en) * | 2009-10-28 | 2012-07-18 | 国际商业机器公司 | Coaxial through-silicon via |
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