CN104103317B - Nonvolatile memory and operating method thereof - Google Patents
Nonvolatile memory and operating method thereof Download PDFInfo
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- CN104103317B CN104103317B CN201310126077.9A CN201310126077A CN104103317B CN 104103317 B CN104103317 B CN 104103317B CN 201310126077 A CN201310126077 A CN 201310126077A CN 104103317 B CN104103317 B CN 104103317B
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Abstract
The invention discloses a method for transforming the distribution of a threshold voltage by a nonvolatile memory of a multilayer store unit (MLC) according to a preset coding table before programming. The method comprises the following steps: grouping a plurality of store units, wherein the store units have a same first voltage in advance and are in a same major state; groping the store units in a preselected major state as a same next state when the store units in the preselected major state have a same preset second potential; and improving the first potential of the store units to a voltage, wherein the improved store units have a highest preset second voltage, and the voltage is higher than a preset highest major state voltage.
Description
Technical field
The present invention is with regard to a kind of method of operation nonvolatile memory；Specifically, it is to be applied to Multi-layer Store unit
(MLC) nonvolatile memory.
Background technology
The storage capacity of nonvolatile memory has been promoted to the access more than per second hundred times, thus result in process progress it is quick and
The technology of development Multi-layer Store unit (MLC).Basic methods and double-deck storage element (BLC) using Multi-layer Store monotechnics
Technology it is similar, except Multi-layer Store monotechnics can make single storage element storage by charging to different voltage levels
Various positions rather than two kinds of positions.In general, MLC technology can be by using 2n- 1 threshold voltage (Vt) is distinguishing 2nPlant shape
State, for storage 2nThe voltage level of (n ＞ 1).Fig. 1 is displayed in a preferable threshold voltage of two positions in MLC storage elements
(Vt) it is distributed.The place value of one storage element is determined via voltage window, and the threshold voltage of the storage element then position
At the voltage window place.
However, in fact, with the size reduction and each storage element of storage element can store more multidigit when, application
The threshold voltage window of BLC technologies is then become less than in the threshold voltage window for distinguishing each place value.Due to using BLC and MLC
Device can use the voltage window of formed objects, therefore the distance in MLC between neighbouring voltage level is significantly less than in MLC
Distance.Additionally, other factorses, such as fabrication error, program interference or second interference effect all may skew or interference thresholds
Voltage, and then make the distance of differentiation different conditions become less.
Fig. 2 shows the threshold voltage distribution of known two MLC nonvolatile storages, wherein the storage element after programming can
Four major states 1,2,3 and major state 4 are divided into according to primary threshold voltage.Each major state can be by four kinds of different next states
N1, n2, n3 and n4 are constituted, and the next state is grouped according to second threshold voltage.In general, the first major state 1
With minimum threshold voltage, and it is easiest to be interfered and be not easy to restrain its distribution.Therefore the one of the first major state 1
Part may be overlapped in the second major state 2., it is clear that in MLC storage elements, detecting voltage level, follow single in BLC storages
Detecting voltage level is compared more complicated in first.Therefore, for determine storage element magnitude of voltage detecting, how to reduce detecting
Error become more and more important.
The content of the invention
The invention provides a kind of nonvolatile memory of Multi-layer Store unit (MLC) basis before programming presets
Coding schedule (coding table) conversion threshold voltage distribution method, methods described includes the multiple storage elements of packet,
And be set in advance under identical major state, the storage element has first voltage of identical.Additionally, methods described is additionally comprised
If the storage element under a pre-selection major state has identical second voltage set in advance, the pre-selection is grouped
The storage element under major state is identical next state.Then, methods described presets again comprising raising with highest
Second voltage the storage element first voltage to a voltage, and the voltage presets higher than described
The voltage of highest major state.
Another open a kind of nonvolatile memory for Multi-layer Store unit (MLC) of the invention, promotion threshold value voltage window
Method.The method is included and presets coding schedule according to one, obtains the voltage after a programming of each storage element；Then,
Multiple storage elements are screened, wherein the storage element has first voltage of identical.The method is additionally comprised according to each storage
The second voltage of memory cell, distinguishes the storage element after the screening.Additionally, the method has highest second comprising lifting again
First voltage of the storage element of position voltage is to a high voltage.Just because of this, it is described with different first
The threshold voltage of the storage element of voltage, can't be overlapped after first voltage is lifted.
Description of the drawings
Fig. 1 discloses a kind of schematic diagram of the distribution of threshold voltage (Vt) level of two MLC storage elements in ideal；
Fig. 2 shows the schematic diagram of the threshold voltage distribution of known two MLC nonvolatile storages；
Fig. 3 shows the schematic diagram of two non-volatile memory arrays；
Fig. 4 shows the schematic diagram that the threshold voltage with n kind major states is distributed in MLC nonvolatile storages；
Fig. 5 shows the schematic diagram of the threshold voltage distribution of an embodiment of the invention；
Fig. 6 shows the schematic diagram of threshold voltage distribution according to another embodiment of the present invention；
Fig. 7 shows the flow chart of an embodiment of the invention；
Fig. 8 shows flow chart according to another embodiment of the present invention；And
Fig. 9 A-9C show the schematic diagram of the threshold voltage distribution of an embodiment of the invention.
Main element symbol description
1 major state
2 major states
3 major states
4 major states
305 storage elements
305-1 left sides storage area
305-2 right sides storage area
1i next states
V11_L lower boundary voltages
V1_L lower boundary voltages
The high boundary voltages of V1i_U
The high boundary voltages of V1_U
The high boundary voltages of Vn_U
Δ V2-1 windows
H major states
C is distributed
C ' distributions
C " is distributed
Specific embodiment
Invention will be described with reference to the accompanying figures.
Embodiments of the invention are described more fully below in reference to accompanying drawing, it is described to wait accompanying drawing to form a part of the invention,
And by way of illustration displaying can put into practice the particular instantiation embodiment of the present invention.However, the present invention can be in many different forms
To embody, and should not be construed as limited by embodiments set forth herein；In fact, these embodiments are provided such that this
It is bright by for comprehensive and complete, and will comprehensively pass on scope of the invention to those who familiarize themselves with the technology.As used herein, art
Language "or" be inclusive inclusive-OR operation son, and be equivalent to term " and/or ", clearly describe unless the context otherwise.Additionally, whole
In individual description, the implication of " " and " described " includes multiple references.
The explanation of embodiments of the invention and method refers to Fig. 3 to 9.It should be noted that the present invention is not intended to limit this
It is bright in the out of the ordinary embodiment for disclosing, and the present invention also can implement this using further feature, element, method and embodiment
It is bright.
Fig. 3 shows one or two non-volatile memory array, and it contains multiple storage elements 305.Each storage element 305 is wrapped
Containing an a left side storage area 305-1 and right side storage area 305-2, capture electric charge (trapped charges) is also housed in it.It is left
Storage area 305-1 in side is considered as first, and storage area 305-2 in right side is considered as second.According to the present invention, the storage list of a unit
Unit includes at least two, but the present invention is then illustrated using two storage elements as example, but is not limited to the storage of two
Unit.Each storage element 305 after programming, due to the quantity in storage area IT electric charge by according to different threshold values electricity
Pressure.In general, the storage element system with identical first threshold voltage is grouped in identical major state.Furthermore, it is understood that
It is can to divide into different next states according to second threshold voltage positioned at the storage element of identical major state.
Fig. 4 shows the threshold voltage distribution of a MLC nonvolatile storages, and it has according to a coding schedule set in advance
N kind major states.The distribution of the first major state 1 includes a high boundary voltage V1_UAnd a lower boundary voltage V1_L.The major state 1 is wrapped
The next state of kind containing i, and each next state represents in the present invention with code name 1i.Next state is the flash according to each next state
Boundary's voltage from low to high, is arranged with the order of 1 to i.First next state (11 or 1 [1]) is containing minimum lower boundary voltage V11_L,
This lower boundary voltage V11_LAlso it is the lower boundary voltage V in the first major state1_L, therefore V11_L=V1_L.I ＆ lt state is (for example
1i) there is the high boundary voltage V of highest in all next states in major state 11i_U.The high boundary voltage of the first major state
V1_UAlso it is the high boundary voltage V of next state 1i1i_U.Highest major state n contains a high boundary voltage Vn_U, it is in original state
The ceiling voltage state of middle whole storage elements, original state is referred to before programming for the first time.Voltage window is then defined as each master
Distance between the high boundary voltage of state and the lower boundary voltage of the major state on the right side of it.For example, Δ V2-1Represent the first master
Window between state and the second major state.
Before programming, first screen higher time that memory storage unit is scheduled to be charged under a default major state
State, such as next state 1i.It is electric to higher voltage via its first voltage that charges in the voltage of next state 1i of major state 1
Put down and lifted, therefore the lower boundary voltage V after its lifting1i_LIt is above the high boundary voltage V of highest major staten_U.Fig. 5 shows
Threshold voltage distribution after highest next state 1i to higher voltage level for lifting the first major state 1.Now, the first major state
1 high boundary voltage V1_UIt is then the high boundary voltage (signable is 1 [i-1]) of the i-th -1 next state.First major state 1 and second
Distance, delta V between major state 22-1(it is V substantially to increase Δ V1i_UDeduct V1[i-1]_U), therefore the first major state 1 and the second main shape
Distance between state 2 is by Δ V2-1Increase to Δ V+ Δ V2-1。
Electricity further to increase the distance between the first major state 1 and the second major state 2, except lifting i ＆ lt state
Outside voltage level, the storage element of the i-th -1 next state also can be by other first voltage in charge storage unit in major state 1
High voltage is promoted to high-voltage level so that flash of the lower boundary voltage of the i-th -1 next state higher than highest major state
Boundary voltage Vn_U, such as V1[i-1]_L＞ Vn_U.Next state after lifting can be grouped major state (referred to as H major states) another in formation.
Fig. 6 is displayed in the i ＆ lt state of the first major state 1 and the i-th -1 next state is moved to the threshold voltage after higher voltage level point
Cloth, to form H major states.The high boundary voltage of the first major state 1 can be determined by the high boundary voltage of the i-th -2 next state, because
Distance between this major state 2 of the first major state 1 and second further increases to Δ V+ Δ V2-1, wherein Δ V=V1i_U-V1[i-2]_U,
And the first major state 1 and the second major state 2 is more easily discriminated between and is come.
According to the present invention, 1 in the first major state kind next state can be promoted to one higher than Vn_UVoltage, wherein 1≤i,
It is available for distinguishing its major state adjacent thereto based on window.
Method for lifting next state voltage can be adjusted to the major state for being suitable to any xth, wherein 1≤x≤n-1.
Fig. 7 shows flow chart according to an embodiment of the invention.In step 200, Multi-layer Store unit (MLC) is first obtained
Nonvolatile memory by coding threshold voltage distribution.This distribution can be divided into multiple major states.With identical first
The different storage elements of voltage are then divided into one group.Each major state includes various next states, with identical first voltage and phase
The different storage elements of same second voltage are then divided into same group.In step 300, a major state is screened.In step 400
In, highest next state is promoted to a higher voltage level in the major state of screening, and its voltage level is higher than highest major state, and
Form a H major states.One selection step 500 may be included in the method for lifting second highest screened in major state
Next state, and packet be main state in H.
Fig. 8 shows another embodiment of the present invention.Step 100 can add the method before programming, to remove non-volatile memory
The electric charge of storage element in device array, and in each step as shown in Figure 7 that continues.
Fig. 9 A show that a major state is distributed C, the distribution of its MLC nonvolatile storage before programming.It has the main shape of n kinds
State, includes i kind next states in major state.Some high level next states, such as 1i, 1 [i-1] and 1 [i-2] are and the second major state
Overlap.One removal step can be removed any capture electric charge being detained in the trapping layer of local, and described local trapping layer can be one
Nitride layer or an ONO (oxide-nitride-oxide) layer, therefore distribution C can again mould (reshaped) into such as Fig. 9 B institutes
The different distribution C ' for showing, wherein the first major state has one compared with long streaking compared to distribution C.Lower boundary voltage V1_LTo left avertence
Move and have state (being 1i in this embodiment) at least one times overlap with the second major state 2.Fig. 9 C show, in the step for applying such as Fig. 7
After rapid, the distribution C of the first major state 1 ".Plurality of higher level state is promoted to a high voltage for being higher than highest major state n.First
Distance between the major state 2 of major state 1 and second further passes through, and the removal step before lifting next state 1i and 1 [i-1] is able to
Increase, therefore it is elevated to distinguish the ability of the first major state and the second major state.
Fully describe the method for the present invention and feature in examples detailed above and description.It should be understood that without departing from the present invention's
Any modification or change of spirit is intended to cover in the protection category of the present invention.
Claims (14)
1. a kind of nonvolatile memory of Multi-layer Store unit (MLC) in programming before according to coding schedule set in advance
The method of the conversion threshold voltage distribution of (coding table), comprising：
Multiple storage elements are grouped, the multiple storage elements being set in advance under identical major state have one first electricity of identical
Pressure；
If the storage element under a pre-selection major state has identical second voltage set in advance, institute is grouped
It is identical next state to state the storage element under pre-selection major state；And
First voltage of the storage element is improved to a voltage, wherein there is the storage element highest to preset
Second voltage, and the voltage higher than the major state set in advance maximum voltage value.
2. method according to claim 1, wherein the major state is one first major state, first major state is in it
There is lowest voltage level between its major state.
3. method according to claim 1, wherein including i kind next states, the i kinds next state in the pre-selection major state
It is, according to the high boundary voltage of each next state, to be arranged with the order of 1 to i, wherein the i ＆ lt state has highest border
Voltage.
4. method according to claim 3, further comprising a step, it is one electric that the step lifts the i-th -1 next state
Pressure, the voltage is higher than the voltage for presetting major state with maximum voltage value.
5. method according to claim 4, further comprising a step, the step forms one second major state, described
Second major state has a lower boundary voltage, and the lower boundary voltage is higher than the high border electricity for presetting highest major state
Pressure.
6. method according to claim 5, further comprising a step, the step is grouped described in the major state
The i-th and i-1 next state after lifting.
7. method according to claim 1, further comprising a step, the step lifts at least two next states to one
Voltage, the voltage is higher than the high boundary voltage for presetting highest major state.
8. method according to claim 1, further comprising a step, the step is in lifting first voltage
Before, remove the capture electric charge (trapped charges) in the nonvolatile memory.
9. the method that one kind supplies the nonvolatile memory promotion threshold value voltage window of Multi-layer Store unit (MLC), comprising：
Coding schedule is preset according to one, the voltage after a programming of each storage element is obtained；
Multiple storage elements are screened, wherein the multiple storage elements being set in advance under identical major state have identical one first
Position voltage；
According to a second voltage of each storage element, the storage element after the screening is distinguished, with the second voltage
The storage element tie up under identical next state；And
First voltage of the storage element with highest second voltage is lifted to a high voltage.
10. method according to claim 9, further comprising a step, the step is lifted has the second highest second
First voltage of the storage element of position voltage is to a high voltage.
11. methods according to claim 9, wherein the threshold voltage of a part for the storage element after the screening, in
The voltage of the storage element without screening is overlapped in before lifting step.
12. methods according to claim 9, wherein first voltage of the lifting presets coding schedule higher than described
The peak of set first voltage.
13. methods according to claim 9, further comprising a step, the step is in lifting first voltage
Before, remove the capture electric charge (trapped charges) in the nonvolatile memory.
14. methods according to claim 9, wherein the threshold value with different first voltage of the storage element
Voltage, after lifting first voltage, and does not overlap with.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101095197A (en) * | 2004-12-23 | 2007-12-26 | 桑迪士克股份有限公司 | Nand-eeprom with reduction of floating gate to floating gate coupling effect |
| CN101656107A (en) * | 2008-08-21 | 2010-02-24 | 旺宏电子股份有限公司 | Method for reading and programming a memory |
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| US8228727B2 (en) * | 2009-11-20 | 2012-07-24 | Macronix International Co., Ltd. | Method for programming multi-level cell and memory apparatus |
| US8498152B2 (en) * | 2010-12-23 | 2013-07-30 | Sandisk Il Ltd. | Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101095197A (en) * | 2004-12-23 | 2007-12-26 | 桑迪士克股份有限公司 | Nand-eeprom with reduction of floating gate to floating gate coupling effect |
| CN101656107A (en) * | 2008-08-21 | 2010-02-24 | 旺宏电子股份有限公司 | Method for reading and programming a memory |
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