CN104078441A - Integrated inductor structure and manufacturing method thereof - Google Patents
Integrated inductor structure and manufacturing method thereof Download PDFInfo
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- CN104078441A CN104078441A CN201310105936.6A CN201310105936A CN104078441A CN 104078441 A CN104078441 A CN 104078441A CN 201310105936 A CN201310105936 A CN 201310105936A CN 104078441 A CN104078441 A CN 104078441A
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Abstract
The invention discloses an integrated inductor structure and a manufacturing method of the integrated inductor structure. The integrated inductor structure comprises a semiconductor substrate, multiple through-silicon through holes and an inductor. The through-silicon through holes are formed in the semiconductor substrate and arranged to form a specific pattern and are filled with metal materials to form pattern type ground connection protection, and the inductor is formed above the semiconductor substrate. The manufacturing method of the integrated inductor structure comprises the steps of forming the semiconductor substrate, forming through-silicon through holes in the semiconductor substrate, arranging the through-silicon through holes into the specific pattern, filling the through-silicon through holes with the metal materials to form the pattern type ground connection protection, and forming the inductor above the semiconductor substrate.
Description
Technical field
The present invention has about a kind of integrated inductance structure and a kind of integrated inductance structure manufacture method, relate to especially a kind of integrated inductance structure and a kind of integrated inductance structure manufacture method of the patterned ground protection (Patterned Ground Shield, PGS) with innovation.
Background technology
Along with IC manufactures towards system single chip (SoC) future development, the passive devices such as integrated inductor (integrated inductor) by extensive integration and making in high-frequency integrated circuit.Because IC manufactures the general structure that adopts silicon base, integrated inductor exists low quality factor (Q-factor) problem because of substrate loss.
Therefore, someone proposes patterned ground protection layer (the Patterned Ground Shield that utilizes polysilicon (polysilicon) metal to form, PGS), reduce the electromagnetic eddy current (eddy current) of integrated inductor, use raising quality factor, for instance, please refer to Fig. 1, a generalized section of the integrated inductance structure 50 disclosing for No. 8106479 for United States Patent (USP) that Fig. 1 illustrates.As shown in Figure 1, patterned ground protection 22 is formed between inductance 30 and grid oxic horizon 24, but, patterned ground protection 22 is like this very poor for the barrier effect of electromagnetic eddy current that is formed at semiconductor base 10 mid-deep stratas, and the material of patterned ground protection 22 in Fig. 1 is polysilicons, cannot effectively reduce electromagnetic eddy current.
Summary of the invention
In view of this, main purpose of the present invention is providing a kind of integrated inductance structure and a kind of integrated inductance structure manufacture method, it has patterned ground protection (the Patterned Ground Shield of innovation, PGS), can reduce electromagnetic eddy current (eddy current) and improve quality factor (Q-factor).
Disclose a kind of integrated inductance structure according to the present invention, this integrated inductance structure includes: semiconductor substrate, multiple straight-through silicon wafer perforation (Through Silicon Via, TSV) and an inductance.The plurality of straight-through silicon wafer perforation is formed in this semiconductor base and is arranged in a specific pattern, and fills a metal material in the plurality of straight-through silicon wafer perforation, to form a patterned ground protection (Patterned Ground Shield, PGS); And this inductance is formed at this semiconductor base top.
Also disclose a kind of integrated inductance structure manufacture method according to the present invention, this integrated inductance structure manufacture method includes: form semiconductor substrate; In this semiconductor base, form multiple straight-through silicon wafer perforation (Through Silicon Via, TSV), and the plurality of straight-through silicon wafer perforation pattern is become to a specific pattern; In the plurality of straight-through silicon wafer perforation, fill a metal material, to form a patterned ground protection (Patterned Ground Shield, PGS); And form an inductance in this semiconductor base top.
In sum, compared to prior art, because disclosed integrated inductance structure and integrated inductance structure manufacture method have patterned ground protection (the Patterned Ground Shield of innovation, PGS), can intercept the formation of the electromagnetic eddy (eddy current) of semiconductor base mid-deep strata, and can block the contingent path of electromagnetic eddy, block effect more thorough, and improve quality factor (Q-factor).
Brief description of the drawings
One generalized section of the integrated inductance structure disclosing for No. 8106479 for United States Patent (USP) that Fig. 1 illustrates.
The generalized section for a kind of integrated inductance structure according to one first embodiment of the present invention that Fig. 2 illustrates.
Fig. 3 is a structure vertical view of the integrated inductance structure of the first embodiment of the present invention.
What Fig. 4 illustrated is the flow chart of summarizing one first embodiment of integrated inductance structure manufacture method of the present invention according to the integrated inductance structure of the first embodiment of the present invention.
The generalized section for a kind of integrated inductance structure according to one second embodiment of the present invention that Fig. 5 illustrates.
Fig. 6 is a structure vertical view of the integrated inductance structure of the second embodiment of the present invention.
The generalized section for a kind of integrated inductance structure according to of the present invention 1 the 3rd embodiment that Fig. 7 illustrates.
Fig. 8 is a structure vertical view of the integrated inductance structure of the second embodiment of the present invention.
The integrated inductance structure for the second embodiment according to the invention described above that Fig. 9 illustrates is summarized the flow chart of one second embodiment of integrated inductance structure manufacture method of the present invention.
The generalized section for a kind of integrated inductance structure according to of the present invention 1 the 4th embodiment that Figure 10 illustrates.
Figure 11 is a structure vertical view of the integrated inductance structure of the fourth embodiment of the present invention.
What Figure 12 illustrated is a rough schematic view that is applied to Flip Chip according to the integrated inductance structure of the fourth embodiment of the present invention.
What Figure 13 illustrated is the flow chart of summarizing one the 4th embodiment of integrated inductance structure manufacture method of the present invention according to the integrated inductance structure of the fourth embodiment of the present invention.
The generalized section for a kind of integrated inductance structure 900 according to of the present invention 1 the 5th embodiment that Figure 14 illustrates.
Figure 15 is a structural base vertical view of the integrated inductance structure of the fifth embodiment of the present invention.
What Figure 16 illustrated is a rough schematic view that is applied to a three-dimensional chip according to the integrated inductance structure of the fifth embodiment of the present invention.
What Figure 17 illustrated is the flow chart of summarizing one the 5th embodiment of integrated inductance structure manufacture method of the present invention according to the integrated inductance structure of the fifth embodiment of the present invention.
What Figure 18 illustrated is a rough schematic view that is applied to a three-dimensional chip according to the integrated inductance structure of embodiments of the invention.
Wherein, description of reference numerals is as follows:
10: semiconductor base
22: patterned ground protection
24: grid oxic horizon
30: inductance
50: integrated inductance structure
200: integrated inductance structure
202: semiconductor base
204: deep trench
206: inductance
208: patterned ground protection
500: integrated inductance structure
502: semiconductor base
504: straight-through silicon wafer perforation
506: inductance
508: patterned ground protection
510: cover metal layer pattern
700: integrated inductance structure
702: semiconductor base
704: metal level heavily distributes
706: inductance
708: patterned ground protection
720: the first chips
730: the second chips
900: integrated inductance structure
902: semiconductor base
904: straight-through silicon wafer perforation
906: inductance
908: patterned ground protection
910: the back side metal level that heavily distributes
920: three-dimensional chip
930: the first chips
940: silicon plug-in unit
950: the second chips
1120: three-dimensional chip
1130: the first chips
1140: silicon plug-in unit
1150: the second chips
Embodiment
Please refer to Fig. 2, the generalized section for a kind of integrated inductance structure 200 according to one first embodiment of the present invention that Fig. 2 illustrates.As shown in Figure 2, integrated inductance structure 200 includes: semiconductor substrate 202, multiple deep trench (deep trench) 204 and an inductance 206.The plurality of deep trench 204 is formed in semiconductor base 202 and is arranged in a specific pattern (for instance, as shown in Figure 3, Fig. 3 is a structure vertical view of integrated inductance structure 200, but the invention is not restricted to this), and in the plurality of deep trench 204, fill a metal material (for example copper, aluminium or gold or its alloy etc.), to form a patterned ground protection (Patterned Ground Shield, PGS) 208, wherein the width of the plurality of deep trench 204 can be less than 20 microns, and the degree of depth of the plurality of deep trench 204 can be as being less than 100 microns but be greater than 20 microns, and inductance 206 is formed at semiconductor base 202 tops.In addition, in the present invention, between inductance 206 and semiconductor base 202, can not there is other any unnecessary patterned ground protections.Please note, the above embodiments only illustrate as of the present invention, are not restrictive condition of the present invention, for instance, also ground connection in addition of patterned ground protection 208, further to reduce electromagnetic eddy current (eddy current) and to improve quality factor (Q-factor).See Fig. 2 and 3, preferably, wherein patterned ground protection 208 below this inductance 206 orthogonal with it (vertical) in fact.
Different from the past, because current sophisticated semiconductor technology can be produced the minimum deep trench of width, therefore the present invention can make the deep trench 204 with this specific pattern by this in semiconductor base 200, and in deep trench 204, fill this metal material, to form the patterned ground protection of innovation, be arranged at the patterned ground protection (please refer to Fig. 1) between inductance and grid oxic horizon for replacing conventional art with polysilicon.
Please refer to Fig. 4, what Fig. 4 illustrated is the flow chart of summarizing one first embodiment of integrated inductance structure manufacture method of the present invention according to above-mentioned integrated inductance structure 200, if can obtain substantially identical result, the step in flow process not necessarily needs to carry out according to the order shown in Fig. 4, also it is continuous not necessarily needing, that is to say, between these steps, can insert other step.The first embodiment of integrated inductance structure manufacture method of the present invention includes the following step:
Step 400: form semiconductor substrate.
Step 402: form multiple deep trench in this semiconductor base, and the plurality of deep trench is arranged in to a specific pattern.
Step 404: fill a metal material in the plurality of deep trench, to form a patterned ground protection.
Step 406: form an inductance in this semiconductor base top.
Note that the above embodiments only illustrate as of the present invention, is not restrictive condition of the present invention, and for instance, the step of integrated inductance structure manufacture method of the present invention can separately include: by this patterned ground protection ground connection.Preferably, this patterned ground protection below this inductance orthogonal with it (vertical) in fact wherein.
Please refer to Fig. 5, the generalized section for a kind of integrated inductance structure 500 according to one second embodiment of the present invention that Fig. 5 illustrates.As shown in Figure 5, integrated inductance structure 500 includes: semiconductor substrate 502, multiple straight-through silicon wafer perforation (Through Silicon Via, TSV) 504 and an inductance 506.The plurality of straight-through silicon wafer perforation 504 is formed in semiconductor base 500 and is arranged in a specific pattern (for instance, as shown in Figure 6, Fig. 6 is a structure vertical view of integrated inductance structure 500, but the invention is not restricted to this), and in the plurality of straight-through silicon wafer perforation 504, fill a metal material (such as copper, aluminium or gold etc.), to form a patterned ground protection (Patterned Ground Shield, PGS) 508, wherein the width of the plurality of straight-through silicon wafer perforation 504 can be less than 20 microns, and inductance 506 is formed at semiconductor base 502 tops.Note that in the present invention between inductance 506 and semiconductor base 502, not there is other any unnecessary patterned ground protections.In addition, integrated inductance structure 500 of the present invention can be applied to the silicon plug-in unit (Si Interposer) in a three-dimensional chip (3D IC).Please note, the above embodiments only illustrate as of the present invention, are not restrictive condition of the present invention, for instance, also ground connection in addition of patterned ground protection 508, to reduce more significantly electromagnetic eddy current (eddy current) and to improve quality factor (Q-factor).In addition, in of the present invention 1 the 3rd embodiment, integrated inductance structure 500 can also separately include: one covers metal layer pattern 510, connect the plurality of straight-through silicon wafer perforation 504 according to this specific pattern, as shown in Figure 7, and this covers metal layer pattern 510 also can form patterned ground protection 508 jointly with the plurality of straight-through silicon wafer perforation 504, as shown in Figure 8; And preferably, patterned ground protection 508 cover metal layer pattern 510 below this inductance 506 orthogonal with it (vertical) in fact.Wherein, this metal level for example can form with the first layer metal in semiconductor technology (metal1).
Different from the past, because current sophisticated semiconductor technology can be produced the minimum straight-through silicon wafer perforation of width, therefore the present invention can make the straight-through silicon wafer perforation 504 with this specific pattern by this in semiconductor base 500, and fill this metal material in straight-through silicon wafer perforation 504, to form the patterned ground protection of innovation, be arranged at the patterned ground protection (please refer to Fig. 1) between inductance and grid oxic horizon for replacing conventional art with polysilicon.
Please refer to Fig. 9, what Fig. 9 illustrated is the flow chart of summarizing one second embodiment of integrated inductance structure manufacture method of the present invention according to above-mentioned integrated inductance structure 500, if can obtain substantially identical result, the step in flow process not necessarily needs to carry out according to the order shown in Fig. 9, also it is continuous not necessarily needing, that is to say, between these steps, can insert other step.The second embodiment of integrated inductance structure manufacture method of the present invention includes the following step:
Step 600: form semiconductor substrate.
Step 602: form multiple straight-through silicon wafer perforation in this semiconductor base, and the plurality of straight-through silicon wafer perforation pattern is become to a specific pattern.
Step 604: fill a metal material in the plurality of straight-through silicon wafer perforation, to form a patterned ground protection.
Step 606: form an inductance in this semiconductor base top.
Note that the above embodiments only illustrate as of the present invention, is not restrictive condition of the present invention, and for instance, the step of integrated inductance structure manufacture method of the present invention can separately include: by this patterned ground protection ground connection.In addition,, in of the present invention 1 the 3rd embodiment, integrated inductance structure manufacture method of the present invention can separately include: cover metal layer pattern according to this specific pattern by one and be connected in the plurality of straight-through silicon wafer perforation.And preferably, the plurality of metal layer pattern below this inductance orthogonal with it (vertical) in fact that cover of this patterned ground protection.Wherein, this metal level for example can form with the first layer metal in semiconductor technology (metal1).
Please refer to Figure 10, the generalized section for a kind of integrated inductance structure 700 according to of the present invention 1 the 4th embodiment that Figure 10 illustrates.As shown in figure 10, integrated inductance structure 700 includes: semiconductor substrate 702, heavily distribute metal level (redistribution layer, RDL) 704 and an inductance 706.Inductance 706 is formed at semiconductor base 702 tops; And the metal level 704 that heavily distributes is formed at inductance 706 tops and has a specific pattern (for instance, as shown in figure 11, Figure 11 is a structure vertical view of integrated inductance structure 700, but the invention is not restricted to this), to form a patterned ground protection (Patterned Ground Shield, PGS) 708, the material of the metal level 704 that wherein heavily distributes can be aluminium.Note that in the present invention between inductance 706 and semiconductor base 702, not there is other any unnecessary patterned ground protections.In addition, integrated inductance structure 700 of the present invention can be applied to the integrated passive device (Integrated Passive Device, IPD) in a three-dimensional chip (3D IC).The integrated inductance structure 700 of the present embodiment can be applied to Flip Chip (Flip Chip), please refer to Figure 12, what Figure 12 illustrated is a rough schematic view that is applied to Flip Chip according to the integrated inductance structure 700 of the fourth embodiment of the present invention, as shown in figure 12, in the time including one first chip 720 of integrated inductance structure 700 and reverse down, the patterned ground protection 708 that the metal level 704 that heavily distributes above in integrated inductance structure 700 forms not only can reduce electromagnetic eddy current (eddy current) and improve quality factor (Q-factor), and can more effectively avoid inductance magnetic field flow in first chip 720 on upper strata to affect the signal of one second chip 730 of lower floor.Please note, the above embodiments only illustrate as of the present invention, are not restrictive condition of the present invention, for instance, also ground connection in addition of patterned ground protection 708, further to reduce electromagnetic eddy current (eddy current) and to improve quality factor (Q-factor).As shown in FIG. 10 and 11, preferably, the pattern of the metal level 704 that wherein heavily distributes is above this inductance 706 orthogonal with it (vertical) in fact.
Please refer to Figure 13, what Figure 13 illustrated is the flow chart of summarizing one the 4th embodiment of integrated inductance structure manufacture method of the present invention according to above-mentioned integrated inductance structure 700, if can obtain substantially identical result, the step in flow process not necessarily needs to carry out according to the order shown in Figure 13, also it is continuous not necessarily needing, that is to say, between these steps, can insert other step.The 4th embodiment of integrated inductance structure manufacture method of the present invention includes the following step:
Step 800: form semiconductor substrate.
Step 802: form an inductance in this semiconductor base top.
Step 804: form in this inductance top and there is one of the specific pattern metal level that heavily distributes, to form a patterned ground protection.
Note that the above embodiments only illustrate as of the present invention, is not restrictive condition of the present invention, and for instance, the step of integrated inductance structure manufacture method of the present invention can separately include: by this patterned ground protection ground connection.Preferably, the pattern of this heavy distribution metal level above this inductance orthogonal with it (vertical) in fact wherein.
Please refer to Figure 14, the generalized section for a kind of integrated inductance structure 900 according to of the present invention 1 the 5th embodiment that Figure 14 illustrates.As shown in figure 14, integrated inductance structure 900 includes: semiconductor substrate 902, multiple straight-through silicon wafer perforation (Through Silicon Via, TSV) 904 a, inductance 906 and the back side metal level (back side redistribution layer, back side RDL) 910 that heavily distributes.Inductance 906 is formed at semiconductor base 902 tops, and the plurality of straight-through silicon wafer perforation 904 is formed in semiconductor base 902.The back side metal level 910 that heavily distributes is formed at the bottom of semiconductor base 902 and is connected in the plurality of straight-through silicon wafer perforation 904, and the back side metal level 910 that heavily distributes has a specific pattern (for instance, as shown in figure 15, Figure 15 is a structural base vertical view of integrated inductance structure 900, but the invention is not restricted to this), to form a patterned ground protection (Patterned Ground Shield, PGS) 908, wherein the back side heavily distribute the material of metal level 904 can be for aluminium.Note that in the present invention between inductance 906 and semiconductor base 902, not there is other any unnecessary patterned ground protections.In addition, integrated inductance structure 900 of the present invention can be applied to the silicon plug-in unit (SiInterposer) in a three-dimensional chip (3D IC), please refer to Figure 16, what Figure 16 illustrated is a rough schematic view that is applied to a three-dimensional chip 920 according to the integrated inductance structure 900 of the fifth embodiment of the present invention, as shown in figure 16, three-dimensional chip 920 includes one first chip 930, one silicon plug-in unit 940 and one second chip 950, wherein silicon plug-in unit 940 has integrated inductance structure 900, and in integrated inductance structure 900, the back side of the below patterned ground protection 908 that metal level 910 forms that heavily distributes not only can reduce electromagnetic eddy current and improve quality factor (Q-factor), and can more effectively avoid inductance magnetic field flow in silicon plug-in unit 940 to affect the signal of one second chip 950 of lower floor.Please note, the above embodiments only illustrate as of the present invention, are not restrictive condition of the present invention, for instance, also ground connection in addition of patterned ground protection 908, further to reduce electromagnetic eddy current (eddy current) and to improve quality factor (Q-factor).
Please refer to Figure 17, what Figure 17 illustrated is the flow chart of summarizing one the 5th embodiment of integrated inductance structure manufacture method of the present invention according to above-mentioned integrated inductance structure 900, if can obtain substantially identical result, the step in flow process not necessarily needs to carry out according to the order shown in Figure 17, also it is continuous not necessarily needing, that is to say, between these steps, can insert other step.The 5th embodiment of integrated inductance structure manufacture method of the present invention includes the following step:
Step 1000: form semiconductor substrate.
Step 1002: form multiple straight-through silicon wafer perforation in this semiconductor base.
Step 1004: form an inductance in this semiconductor base top.
Step 1006: form the metal level that heavily distributes of a back side with a specific pattern in the bottom of this semiconductor base, and this back side metal level that heavily distributes is connected in to the plurality of straight-through silicon wafer perforation, to form a patterned ground protection.
Note that the above embodiments only illustrate as of the present invention, is not restrictive condition of the present invention, and for instance, the step of integrated inductance structure manufacture method of the present invention can separately include: by this patterned ground protection ground connection.
In addition, integrated inductance structure of the present invention can be applied to the silicon plug-in unit (Si Interposer) in a three-dimensional chip (3D IC), please refer to Figure 18, the integrated inductance structure for foundation previous embodiment of the present invention that Figure 18 illustrates is applied to a rough schematic view of a three-dimensional chip 1120, as shown in figure 18, three-dimensional chip 1120 includes one first chip 1130, one silicon plug-in unit 1140 and one second chip 1150, wherein silicon plug-in unit 1140 includes an integrated inductance structure of the present invention, it has the perforation of straight-through silicon wafer and the back side heavily distribute metal level or the metal level that heavily distributes.
In sum, compared to prior art, because disclosed integrated inductance structure and integrated inductance structure manufacture method have the patterned ground protection of innovation, can intercept the formation of the electromagnetic eddy of semiconductor base mid-deep strata, and can block the contingent path of electromagnetic eddy, block effect more thorough, and improve quality factor, and can be applicable to three-dimensional chip or Flip Chip.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application Patent right requirement scope change and modify, and all should belong to covering scope of the present invention.
Claims (13)
1. an integrated inductance structure, includes:
Semiconductor substrate;
Multiple straight-through silicon wafer perforation, are formed in this semiconductor base and are arranged in a specific pattern, and fill a metal material in this straight-through silicon wafer perforation, to form a patterned ground protection; And
One inductance, is formed at this semiconductor base top.
2. integrated inductance structure as claimed in claim 1, separately includes:
One covers metal layer pattern, is formed at the top of this semiconductor base, bores a hole jointly to form this patterned ground protection to connect the plurality of straight-through silicon wafer according to this specific pattern.
3. integrated inductance structure as claimed in claim 2, wherein this to cover metal layer pattern orthogonal with this inductance below this inductance in fact.
4. integrated inductance structure as claimed in claim 1, wherein this patterned ground protection ground connection.
5. integrated inductance structure as claimed in claim 1, wherein the width of this straight-through silicon wafer perforation is less than 20 microns.
6. integrated inductance structure as claimed in claim 1, it is applied to the silicon plug-in unit in a three-dimensional chip.
7. integrated inductance structure as claimed in claim 1, wherein this metal material is copper, aluminium or gold.
8. integrated inductance structure as claimed in claim 1, separately includes:
One back side metal layer pattern that heavily distributes, is formed at the below of this semiconductor base, to connect the plurality of straight-through silicon wafer perforation according to this specific pattern, jointly to form this patterned ground protection.
9. integrated inductance structure as claimed in claim 8, wherein this back side metal layer pattern that heavily distributes is orthogonal with this inductance below this inductance in fact.
10. an integrated inductance structure manufacture method, includes:
Form semiconductor substrate;
In this semiconductor base, form multiple straight-through silicon wafer perforation, and the plurality of straight-through silicon wafer perforation pattern is become to a specific pattern;
In this straight-through silicon wafer perforation, fill a metal material, to form a patterned ground protection; And
Form an inductance in this semiconductor base top.
11. integrated inductance structure manufacture methods as claimed in claim 10, separately include:
Cover metal layer pattern according to this specific pattern by one and connect the plurality of straight-through silicon wafer and bore a hole jointly to form this patterned ground protection, wherein this covers metal layer pattern and is formed at the top of this semiconductor base.
12. integrated inductance structure manufacture methods as claimed in claim 11, wherein this to cover metal layer pattern orthogonal with this inductance below this inductance in fact.
13. integrated inductance structure manufacture methods as claimed in claim 10, separately include:
According to this specific pattern, one back side metal layer pattern that heavily distributes is connected to the plurality of straight-through silicon wafer perforation, jointly to form this patterned ground protection, this back side metal layer pattern that heavily distributes is formed at the below of this semiconductor base.
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| CN201310105936.6A CN104078441A (en) | 2013-03-28 | 2013-03-28 | Integrated inductor structure and manufacturing method thereof |
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| CN201310105936.6A CN104078441A (en) | 2013-03-28 | 2013-03-28 | Integrated inductor structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017177387A1 (en) * | 2016-04-13 | 2017-10-19 | 深圳线易科技有限责任公司 | Reconfigurable magnetic-induction connection substrate and reconfigurable magnetic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2672876Y (en) * | 2003-07-28 | 2005-01-19 | 威盛电子股份有限公司 | Earth shield structure |
| US20090090995A1 (en) * | 2007-10-05 | 2009-04-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | On-chip inductors with through-silicon-via fence for Q improvement |
| US20100295151A1 (en) * | 2008-10-31 | 2010-11-25 | Panasonic Corporation | Semiconductor device |
-
2013
- 2013-03-28 CN CN201310105936.6A patent/CN104078441A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2672876Y (en) * | 2003-07-28 | 2005-01-19 | 威盛电子股份有限公司 | Earth shield structure |
| US20090090995A1 (en) * | 2007-10-05 | 2009-04-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | On-chip inductors with through-silicon-via fence for Q improvement |
| US20100295151A1 (en) * | 2008-10-31 | 2010-11-25 | Panasonic Corporation | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017177387A1 (en) * | 2016-04-13 | 2017-10-19 | 深圳线易科技有限责任公司 | Reconfigurable magnetic-induction connection substrate and reconfigurable magnetic device |
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Application publication date: 20141001 |