CN104064158B - There is the gate driver circuit of self-compensating function - Google Patents

There is the gate driver circuit of self-compensating function Download PDF

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Publication number
CN104064158B
CN104064158B CN201410342346.XA CN201410342346A CN104064158B CN 104064158 B CN104064158 B CN 104064158B CN 201410342346 A CN201410342346 A CN 201410342346A CN 104064158 B CN104064158 B CN 104064158B
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China
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electrically
tft
module
film transistor
thin film
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CN201410342346.XA
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Chinese (zh)
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CN104064158A (en
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戴超
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深圳市华星光电技术有限公司
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3696Generation of voltages supplied to electrode drivers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0404Matrix technologies
    • G09G2300/0408Integration of the drivers onto the display substrate
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0289Details of voltage level shifters arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery

Abstract

The invention provides a kind of gate driver circuit with self-compensating function, comprise: multiple GOA unit of cascade, this N level GOA unit comprises: above draw control module, upper drawing-die piece, lower transmission module, the first drop-down module, bootstrap capacitor module and the drop-down module that maintains; On this, drawing-die piece, the first drop-down module, bootstrap capacitor module, drop-down holding circuit are electrically connected with N level signal point Q (N) and this N level horizontal scanning line G (N) respectively, on this, draw control module and lower transmission module to be electrically connected with this N level signal point Q (N) respectively, this drop-down module input direct-current low-voltage VSS that maintains; This drop-down module that maintains adopts the first drop-down module and the second drop-down module alternation formation that maintains of maintaining. The drop-down reliability that maintains module and improve gate driver circuit long period of operation that the present invention has a self-compensating function by design, reduces the impact of threshold voltage shift on gate driver circuit running.

Description

There is the gate driver circuit of self-compensating function

Technical field

The present invention relates to liquid crystal technology field, relate in particular to a kind of grid with self-compensating function and drive electricityRoad.

Background technology

GOA (GateDriveronArray, the capable driving of array base palte) technology is using as gate switch electricityThe TFT (ThinFilmTransistor, TFT) on road is integrated on array base palte, fromAnd save the grid-driving integrated circuit part being originally arranged on outside array base palte, from material cost and techniqueStep two aspect reduces the cost of product. GOA technology is current TFT-LCD (ThinFilmTransistor-LiquidCrystalDisplay, TFT liquid crystal display) technical field is normalWith a kind of gate driver circuit technology, its manufacture craft is simple, has a good application prospect. GOAThe function of circuit mainly comprises: utilize the high level signal of lastrow grid line output to shift register cellIn capacitor charging so that one's own profession grid line output high level signal, the height of recycling next line grid line outputLevel signal realizes and resetting.

Refer to Fig. 1, Fig. 1 is the gate driver circuit configuration diagram often adopting at present. Comprise: cascadeMultiple GOA unit, according to N level GOA unit controls to viewing area N level horizontal scanning lineG (N) charging, this N level GOA unit comprises and draws control module 1 ', upper drawing-die piece 2 ', passes mould downPiece 3 ', the first drop-down module 4 ' (Keypull-downpart), bootstrap capacitor module 5 ' and drop-down maintainingModule 6 ' (Pull-downholdingpart). Described upper drawing-die piece 2 ', the first drop-down module 4 ', bootstrapping electricityMolar piece 5 ', drop-down holding circuit 6 ' are swept with N level signal point Q (N) and this N level level respectivelyRetouch line G (N) and be electrically connected, draw on described control module 1 ' and lower transmission module 3 ' respectively with this N level gridSignaling point Q (N) is electrically connected, described drop-down module 6 ' the input direct-current low-voltage VSS that maintains.

On described, draw control module 1 ' to comprise the first film transistor T 1 ', its grid is inputted from N-1 levelThe number of delivering a letter ST (N-1) under GOA unit, drain electrode is electrically connected at N-1 level horizontal scanning line G (N-1),Source electrode is electrically connected at this N level signal point Q (N); Described upper drawing-die piece 2 ' comprises the second film crystalline substanceBody pipe T2 ', its grid is electrically connected this N level signal point Q (N), when drain electrode input the first high frequencyClock signal CK or the second high frequency clock signal XCK, source electrode is electrically connected at N level horizontal scanning lineG (N); Described lower transmission module 3 ' comprises the 3rd thin film transistor (TFT) T3 ', and its grid is electrically connected this N level gridUtmost point signaling point Q (N), drain electrode input the first high frequency clock signal CK or the second high frequency clock signal XCK,Source electrode is exported the number of delivering a letter ST (N) under N level; Described the first drop-down module 4 ' comprises the 4th thin film transistor (TFT)T4 ', its grid is electrically connected N+1 level horizontal scanning line G (N+1), and drain electrode is electrically connected at N levelHorizontal scanning line G (N), source electrode input direct-current low-voltage VSS; The 5th thin film transistor (TFT) T5 ', its gridBe electrically connected N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected at this N level signal pointQ (N), source electrode input direct-current low-voltage VSS; Described bootstrap capacitor module 5 ' comprises bootstrap capacitor Cb '; InstituteStating the drop-down module 6 ' that maintains comprising: the 6th thin film transistor (TFT) T6 ', its grid is electrically connected the first circuit pointP (N) ', drain electrode is electrically connected N level horizontal scanning line G (N), source electrode input direct-current low-voltage VSS; TheSeven thin film transistor (TFT) T7 ', its grid is electrically connected the first circuit point P (N) ', and drain electrode is electrically connected this NLevel signal point Q (N), source electrode input direct-current low-voltage VSS; The 8th thin film transistor (TFT) T8 ', its gridThe utmost point is electrically connected second circuit point K (N) ', and drain electrode is electrically connected N level horizontal scanning line G (N), source electrodeInput direct-current low-voltage VSS; The 9th thin film transistor (TFT) T9 ', its grid is electrically connected second circuit point K (N) ',Drain electrode is electrically connected this N level signal point Q (N), source electrode input direct-current low-voltage VSS; The tenth is thinFilm transistor T10 ', its grid is inputted the first low-frequency clock signal LC1, drain electrode input the first low-frequency clockSignal LC1, source electrode is electrically connected the first circuit point P (N) '; The 11 thin film transistor (TFT) T11 ', its gridInput the second low-frequency clock signal LC2, drain electrode input the first low-frequency clock signal LC1, source electrode is electrically connectedThe first circuit point P (N) '; The 12 thin film transistor (TFT) T12 ', its grid is inputted the second low-frequency clock signalLC2, drain electrode input the second low-frequency clock signal LC2, source electrode is electrically connected second circuit point K (N) '; The13 thin film transistor (TFT) T13 ', its grid is inputted the first low-frequency clock signal LC1, and drain electrode input second is lowFrequently clock signal LC2, source electrode is electrically connected second circuit point K (N) '; The 14 thin film transistor (TFT) T14 ',Its grid is electrically connected this N level signal point Q (N), and drain electrode is electrically connected the first circuit point P (N) ',Source electrode input direct-current low-voltage VSS; The 15 thin film transistor (TFT) T15 ', its grid is electrically connected this NLevel signal point Q (N), drain electrode is electrically connected second circuit point K (N) ', source electrode input direct-current low-voltageVSS; Wherein, the 6th thin film transistor (TFT) T6 ' and the 8th thin film transistor (TFT) T8 ' are responsible for maintaining between inaction periodThe electronegative potential of N level horizontal scanning line G (N), the 7th thin film transistor (TFT) T7 ' and the 9th thin film transistor (TFT) T9 'Be responsible for maintaining between inaction period the electronegative potential of N level signal point Q (N).

From whole circuit framework, the drop-down module 6 ' that maintains is in longer duty, and namelyOne circuit point P (N) ' and second circuit point K (the N) ' high potential state in a forward for a long time, thisIn sample circuit, be subject to the most serious several elements of voltage stress effect (Stress) and be exactly thin film transistor (TFT) T6 ',T7 ', T8 ', T9 '. Along with the increase of gate driver circuit working time, thin film transistor (TFT) T6 ', T7 ',The threshold voltage vt h of T8 ', T9 ' can increase gradually, and ON state current can reduce gradually, and this will cause NLevel horizontal scanning line G (N) and N level signal point Q (N) cannot maintain well one stable lowPotential state, this is also to affect the most important factor of gate driver circuit reliability.

For amorphous silicon film transistor gate driver circuit, the drop-down module that maintains is absolutely necessary,Conventionally can be designed as one group of drop-down module that maintains, or the drop-down module that maintains of two groups of alternating actions. DesignBecoming two groups of drop-down module main purposes that maintain is exactly in order to alleviate drop-down the first circuit point P (N) ' in module that maintainsWith second circuit point K (N) ' voltage stress that is subject to of thin film transistor (TFT) T6 ', T7 ', T8 ', T9 ' controlled doesWith. But actual measurement discovery, even if be designed to two groups of drop-down modules that maintain, thin film transistor (TFT) T6 ', T7 ',These four thin film transistor (TFT)s of T8 ', T9 ' are still that in whole gate driver circuit circuit, to be subject to voltage stress the tightestHeavy part, that is to say that threshold voltage (Vth) drift of thin film transistor (TFT) is maximum.

Referring to Fig. 2 a, is thin film transistor (TFT) overall current logarithm before and after threshold voltage shift and voltage curveRelationship change schematic diagram, wherein, solid line is electric current logarithm and the voltage relationship song that threshold voltage shift does not occurLine, dotted line is electric current logarithm and the voltage curve after threshold voltage shift. From Fig. 2 a, sameUnder one gate-source voltage Vgs, the electric current logarithm Log (Ids) that threshold voltage shift does not occur is greater than threshold voltageElectric current logarithm after drift. Referring to Fig. 2 b, is thin film transistor (TFT) overall current before and after threshold voltage shiftWith voltage curve relationship change schematic diagram. From Fig. 2 b, under same drain-source electrode current Ids, do not send outThe grid voltage Vg1 of raw threshold voltage shift is less than the grid voltage Vg2 after threshold voltage shift, i.e. thresholdAfter threshold voltage drift, want the drain-source electrode current Ids that reaches equal, need larger grid voltage.

Can be found out by Fig. 2 a and Fig. 2 b, to the forward drift of threshold voltage vt h can cause thin film transistor (TFT)ON state current Ion reduces gradually, along with the increase of threshold voltage vt h, and the ON state current Ion of thin film transistor (TFT)Can continue to reduce, so, for circuit, just cannot maintain well N level signal point Q (N)With stablizing of N level horizontal scanning line G (N) current potential, will cause like this LCD picture to showExtremely.

As mentioned above, the element the most easily losing efficacy in gate driver circuit is exactly the drop-down film crystalline substance that maintains moduleBody pipe T6 ', T7 ', T8 ', T9 ', therefore, can for what improve gate driver circuit and display panelsLean on property to address this problem. Conventionally the way in design is the chi that increases these four thin film transistor (TFT)sVery little, still, when increasing thin film transistor (TFT) size, also can increase the OFF leakage current of thin film transistor (TFT) work,Cannot be from dealing with problems in essence.

Summary of the invention

The object of the present invention is to provide a kind of gate driver circuit with self-compensating function, pass through toolThe drop-down reliability that maintains module and improve gate driver circuit long period of operation that has a self-compensating function, fallsThe impact of low threshold voltage drift on gate driver circuit running.

For achieving the above object, the invention provides a kind of gate driver circuit with self-compensating function, bagDraw together: multiple GOA unit of cascade, according to N level GOA unit controls to viewing area N level waterScan lines G (N) charging, this N level GOA unit comprises: above draw control module, upper drawing-die piece,Lower transmission module, the first drop-down module, bootstrap capacitor module and the drop-down module that maintains; Described upper drawing-die piece,The first drop-down module, bootstrap capacitor module, drop-down holding circuit respectively with N level signal point Q (N)Be electrically connected with this N level horizontal scanning line G (N), draw on described control module and lower transmission module respectively withThis N level signal point Q (N) is electrically connected, the described drop-down module input direct-current low-voltage VSS that maintains;

The described drop-down module that maintains adopts the first drop-down module and second that maintains drop-downly to maintain module alternationForm;

Described the first drop-down module that maintains comprises: the first film transistor T 1, its grid is electrically connected firstCircuit point P (N), drain electrode is electrically connected N level horizontal scanning line G (N), source electrode input direct-current low-voltageVSS; The second thin film transistor (TFT) T2, its grid is electrically connected the first circuit point P (N), and drain electrode is electrically connectedN level signal point Q (N), source electrode input direct-current low-voltage VSS; The 3rd thin film transistor (TFT) T3, itsGrid is electrically connected the first low-frequency clock signal LC1 or the first high frequency clock signal CK, and drain electrode is electrically connectedThe first low-frequency clock signal LC1 or the first high frequency clock signal CK, source electrode is electrically connected second circuit pointS (N); The 4th thin film transistor (TFT) T4, its grid is electrically connected N level signal point Q (N), drain electrode electricityProperty connect second circuit point S (N), source electrode input direct-current low-voltage VSS; The 5th thin film transistor (TFT) T5, itsGrid is electrically connected N-1 level signal point Q (N-1), and drain electrode is electrically connected the first circuit point P (N),Source electrode input direct-current low-voltage VSS; The 6th thin film transistor (TFT) T6, its grid is electrically connected N+1 level waterScan lines G (N+1), drain electrode is electrically connected the first circuit point P (N), and source electrode is electrically connected N level gridSignaling point Q (N); The 7th thin film transistor (TFT) T7, its grid is electrically connected the second low-frequency clock signal LC2Or the second high frequency clock signal XCK, drain electrode is electrically connected the first low-frequency clock signal LC1 or the first high frequencyClock signal C K, source electrode is electrically connected second circuit point S (N); The first capacitor C st1, its top crown is electricalConnect second circuit point S (N), bottom crown is electrically connected the first circuit point P (N);

Described the second drop-down module that maintains comprises: the 8th thin film transistor (TFT) T8, its grid is electrically connected the 3rdCircuit point K (N), drain electrode is electrically connected N level horizontal scanning line G (N), source electrode input direct-current low-voltageVSS; The 9th thin film transistor (TFT) T9, its grid is electrically connected tertiary circuit point K (N), and drain electrode is electrically connectedN level signal point Q (N), source electrode input direct-current low-voltage VSS; The tenth thin film transistor (TFT) T10,Its grid is electrically connected the second low-frequency clock signal LC2 or the second high frequency clock signal XCK, and drain electrode electricallyConnect the second low-frequency clock signal LC2 or the second high frequency clock signal XCK, source electrode is electrically connected the 4th electricityWaypoint T (N); The 11 thin film transistor (TFT) T11, its grid is electrically connected N level signal point Q (N),Drain electrode is electrically connected the 4th circuit point T (N), source electrode input direct-current low-voltage VSS; The 12 film crystalPipe T12, its grid is electrically connected N-1 level signal point Q (N-1), and drain electrode is electrically connected tertiary circuitPoint K (N), source electrode input direct-current low-voltage VSS; The 13 thin film transistor (TFT) T13, its grid electrically connectsMeet N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected tertiary circuit point K (N), and source electrode electrically connectsMeet N level signal point Q (N); The 14 thin film transistor (TFT) T14, it is first low that its grid is electrically connectedFrequently clock signal LC1 or the first high frequency clock signal CK, drain electrode is electrically connected the second low-frequency clock signalLC2 or the second high frequency clock signal XCK, source electrode is electrically connected the 4th circuit point T (N); The second electric capacityCst2, its top crown is electrically connected the 4th circuit point T (N), and bottom crown is electrically connected tertiary circuit point K (N).

On described, draw control module to comprise the 15 thin film transistor (TFT) T15, its grid is inputted from N-1 levelThe number of delivering a letter ST (N-1) under GOA unit, drain electrode is electrically connected at N-1 level horizontal scanning line G (N-1),Source electrode is electrically connected at this N level signal point Q (N); Described upper drawing-die piece comprises the 16 film crystalline substanceBody pipe T16, its grid is electrically connected this N level signal point Q (N), when drain electrode input the first high frequencyClock signal CK or the second high frequency clock signal XCK, source electrode is electrically connected at N level horizontal scanning lineG (N); Described lower transmission module comprises the 17 thin film transistor (TFT) T17, and its grid is electrically connected this N levelSignal point Q (N), drain electrode input the first high frequency clock signal CK or the second high frequency clock signal XCK,Source electrode is exported the number of delivering a letter ST (N) under N level; Described the first drop-down module comprises the 18 thin film transistor (TFT)T18, its grid is electrically connected N+2 level horizontal scanning line G (N+2), and drain electrode is electrically connected at N levelHorizontal scanning line G (N), source electrode input direct-current low-voltage VSS; The 19 thin film transistor (TFT) T19, its gridThe utmost point is electrically connected N+2 level horizontal scanning line G (N+2), and drain electrode is electrically connected at this N level signalPoint Q (N), source electrode input direct-current low-voltage VSS; Described bootstrap capacitor module comprises bootstrap capacitor Cb.

In the first order annexation of described gate driver circuit, the grid of the 5th thin film transistor (TFT) T5 is electricalBe connected in circuit start signal STV; The grid of the 12 thin film transistor (TFT) T12 is electrically connected at circuit and opensMoving signal STV; The grid of the 15 thin film transistor (TFT) T15 and drain electrode are all electrically connected at circuit start letterNumber STV.

In the afterbody annexation of described gate driver circuit, the grid electricity of the 6th thin film transistor (TFT) T6Property is connected in circuit start signal STV; The grid of the 13 thin film transistor (TFT) T13 is electrically connected at circuitEnabling signal STV; The grid of the 18 thin film transistor (TFT) T18 is electrically connected at second level horizontal scanning lineG (2); The grid of the 19 thin film transistor (TFT) T19 is electrically connected at second level horizontal scanning line G (2).

Described the first drop-down module that maintains also comprises: the 3rd capacitor C st3, its top crown is electrically connected the first electricityWaypoint P (N), bottom crown input direct-current low-voltage VSS; Described the first drop-down module and second drop-down that maintainsThe circuit framework that maintains module is identical.

Described the first drop-down module that maintains also comprises: the 20 thin film transistor (TFT) T20, its grid is electrically connectedN+1 level horizontal scanning line G (N+1), drain electrode is electrically connected second circuit point S (N), source electrode input direct-currentLow-voltage VSS; Described first drop-down to maintain module identical with the second drop-down circuit framework that maintains module.

Described the first drop-down module that maintains also comprises: the 3rd capacitor C st3, its top crown is electrically connected the first electricityWaypoint P (N), bottom crown input direct-current low-voltage VSS; The 20 thin film transistor (TFT) T20, its grid electricityProperty connect N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected second circuit point S (N), source electrode is defeatedEnter DC low-voltage VSS; Described the first drop-down module and the second drop-down circuit framework phase that maintains module of maintainingWith.

Described the first high frequency clock signal CK and the second high frequency clock signal XCK are two complete phases of phase placeAnti-high frequency clock signal source; Described the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2Two antipodal low frequency signal sources of phase place.

Grid and the 19 thin film transistor (TFT) of the 18 thin film transistor (TFT) T18 in described the first drop-down moduleThe grid of T19 is all electrically connected N+2 level horizontal scanning line G (N+2), mainly for realizing N level gridUtmost point signaling point Q (N) current potential is three phases, and the first stage is when rising to a high potential and maintaining one sectionBetween, rise again on the basis of a first stage high potential maintain a period of time, the 3rd rank of second stageSection drops to the high potential remaining basically stable with the first stage on the basis of second stage, then utilizes three rankPhase III in section is carried out the self-compensating of threshold voltage.

Described N level signal point Q (N) current potential is three phases, and wherein the variation of phase III is mainBe subject to the impact of the 6th thin film transistor (TFT) T6 or the 13 transistor (T13).

Beneficial effect of the present invention: the invention provides a kind of gate driver circuit with self-compensating function,Utilize the boot strap of electric capacity to control drop-down the first circuit point P (N) or the tertiary circuit point that maintains moduleK (N), design can detect the function of thin film transistor (TFT) threshold voltage, and threshold voltage is stored in to the first electricityWaypoint P (N) or tertiary circuit point K (N), and then realize the first circuit point P (N) or tertiary circuit point K (N)Control voltage change along with the threshold voltage shift of thin film transistor (TFT). The present invention has oneself by designCompensate function drop-down maintains module improves the reliability of gate driver circuit long period of operation, falls low-threshold powerPress the impact of drift on gate driver circuit running.

In order further to understand feature of the present invention and technology contents, refer to following relevant the present inventionDetailed description and accompanying drawing, but accompanying drawing only provide with reference to and explanation use, be not used for the present invention to be limitSystem.

Brief description of the drawings

Below in conjunction with accompanying drawing, by the specific embodiment of the present invention is described in detail, will make skill of the present inventionArt scheme and other beneficial effect are apparent.

In accompanying drawing,

Fig. 1 is the gate driver circuit configuration diagram often adopting at present;

Fig. 2 a is thin film transistor (TFT) overall current logarithm and voltage curve relationship change before and after threshold voltage shiftSchematic diagram;

Fig. 2 b is thin film transistor (TFT) overall current and the signal of voltage curve relationship change before and after threshold voltage shiftFigure;

Fig. 3 is the gate driver circuit single-stage configuration diagram that the present invention has self-compensating function;

Fig. 4 is the gate driver circuit single-stage framework first order connection pass that the present invention has self-compensating functionIt is schematic diagram;

Fig. 5 is the gate driver circuit single-stage framework afterbody connection that the present invention has self-compensating functionBe related to schematic diagram;

Fig. 6 is the first drop-down circuit diagram that maintains module the first embodiment adopting in Fig. 3;

Fig. 7 a is the gate driver circuit sequential chart shown in Fig. 3 before threshold voltage shift;

Fig. 7 b is the gate driver circuit sequential chart shown in Fig. 3 after threshold voltage shift;

Fig. 8 is the first drop-down circuit diagram that maintains module the second embodiment adopting in Fig. 3;

Fig. 9 is the first drop-down circuit diagram that maintains module the 3rd embodiment adopting in Fig. 3;

Figure 10 is the first drop-down circuit diagram that maintains module the 4th embodiment adopting in Fig. 3.

Detailed description of the invention

Technological means and the effect thereof taked for further setting forth the present invention, below in conjunction with of the present inventionPreferred embodiment and accompanying drawing thereof are described in detail.

Refer to Fig. 3, the gate driver circuit single-stage framework for the present invention with self-compensating function is illustratedFigure. Comprise: multiple GOA unit of cascade, according to N level GOA unit controls to viewing areaN level horizontal scanning line G (N) charging, this N level GOA unit comprises: above draw control module 1, on drawModule 2, lower transmission module 3, the first drop-down module 4, bootstrap capacitor module 5 and the drop-down module 6 that maintains;Described upper drawing-die piece 2, the first drop-down module 4, bootstrap capacitor module 5, drop-down holding circuit 6 respectively withN level signal point Q (N) and this N level horizontal scanning line G (N) are electrically connected, and draw control on describedMolding piece 1 is electrically connected with this N level signal point Q (N) respectively with lower transmission module 3, described drop-downMaintain module 6 input direct-current low-voltage VSS.

The described drop-down module 6 that maintains adopts the first drop-down module 61 and the second drop-down module 62 that maintains of maintainingAlternation forms;

Described the first drop-down module 61 that maintains comprises: the first film transistor T 1, its grid is electrically connected theOne circuit point P (N), drain electrode is electrically connected N level horizontal scanning line G (N), source electrode input direct-current low-voltageVSS; The second thin film transistor (TFT) T2, its grid is electrically connected the first circuit point P (N), and drain electrode is electrically connectedN level signal point Q (N), source electrode input direct-current low-voltage VSS; The 3rd thin film transistor (TFT) T3, itsGrid is electrically connected the first low-frequency clock signal LC1 or the first high frequency clock signal CK, and drain electrode is electrically connectedThe first low-frequency clock signal LC1 or the first high frequency clock signal CK, source electrode is electrically connected second circuit pointS (N); The 4th thin film transistor (TFT) T4, its grid is electrically connected N level signal point Q (N), drain electrode electricityProperty connect second circuit point S (N), source electrode input direct-current low-voltage VSS; The 5th thin film transistor (TFT) T5, itsGrid is electrically connected N-1 level signal point Q (N-1), and drain electrode is electrically connected the first circuit point P (N),Source electrode input direct-current low-voltage VSS; The 6th thin film transistor (TFT) T6, its grid is electrically connected N+1 level waterScan lines G (N+1), drain electrode is electrically connected the first circuit point P (N), and source electrode is electrically connected N level gridSignaling point Q (N); The 7th thin film transistor (TFT) T7, its grid is electrically connected the second low-frequency clock signal LC2Or the second high frequency clock signal XCK, drain electrode is electrically connected the first low-frequency clock signal LC1 or the first high frequencyClock signal C K, source electrode is electrically connected second circuit point S (N); The first capacitor C st1, its top crown is electricalConnect second circuit point S (N), bottom crown is electrically connected the first circuit point P (N);

Described the second drop-down module 62 that maintains comprises: the 8th thin film transistor (TFT) T8, its grid is electrically connected theThree-circuit point K (N), drain electrode is electrically connected N level horizontal scanning line G (N), source electrode input direct-current low-voltageVSS; The 9th thin film transistor (TFT) T9, its grid is electrically connected tertiary circuit point K (N), and drain electrode is electrically connectedN level signal point Q (N), source electrode input direct-current low-voltage VSS; The tenth thin film transistor (TFT) T10,Its grid is electrically connected the second low-frequency clock signal LC2 or the second high frequency clock signal XCK, and drain electrode electricallyConnect the second low-frequency clock signal LC2 or the second high frequency clock signal XCK, source electrode is electrically connected the 4th electricityWaypoint T (N); The 11 thin film transistor (TFT) T11, its grid is electrically connected N level signal point Q (N),Drain electrode is electrically connected the 4th circuit point T (N), source electrode input direct-current low-voltage VSS; The 12 film crystalPipe T12, its grid is electrically connected N-1 level signal point Q (N-1), and drain electrode is electrically connected tertiary circuitPoint K (N), source electrode input direct-current low-voltage VSS; The 13 thin film transistor (TFT) T13, its grid electrically connectsMeet N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected tertiary circuit point K (N), and source electrode electrically connectsMeet N level signal point Q (N); The 14 thin film transistor (TFT) T14, it is first low that its grid is electrically connectedFrequently clock signal LC1 or the first high frequency clock signal CK, drain electrode is electrically connected the second low-frequency clock signalLC2 or the second high frequency clock signal XCK, source electrode is electrically connected the 4th circuit point T (N); The second electric capacityCst2, its top crown is electrically connected the 4th circuit point T (N), and bottom crown is electrically connected tertiary circuit point K (N).

On described, draw control module 1 to comprise the 15 thin film transistor (TFT) T15, its grid is inputted from N-1The number of delivering a letter ST (N-1) under level GOA unit, drain electrode is electrically connected at N-1 level horizontal scanning lineG (N-1), source electrode is electrically connected at this N level signal point Q (N); Described upper drawing-die piece 2 comprises16 thin film transistor (TFT) T16, its grid is electrically connected this N level signal point Q (N), drain electrode inputThe first high frequency clock signal CK or the second high frequency clock signal XCK, source electrode is electrically connected at N level waterScan lines G (N); Described lower transmission module 3 comprises the 17 thin film transistor (TFT) T17, and its grid electrically connectsMeet this N level signal point Q (N), when drain electrode input the first high frequency clock signal CK or the second high frequencyClock signal XCK, source electrode is exported the number of delivering a letter ST (N) under N level; Described the first drop-down module 4 comprises18 thin film transistor (TFT) T18, its grid is electrically connected N+2 level horizontal scanning line G (N+2), drain electrode electricityProperty is connected in N level horizontal scanning line G (N), source electrode input direct-current low-voltage VSS; The 19 film crystalline substanceBody pipe T19, its grid is electrically connected N+2 level horizontal scanning line G (N+2), and drain electrode is electrically connected at thisN level signal point Q (N), source electrode input direct-current low-voltage VSS; In described the first drop-down module 4The grid of the grid of the 18 thin film transistor (TFT) T18 and the 19 thin film transistor (TFT) T19 is all electrically connectedN+2 level horizontal scanning line G (N+2), the object of doing is like this in order to make N level signal point Q (N)Current potential is three phases, and the first stage is rise to a high potential and maintain a period of time, and second stage existsRise again on the basis of a first stage high potential maintain a period of time, the phase III is in second stageOn basis, drop to the high potential remaining basically stable with the first stage, then utilize the phase III in three phasesCarry out the self-compensating of threshold voltage; Described bootstrap capacitor module 5 comprises bootstrap capacitor Cb.

Progression between described multistage horizontal scanning line circulates, as N level horizontal scanning line G (N)In N while being afterbody Last, N+2 level horizontal scanning line G (N+2) represents that second level level sweepsRetouch line G (2); In the time that the N in N level horizontal scanning line G (N) is penultimate stage Last-1, N+2Level horizontal scanning line G (N+2) represents first order horizontal scanning line G (1), by that analogy.

Refer to Fig. 4 and in conjunction with Fig. 3, Fig. 4 is the gate driver circuit that the present invention has self-compensating functionSingle-stage framework first order annexation schematic diagram, N is the gate driver circuit annexation signal of 1 o'clockFigure. Wherein, the grid of the 5th thin film transistor (TFT) T5 is electrically connected at circuit start signal STV; The 12The grid of thin film transistor (TFT) T12 is electrically connected at circuit start signal STV; The 15 thin film transistor (TFT) T15Grid and drain electrode be all electrically connected at circuit start signal STV.

Refer to Fig. 5 and in conjunction with Fig. 3, Fig. 5 is the gate driver circuit that the present invention has self-compensating functionSingle-stage framework afterbody annexation schematic diagram, gate driver circuit when N is afterbody LastAnnexation schematic diagram. Wherein, the grid of the 6th thin film transistor (TFT) T6 is electrically connected at circuit start signalSTV; The grid of the 13 thin film transistor (TFT) T13 is electrically connected at circuit start signal STV; The 18The grid of thin film transistor (TFT) T18 is electrically connected at second level horizontal scanning line G (2); The 19 film crystalThe grid of pipe T19 is electrically connected at second level horizontal scanning line G (2).

Referring to Fig. 6, is the first drop-down circuit diagram that maintains module the first embodiment adopting in Fig. 3. BagDraw together: the first film transistor T 1, its grid is electrically connected the first circuit point P (N), and drain electrode is electrically connected theN level horizontal scanning line G (N), source electrode input direct-current low-voltage VSS; The second thin film transistor (TFT) T2, its gridThe utmost point is electrically connected the first circuit point P (N), and drain electrode is electrically connected N level signal point Q (N), and source electrode is defeatedEnter DC low-voltage VSS; The 3rd thin film transistor (TFT) T3, its grid is electrically connected the first low-frequency clock signalLC1 or the first high frequency clock signal CK, drain electrode is electrically connected the first low-frequency clock signal LC1 or the first heightFrequently clock signal C K, source electrode is electrically connected second circuit point S (N); The 4th thin film transistor (TFT) T4, its gridThe utmost point is electrically connected N level signal point Q (N), and drain electrode is electrically connected second circuit point S (N), and source electrode is defeatedEnter DC low-voltage VSS, the 4th thin film transistor (TFT) T4 mainly drags down second circuit point S (N) between action period,So just can realize the object of putting S (N) and control the first circuit point P (N) current potential by second circuit; TheFive thin film transistor (TFT) T5, its grid is electrically connected N-1 level signal point Q (N-1), and drain electrode electrically connectsMeet the first circuit point P (N), source electrode input direct-current low-voltage VSS, the work of described the 5th thin film transistor (TFT) T5With being the action period of guaranteeing in N level horizontal scanning line G (N) and N level signal point Q (N) outputBetween, the closed condition of the first circuit point P (N) in electronegative potential, thus guarantee N level horizontal scanning line G (N)Can normally export with N level signal point Q (N); The 6th thin film transistor (TFT) T6, its grid electrically connectsMeet N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected the first circuit point P (N), and source electrode electrically connectsMeet N level signal point Q (N), the object of design is utilized N level signal point Q (N) exactly like thisThree phases in the current potential of phase III carry out the detecting of threshold voltage, and its current potential is stored in to firstCircuit point P (N); The 7th thin film transistor (TFT) T7, its grid be electrically connected the second low-frequency clock signal LC2 orThe second high frequency clock signal XCK, when drain electrode is electrically connected the first low-frequency clock signal LC1 or the first high frequencyClock signal CK, source electrode is electrically connected second circuit point S (N); The first capacitor C st1, its top crown electrically connectsMeet second circuit point S (N), bottom crown is electrically connected the first circuit point P (N). Described the first drop-down mould that maintainsPiece is identical with the second drop-down circuit framework that maintains module.

Refer to Fig. 7 a, 7b and in conjunction with Fig. 3, Fig. 7 a is that before threshold voltage shift, the grid shown in Fig. 3 drivesMoving circuit timing diagram, Fig. 7 b is the gate driver circuit sequential chart shown in Fig. 3 after threshold voltage shift. ?In Fig. 7 a, 7b, STV signal is circuit start signal, the first high frequency clock signal CK and the second high frequencyClock signal XCK is one group of antipodal high frequency clock control signal of phase place, the first low-frequency clock signalLC1 and the second low-frequency clock signal LC2 are two antipodal low frequency signal sources of phase place, and G (N-1) isN-1 level horizontal scanning line, i.e. the Scan out of previous stage, ST (N-1) delivers a letter under N-1 levelNumber, previous stage under the number of delivering a letter, Q (N-1) is N-1 level signal point, i.e. the grid of previous stage letterNumber point, Q (N) is N level signal point, i.e. signal point at the corresponding levels.

Fig. 7 a, 7b are the sequential chart of the first low-frequency clock signal LC1 under in running order, first timeDraw and maintain the sequential chart of module 61 under in running order. Can find out N level signal point Q (N)Current potential is three phases, and the first stage is rise to a high potential and maintain a period of time, and second stage existsRise again on the basis of a first stage high potential maintain a period of time, the phase III is in second stageOn basis, drop to the high potential remaining basically stable with the first stage, wherein the variation of phase III is mainly subject to the 6thThe impact of thin film transistor (TFT) T6. From Fig. 7 a, when the initial time T0 that just lighted at liquid crystal panel,Threshold voltage vt h is less, and when gate driver circuit is not through long period of operation, threshold voltage vt h does not occurDrift, the phase III current potential of N level signal point Q (N) is lower, with it the first corresponding circuit pointThe current potential of P (N) is also lower. From Fig. 7 b, the phase III current potential of N level signal point Q (N) existsLifting thereupon after voltage stress effect lower threshold voltages Vth drift, so just can realize and utilize this partThe object of the threshold voltage of detecting the first film transistor T 1 and the second thin film transistor (TFT) T2.

The course of work by gate driver circuit shown in Fig. 7 a and the known Fig. 3 of 7b is: N+1 level levelWhen scan line G (N+1) conducting, the 6th thin film transistor (TFT) T6 opens, now N level signal point Q (N)Identical with the current potential of the first circuit point P (N), the second thin film transistor (TFT) T2 equivalence becomes diode connection, firstCircuit point P (N), in the phase III of N level signal point Q (N), can pass through the 6th thin film transistor (TFT)The value of the threshold voltage of T6 storage the first film transistor T 1 and the second thin film transistor (TFT) T2, so, withThe drift of threshold voltage vt h, the current potential lifting of the phase III of N level signal point Q (N), theThe also lifting of potential value of the threshold voltage of one circuit point P (N) storage, then, second circuit point S (N) is logical againCross the first capacitor C st1 and carry out lifting the first circuit point P (N), variation that so just can compensating threshold voltage.

In Fig. 7 a, 7b, before and after threshold voltage vt h drifts about, N level signal point Q (N) and the first electricityAlso there is obvious variation in the current potential of waypoint P (N), especially the increase of the current potential of the first circuit point P (N)Can effectively reduce threshold voltage shift opens the first film transistor T 1 and the second thin film transistor (TFT) T2The impact of state electric current, thus guarantee N level horizontal scanning line G (N) and N level signal point Q (N)Can, after long period of operation, still maintain well low-potential state.

In like manner, when the second low-frequency clock signal LC2 is when in running order (not shown), the second drop-down dimensionHold module 62 and work, N level signal point Q (N) is three phases, and the first stage is to rise to oneIndividual high potential also maintains a period of time, and second stage rises again a high potential also on the basis of first stageMaintain a period of time, the phase III drops to the height remaining basically stable with the first stage on the basis of second stageCurrent potential, wherein the variation of phase III is mainly subject to the impact of the 13 thin film transistor (TFT) T13, and the phase III existsLower before threshold voltage shift, lifting thereupon after threshold voltage shift, so just can realize and utilize this partDetect the object of the threshold voltage of the 8th thin film transistor (TFT) T8 and the 9th transistor T 9. Now Fig. 3 instituteThe course of work of showing gate driver circuit is: when N+1 level horizontal scanning line G (N+1) conducting, and the 13Thin film transistor (TFT) T13 opens, now the current potential of N level signal point Q (N) and tertiary circuit point K (N)Identical, the 9th thin film transistor (TFT) T9 equivalence becomes diode connection, and tertiary circuit point K (N) is at N level gridThe phase III of utmost point signaling point Q (N), can pass through the 13 thin film transistor (TFT) T13 storage the 8th film crystalline substanceThe value of the threshold voltage of body pipe T8 and the 9th transistor T 9, so, along with the drift of threshold voltage vt h,The current potential lifting of the phase III of N level signal point Q (N), the threshold value of tertiary circuit point K (N) storageThe also lifting of the potential value of voltage, then, the 4th circuit point T (N) carrys out lifting by the second capacitor C st2 againThree-circuit point K (N), variation that so just can compensating threshold voltage, thus guarantee the horizontal sweep of N levelLine G (N) and N level signal point Q (N) can, after long period of operation, still maintain low electricity wellPosition state.

As shown in Fig. 7 a, 7b, the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 hand overTemporary substitute is done, namely the first drop-down module 61 and the second drop-down module 62 that maintains of maintaining shown in Fig. 3Alternation, can reduce working time of each module like this, and the voltage stress effect being subject to is reduced,And then the reliability of raising circuit entirety.

Refer to Fig. 8 and in conjunction with Fig. 6, Fig. 8 is the first drop-down module the second embodiment that maintains that Fig. 3 adoptsCircuit diagram. Fig. 8 increases a 3rd capacitor C st3 on the basis of Fig. 6, and its top crown is electrically connectedThe first circuit point P (N), bottom crown input direct-current low-voltage VSS, the Main Function of the 3rd capacitor C st3 is justIt is storage threshold voltage. Described the first drop-down module and the second drop-down circuit framework phase that maintains module of maintainingWith. Owing to itself there is certain parasitic capacitance in the first film transistor T 1 and the second thin film transistor (TFT) T2,Can play the effect of the 3rd capacitor C st3, therefore, in side circuit design, the 3rd capacitor C st3 canRemove.

Refer to Fig. 9 and in conjunction with Fig. 6, Fig. 9 is the first drop-down module the 3rd embodiment that maintains that Fig. 3 adoptsCircuit diagram. Fig. 9 increases a 20 thin film transistor (TFT) T20, its grid electricity on the basis of Fig. 6Property connect N+1 level horizontal scanning line G (N+1), drain electrode is electrically connected second circuit point S (N), source electrode is defeatedEnter DC low-voltage VSS; Described the first drop-down module and the second drop-down circuit framework phase that maintains module of maintainingWith. The main purpose of the 20 thin film transistor (TFT) T20 is to make up N level signal point Q (N) firstStage current potential is not high, and the second circuit point S (N) causing between action period current potential drop-down low not.

Refer to Figure 10 and in conjunction with Fig. 6, Figure 10 be Fig. 3 adopt first drop-downly maintain module the 4th enforcementThe circuit diagram of example. Figure 10 increases on the basis of Fig. 6: the 3rd capacitor C st3, its top crown electrically connectsMeet the first circuit point P (N), bottom crown input direct-current low-voltage VSS; The 20 thin film transistor (TFT) T20,Its grid is electrically connected N+1 level horizontal scanning line G (N+1), and drain electrode is electrically connected second circuit point S (N),Source electrode input direct-current low-voltage VSS. Described the first drop-down module and the second drop-down circuit that maintains module of maintainingFramework is identical.

The first drop-down module 61 and the second drop-down module 62 that maintains of maintaining in gate driver circuit shown in Fig. 3All can replace with any one the drop-down modular circuit framework that maintains in Fig. 6, Fig. 8, Fig. 9, Figure 10,And first drop-downly maintains module 61 and second drop-down to maintain module 62 circuit frameworks identical, its grid after replacingUtmost point drive circuit sequential chart is identical with Fig. 7 a, Fig. 7 b, and the grid shown in its course of work and Fig. 3 drives electricityRoad is identical, therefore repeats no more.

In sum, the invention provides a kind of gate driver circuit with self-compensating function, for existingIn gate driver circuit framework, the drop-down module that maintains is subject to the problem that voltage stress seriously, the most easily lost efficacy, profitControl drop-down the first circuit point P (N) or the tertiary circuit point that maintains module with the boot strap of electric capacityK (N), design can detect the function of thin film transistor (TFT) threshold voltage, and threshold voltage is stored in to the first electricityWaypoint P (N) or tertiary circuit point K (N), and then realize the first circuit point P (N) or tertiary circuit point K (N)Control voltage change along with the threshold voltage shift of thin film transistor (TFT). The present invention has oneself by designCompensate function drop-down maintains module improves the reliability of gate driver circuit long period of operation, falls low-threshold powerPress the impact of drift on gate driver circuit running.

The above, for the person of ordinary skill of the art, can be according to technical scheme of the present inventionMake other various corresponding changes and distortion with technical conceive, and all these changes and distortion all should belong toThe protection domain of the claims in the present invention.

Claims (10)

1. a gate driver circuit with self-compensating function, is characterized in that, comprising: cascadeMultiple GOA unit, according to N level GOA unit controls to viewing area N level horizontal scanning line(G (N)) charging, this N level GOA unit comprises: above draw control module, upper drawing-die piece, pass mould downPiece, the first drop-down module, bootstrap capacitor module and the drop-down module that maintains; Described upper drawing-die piece, first timeDrawing-die piece, bootstrap capacitor module, drop-down holding circuit respectively with N level signal point (Q (N)) andThis N level horizontal scanning line (G (N)) is electrically connected, and draws on described control module and lower transmission module to distinguishBe electrically connected the described drop-down low electricity of module input direct-current that maintains with this N level signal point (Q (N))Press (VSS);
The described drop-down module that maintains adopts the first drop-down module and second that maintains drop-downly to maintain module alternationForm;
Described the first drop-down module that maintains comprises: the first film transistor (T1), its grid is electrically connected theOne circuit point (P (N)), drain electrode is electrically connected N level horizontal scanning line (G (N)), source electrode input direct-currentLow-voltage (VSS); The second thin film transistor (TFT) (T2), its grid is electrically connected the first circuit point (P (N)),Drain electrode is electrically connected N level signal point (Q (N)), source electrode input direct-current low-voltage (VSS); TheThree thin film transistor (TFT)s (T3), its grid is electrically connected the first low-frequency clock signal (LC1) or the first high frequencyClock signal (CK), drain electrode is electrically connected the first low-frequency clock signal (LC1) or the first high frequency clock letterNumber (CK), source electrode is electrically connected second circuit point (S (N)); The 4th thin film transistor (TFT) (T4), its gridBe electrically connected N level signal point (Q (N)), drain electrode is electrically connected second circuit point (S (N)), sourceUtmost point input direct-current low-voltage (VSS); The 5th thin film transistor (TFT) (T5), its grid is electrically connected N-1Level signal point (Q (N-1)), drain electrode is electrically connected the first circuit point (P (N)), and source electrode input direct-current is lowVoltage (VSS); The 6th thin film transistor (TFT) (T6), its grid is electrically connected N+1 level horizontal scanning line(G (N+1)), drain electrode is electrically connected the first circuit point (P (N)), and source electrode is electrically connected N level grid letterNumber point (Q (N)); The 7th thin film transistor (TFT) (T7), its grid is electrically connected the second low-frequency clock signal (LC2)Or second high frequency clock signal (XCK), drain electrode is electrically connected the first low-frequency clock signal (LC1) or theOne high frequency clock signal (CK), source electrode is electrically connected second circuit point (S (N)); The first electric capacity (Cst1),Its top crown is electrically connected second circuit point (S (N)), and bottom crown is electrically connected the first circuit point (P (N));
Described the second drop-down module that maintains comprises: the 8th thin film transistor (TFT) (T8), its grid is electrically connected theThree-circuit point (K (N)), drain electrode is electrically connected N level horizontal scanning line (G (N)), source electrode input direct-currentLow-voltage (VSS); The 9th thin film transistor (TFT) (T9), its grid is electrically connected tertiary circuit point (K (N)),Drain electrode is electrically connected N level signal point (Q (N)), source electrode input direct-current low-voltage (VSS); TheTen thin film transistor (TFT)s (T10), its grid is electrically connected the second low-frequency clock signal (LC2) or the second high frequencyClock signal (XCK), drain electrode is electrically connected the second low-frequency clock signal (LC2) or the second high frequency clockSignal (XCK), source electrode is electrically connected the 4th circuit point (T (N)); The 11 thin film transistor (TFT) (T11),Its grid is electrically connected N level signal point (Q (N)), and drain electrode is electrically connected the 4th circuit point (T (N)),Source electrode input direct-current low-voltage (VSS); The 12 thin film transistor (TFT) (T12), its grid is electrically connected theN-1 level signal point (Q (N-1)), drain electrode is electrically connected tertiary circuit point (K (N)), and source electrode input is straightStream low-voltage (VSS); The 13 thin film transistor (TFT) (T13), its grid is electrically connected N+1 level levelScan line (G (N+1)), drain electrode is electrically connected tertiary circuit point (K (N)), and source electrode is electrically connected N levelSignal point (Q (N)); The 14 thin film transistor (TFT) (T14), when its grid is electrically connected the first low frequencyClock signal (LC1) or the first high frequency clock signal (CK), drain electrode is electrically connected the second low-frequency clock signal(LC2) or the second high frequency clock signal (XCK), source electrode is electrically connected the 4th circuit point (T (N)); TheTwo electric capacity (Cst2), its top crown is electrically connected the 4th circuit point (T (N)), and bottom crown is electrically connected the 3rdCircuit point (K (N)).
2. the gate driver circuit with self-compensating function as claimed in claim 1, is characterized in that,On described, draw control module to comprise the 15 thin film transistor (TFT) (T15), its grid is inputted from N-1 levelThe number of delivering a letter under GOA unit (ST (N-1)), drain electrode is electrically connected at N-1 level horizontal scanning line(G (N-1)), source electrode is electrically connected at this N level signal point (Q (N)); Described upper drawing-die piece bagDraw together the 16 thin film transistor (TFT) (T16), its grid is electrically connected this N level signal point (Q (N)),Drain electrode input the first high frequency clock signal (CK) or the second high frequency clock signal (XCK), source electrode electrically connectsBe connected to N level horizontal scanning line (G (N)); Described lower transmission module comprises the 17 thin film transistor (TFT) (T17),Its grid is electrically connected this N level signal point (Q (N)), drain electrode input the first high frequency clock signal(CK) or the second high frequency clock signal (XCK), source electrode is exported the number of delivering a letter under N level (ST (N));Described the first drop-down module comprises the 18 thin film transistor (TFT) (T18), and its grid is electrically connected N+2 levelHorizontal scanning line (G (N+2)), drain electrode is electrically connected at N level horizontal scanning line (G (N)), and source electrode is defeatedEnter DC low-voltage (VSS); The 19 thin film transistor (TFT) (T19), its grid is electrically connected N+2 levelHorizontal scanning line (G (N+2)), drain electrode is electrically connected at this N level signal point (Q (N)), source electrodeInput direct-current low-voltage (VSS); Described bootstrap capacitor module comprises bootstrap capacitor (Cb).
3. the gate driver circuit with self-compensating function as claimed in claim 2, is characterized in that,In the first order annexation of described gate driver circuit, the grid of the 5th thin film transistor (TFT) (T5) electrically connectsBe connected to circuit start signal (STV); The grid of the 12 thin film transistor (TFT) (T12) is electrically connected at circuitEnabling signal (STV); The grid of the 15 thin film transistor (TFT) (T15) and drain electrode are all electrically connected at circuitEnabling signal (STV).
4. the gate driver circuit with self-compensating function as claimed in claim 2, is characterized in that,In the afterbody annexation of described gate driver circuit, the grid of the 6th thin film transistor (TFT) (T6) is electricalBe connected in circuit start signal (STV); The grid of the 13 thin film transistor (TFT) (T13) is electrically connected at electricityRoad enabling signal (STV); The grid of the 18 thin film transistor (TFT) (T18) is electrically connected at second level levelScan line (G (2)); The grid of the 19 thin film transistor (TFT) (T19) is electrically connected at second level horizontal sweepLine (G (2)).
5. the gate driver circuit with self-compensating function as claimed in claim 1, is characterized in that,Described the first drop-down module that maintains also comprises: the 3rd electric capacity (Cst3), its top crown is electrically connected the first electricityWaypoint (P (N)), bottom crown input direct-current low-voltage (VSS); Described first drop-downly maintains module and secondThe drop-down circuit framework that maintains module is identical.
6. the gate driver circuit with self-compensating function as claimed in claim 1, is characterized in that,Described the first drop-down module that maintains also comprises: the 20 thin film transistor (TFT) (T20), its grid is electrically connected theN+1 level horizontal scanning line (G (N+1)), drain electrode is electrically connected second circuit point (S (N)), source electrode inputDC low-voltage (VSS); Described the first drop-down module and the second drop-down circuit framework that maintains module of maintainingIdentical.
7. the gate driver circuit with self-compensating function as claimed in claim 1, is characterized in that,Described the first drop-down module that maintains also comprises: the 3rd electric capacity (Cst3), its top crown is electrically connected the first electricityWaypoint (P (N)), bottom crown input direct-current low-voltage (VSS); The 20 thin film transistor (TFT) (T20), itsGrid is electrically connected N+1 level horizontal scanning line (G (N+1)), and drain electrode is electrically connected second circuit point(S (N)), source electrode input direct-current low-voltage (VSS); Described the first drop-down module and the second drop-down dimension of maintainingThe circuit framework of holding module is identical.
8. the gate driver circuit with self-compensating function as claimed in claim 2, is characterized in that,Described the first high frequency clock signal (CK) is that two phase places are complete with the second high frequency clock signal (XCK)Contrary high frequency clock signal source; Described the first low-frequency clock signal (LC1) and the second low-frequency clock signal(LC2) be two antipodal low frequency signal sources of phase place.
9. the gate driver circuit with self-compensating function as claimed in claim 2, is characterized in that,Grid and the 19 thin film transistor (TFT) of the 18 thin film transistor (TFT) (T18) in described the first drop-down module(T19) grid is all electrically connected N+2 level horizontal scanning line (G (N+2)), realizes N level gridSignaling point (Q (N)) current potential is three phases, and the first stage is when rising to a high potential and maintaining one sectionBetween, rise again on the basis of a first stage high potential maintain a period of time, the 3rd rank of second stageSection drops to the high potential remaining basically stable with the first stage on the basis of second stage, then utilizes three rankPhase III in section is carried out the self-compensating of threshold voltage.
10. the gate driver circuit with self-compensating function as claimed in claim 9, is characterized in that,Described N level signal point (Q (N)) current potential is three phases, and wherein the variation of phase III is subject toThe impact of six thin film transistor (TFT)s (T6) or the 13 transistor (T13).
CN201410342346.XA 2014-07-17 2014-07-17 There is the gate driver circuit of self-compensating function CN104064158B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410342346.XA CN104064158B (en) 2014-07-17 2014-07-17 There is the gate driver circuit of self-compensating function

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN201410342346.XA CN104064158B (en) 2014-07-17 2014-07-17 There is the gate driver circuit of self-compensating function
US14/398,452 US9524688B2 (en) 2014-07-17 2014-08-14 Self-compensating gate driving circuit
GB1700516.6A GB2543210B (en) 2014-07-17 2014-08-14 Self-compensating gate driving circuit
PCT/CN2014/084339 WO2016008189A1 (en) 2014-07-17 2014-08-14 Gate drive circuit having self-compensation function
KR1020177003660A KR101879145B1 (en) 2014-07-17 2014-08-14 Gate drive circuit having self-compensation function
JP2017502217A JP6321280B2 (en) 2014-07-17 2014-08-14 Gate electrode drive circuit with bootstrap function

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GB2543210B (en) 2020-09-02
GB2543210A (en) 2017-04-12
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WO2016008189A1 (en) 2016-01-21
GB201700516D0 (en) 2017-03-01
CN104064158A (en) 2014-09-24
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US20160260403A1 (en) 2016-09-08
US9524688B2 (en) 2016-12-20

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