CN104034737A - Method for detecting testability of three-dimensional chip - Google Patents
Method for detecting testability of three-dimensional chip Download PDFInfo
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- CN104034737A CN104034737A CN201410265092.6A CN201410265092A CN104034737A CN 104034737 A CN104034737 A CN 104034737A CN 201410265092 A CN201410265092 A CN 201410265092A CN 104034737 A CN104034737 A CN 104034737A
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Abstract
The invention provides a method for detecting the testability of a three-dimensional chip. The method comprises the steps of scanning the chip to be detected under the condition that a safe distance is kept between a probe and the chip to be detected; if the probe is contacted with a test pad under the condition of the safe distance, acquiring the result that the test pad has detects; if the probe is not contacted with the test pad under the condition of the safe distance, enabling the probe to prick into the test pad, and checking the contact condition between the probe and the test pad; if the contact between the probe and the test pad has deviation, acquiring the result that the test pad has detects; if the contact between the probe and the test pad is good, acquiring the result that the test pad does not have defects and the chip to be detected can be normally tested.After the method is adopted, the chip which is about to be detected and has defects can be effectively found out under the condition that the extra cost is not increased, the probe is prevented from testing the chip which is about to be detected and has defects, and the probe is further protected. The method is suitable for large-scale production test, and the testing cost is greatly saved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of in the test of wafer level the detection method of 3 D stereo chip testability.
Background technology
When MEMS (microelectromechanical systems) carries out wafer-level test to 3 D stereo chip, the main interface unit between 3 D stereo chip (being referred to as afterwards chip to be measured) and test machine to be measured is probe.Main cost depletions in test is probe on probe clamp.Cause probe on probe clamp damage for fear of the upper defect of chip testing pad (Pad), need before testing, 3 D stereo chip be checked through this type of defect, indicate the coordinate of defective chip, and in follow-up test, avoid this defective chip, in case probe is caused damage.
Concrete, please refer to Fig. 1, Fig. 1 is the structural representation of chip to be measured and probe in prior art; The structure of MEMS chip to be measured is 3-D solid structure, multiple testing cushion 2 are formed at the surface of chip 1 to be measured, an and outstanding part, be that the surface of testing cushion 2 and chip 1 to be measured is not an aspect, testing cushion 2 is h higher than the projecting height on chip to be measured 1 surface, and projecting height h can reach 200 μ m conventionally to 300 μ m.Due to the testing cushion 2 on chip 1 to be measured is to realize by the processing technology of machine cuts, therefore in the testing cushion 2 of chip 1 to be measured, there will be cutting relic, the broken not congruent defect 3 of cutting, cut fuses, the conventionally outstanding certain altitude of described defect 3, and described defect 3 can cause probe 5 in probe 4 to damage in the time testing.
Prior art scheme adopts near infrared imaging equipment to check the defect of testing cushion on 3 D stereo chip, obtain the 3-D view of 3 D stereo chip by near infrared imaging, then judge the defect of testing cushion on 3 D stereo chip by high speed processor analyzing three-dimensional view data, thereby can locate the defective chip of tool, in the time of follow-up test, avoid the defective chip of tool, and then avoid the infringement of defect to probe.But there are two shortcomings in prior art scheme: the one, inefficiency, is not suitable for scale of mass production test; The 2nd, need professional near infrared imaging equipment and image processing system, with high costs.Because causing prior art scheme, these two shortcomings are unfavorable for 3 D stereo chip to carry out on a large scale, test cheaply.
Summary of the invention
The object of the present invention is to provide a kind of detection method of 3 D stereo chip testability, can obtain quickly and efficiently the coordinate with defective chip, and with low cost.
To achieve these goals, the present invention proposes a kind of detection method of 3 D stereo chip testability, for wafer to be measured is judged to whether the multiple testing cushion in 3 D stereo chip to be measured exist defect, and described method comprises step in the test of wafer level:
Adjusting probe and described chip to be measured keeps a safe distance;
Keep described probe to be positioned at safe distance and described chip to be measured is scanned;
Whether can contact to judge whether testing cushion exists defect by described probe and described testing cushion, if there is contact, there is defect in described testing cushion, if there is not contact, carries out next step;
Adjust described probe and penetrate in described testing cushion, be located at proper testing position;
Judge by the contact condition of described probe and described testing cushion whether testing cushion exists defect, well illustrate that testing cushion does not exist defect if probe contacts with described testing cushion, exist deviation to illustrate that testing cushion exists defect if probe contacts with described testing cushion.
Preferably, the safe distance of adjusting described probe comprises step:
One standard chips is provided, and all there is not defect in the standard testing pad on described standard chips;
Zero clearing is carried out in the position of described probe and rise pin, guarantee that described probe all contacts with described standard testing pad;
Adjust described probe, in the time that described probe and described standard testing pad all depart from, record the now distance value of probe and standard chips, on the basis of described distance value, add an empirical value as safe distance.
Preferably, check by the automatic needle tracking audit function of probe station whether pin trace judges in standard testing pad whether probe all contacts with standard testing pad.
Preferably, whether all connect and judge whether probe all contacts with standard testing pad with standard testing pad by detecting board detector probe.
Preferably, observe pin trace by the automatic needle tracking audit function of probe station and whether disappear to judge whether probe and standard testing pad all depart from.
Preferably, whether all disconnect and judge whether probe and standard testing pad all depart from by detection board detector probe and standard testing pad.
Preferably, in probe penetrates testing cushion after, the contact condition of described probe and described testing cushion is observed pin trace by the automatic needle tracking audit function of probe station and whether in testing cushion, is judged whether probe good with contacting of testing cushion.
Preferably, in probe penetrates testing cushion after, whether the contact condition of described probe and described testing cushion is all connected and is judged whether probe contacts with testing cushion good with testing cushion by detecting board detector probe.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: in the situation that probe and chip to be measured keep a safe distance, chip to be measured is scanned, if probe exists and contacts with testing cushion under safe distance, illustrate that testing cushion exists defect; If there is not contact, make probe penetrate in testing cushion, and check the contact condition of probe and testing cushion, if contact exists deviation, illustrate that testing cushion exists defect, if contact is good, illustrate that testing cushion does not exist defect, this chip to be measured can be tested.Adopt said method in the situation that not increasing extra cost, to find and to provide defective chip to be measured efficiently, avoid probe to test the defective chip to be measured of tool, thereby can protect probe.Said method is applicable to produce test in enormous quantities, greatly saves testing cost.
Brief description of the drawings
Fig. 1 is the structural representation of chip to be measured and probe in prior art;
Fig. 2 is the process flow diagram of the detection method of 3 D stereo chip testability in one embodiment of the invention;
Fig. 3 is the structural representation that one embodiment of the invention middle probe all contacts with standard testing pad;
Fig. 4 is the schematic diagram that one embodiment of the invention middle probe and standard testing pad all contact rear pin trace;
Fig. 5 is the structural representation that one embodiment of the invention middle probe and standard chips keep a safe distance;
Fig. 6 is the structural representation that one embodiment of the invention middle probe contacts with defect in chip to be measured;
Fig. 7 is the discontiguous structural representation of defect in one embodiment of the invention middle probe and chip to be measured;
Fig. 8 is that one embodiment of the invention middle probe penetrates the structural representation in testing cushion;
Fig. 9 is the schematic diagram that one embodiment of the invention middle probe penetrates pin trace in the defective testing cushion of tool.
Embodiment
Below in conjunction with schematic diagram, the detection method of 3 D stereo chip testability of the present invention is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, in the present embodiment, proposed a kind of detection method of 3 D stereo chip testability, for wafer to be measured is judged to whether multiple testing cushion of 3 D stereo chip to be measured exist defect, and described method comprises step in the test of wafer level:
S100: adjust probe and described chip to be measured and keep a safe distance;
S200: keep described probe to be positioned at safe distance and described chip to be measured is scanned;
S300: whether have to contact to judge whether testing cushion exists defect by described probe and described testing cushion, if there is contact, described testing cushion exists defect, if there is not contact, carries out next step;
S400: adjust described probe on the appointment chip to be measured on wafer to be measured and penetrate in described testing cushion, be located at proper testing position;
S500: judge by the contact condition of described probe and described testing cushion whether testing cushion exists defect, well illustrate that testing cushion does not exist defect if probe contacts with described testing cushion, exist deviation to illustrate that testing cushion exists defect if probe contacts with described testing cushion.
Please refer to Fig. 3 to Fig. 5, in the present embodiment, step S100 comprises:
One standard chips 10 being provided, having multiple standard testing pads 20 on described standard chips 10, all there is not defect in described standard testing pad 20;
Zero clearing is carried out in the position of described probe 31 and rise pin, guarantee that described probe 31 all contacts with described standard testing pad 20, as shown in Figure 3;
Adjust described probe 31, in the time that described probe 31 all departs from described standard testing pad 20, as shown in Figure 5, record the distance value of probe now 31 and standard chips 10, on the basis of described distance value, add an empirical value as safe distance h1, described empirical value is less than the height value that is gone out defect by analysis of experimental data conventionally.
Please refer to Fig. 4, in the present embodiment, check that by the automatic needle tracking audit function of probe station 30 whether pin trace 32 judges whether probe 31 all contacts with standard testing pad 20 in standard testing pad 20 is interior, while only having pin trace 32 to be all positioned at described standard testing pad 20, just show that described probe 31 all contacts with standard testing pad 20.Wherein, described probe station 30 carries automatic needle tracking audit function, can check that probe 31 pricks the pin trace 32 on described standard testing pad 20.
Same, can observe pin trace 32 by the automatic needle tracking audit function of probe station and whether disappear to judge whether probe 31 and standard testing pad 20 all depart from, and only have in the time that pin trace 32 disappears completely, could assert that probe 31 and standard testing pad 20 all depart from.
Whether be positioned in standard testing pad 20 except observing pin trace 32, can also whether all connect and judge whether probe 31 all contacts with standard testing pad 20 with standard testing pad 20 by detecting board detector probe 31.Same, detection board has the function of detector probe 31 on-off (Open-short), in the time that probe 31 contacts with standard testing pad 20, detects board and can detect that probe 31 is in on-state by above-mentioned functions.In the time that probe 31 does not contact with standard testing pad 20, detect board and the state of probe 31 in disconnecting can be detected.Whether what therefore, adopt that this mode can be sensitiveer judges probe 31 and contacts with standard testing pad 20.
Same, can whether all disconnect and judge whether probe 31 and standard testing pad 20 all depart from by detection board detector probe 31 and standard testing pad 20.Only have when detecting when board detects that probe 31 all disconnects with standard testing pad 20 and could assert that probe 31 and standard testing pad 20 all depart from.
Please refer to Fig. 6, keep described probe 31 to be positioned at safe distance h1 and described chip 100 to be measured is scanned, if there is the defect 210 being formed by relic in testing cushion 200, therefore its both height H 1 is usually above the height of testing cushion 200, even, higher than safe distance h1, using the probe 31 of the h1 that keeps a safe distance to scan, is highly the defect 210 of H1 if exist, will inevitably come in contact with probe 31, thereby can detect defect 31.Because defect 210 is the relic of described testing cushion 200, in the time that probe 31 contacts with described defect 210, be defaulted as described probe 31 and contact with described defect 210.
Therefore, same, can adopt and judge in two ways whether probe 31 exists and contact with testing cushion 200: one, judge with the on-off of testing cushion 200 whether probe 31 exists and contact with chip 100 to be measured by detecting board detector probe 31; Whether two, carry out observation test pad 200 by the automatic needle tracking audit function of probe station exists pin trace 32 to judge whether probe 31 exists and contact with testing cushion 200.
Please refer to Fig. 7, because some defect 210 is little, the height H 2 that itself and testing cushion 200 are superimposed is less than safe distance h1, therefore probe 31 can't come in contact with defect 210, now, can adjust described probe 31 and penetrate in described testing cushion 200, be located at proper testing position, as shown in Figure 8; Now, if testing cushion 200 exists defect 210, the syringe needle of probe 31 can bend or lateral deviation, penetrates other places or unsettled.
Therefore, can adopt detection board detector probe 31 whether all to connect and judge whether probe 31 contacts with testing cushion 200 good with testing cushion 200, if a part does not contact well, still there is defect 210 in explanation, if contact is all good, illustrate that this chip 100 to be measured does not have any defect 210, can carry out follow-up test.
Same, please refer to Fig. 9, can adopt the automatic needle tracking audit function of probe station to observe pin trace 32 and whether judge whether probe 31 is good with contacting of testing cushion 200 in testing cushion 200 is interior, if there is defect 210, can cause as the situation in Fig. 9, one of them pin trace 32 can deflect away from testing cushion 200, therefore can judge that this testing cushion 200 exists defect 210, is not suitable for carrying out follow-up test.
After judging whether chip 100 to be measured has defect 210, can position or mark it, in the time of follow-up test, need to avoid the chip to thering is defect 210 to test, can protect probe can not damaged by defect 210.Meanwhile, the method that the present embodiment proposes does not all have extra increase equipment, has reduced greatly the production cost required to Defect Scanning, and improve efficiency, by required 20 minutes of professional near infrared imaging equipment Inspection defect, be reduced to about 8 minutes, be applicable to testing on a large scale.
To sum up, in the detection method of the 3 D stereo chip testability providing in the embodiment of the present invention, chip to be measured on probe and wafer to be measured keeps a safe distance, chips to be measured all on wafer to be measured is scanned, if the testing cushion of probe and chip to be measured exists and contacts under safe distance, illustrate testing cushion exist a kind of exceed safe distance defect; If there is not contact, the testing cushion that chip to be measured is described do not exist exceed safe distance defect.The decision method whether probe contacts with testing cushion is that all chips to be measured carry out in scanning process on to wafer to be measured, for example, according to certain sweep frequency (100 chips to be measured of every scanning), on the appointment chip to be measured of wafer to be measured, probe is penetrated in its testing cushion, and the pin trace that uses probe station self-verifying testing cushion is the position that probe contacts with testing cushion, if there is deviation in probe location, there is defect in the testing cushion that this region chip to be measured is described, if probe location is good, there is not defect in the testing cushion that this region chip to be measured is described, the chip to be measured in this region can carry out formal test.Adopt said method in the situation that not increasing extra cost, to find and to provide defective chip to be measured efficiently, avoid probe to test the defective chip to be measured of tool, thereby can protect probe.Said method is applicable to produce test in enormous quantities, greatly saves testing cost.
Above are only the preferred embodiments of the present invention, the present invention is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of technical scheme of the present invention; the technical scheme that the present invention is disclosed and technology contents make any type of variations such as replacement or amendment that are equal to; all belong to the content that does not depart from technical scheme of the present invention, within still belonging to protection scope of the present invention.
Claims (8)
1. a detection method for 3 D stereo chip testability, for wafer to be measured is judged to whether the multiple testing cushion in 3 D stereo chip to be measured exist defect, and described method comprises step in the test of wafer level:
Adjusting probe and described chip to be measured keeps a safe distance;
Keep described probe to be positioned at safe distance and described chip to be measured is scanned;
Whether can contact to judge whether testing cushion exists defect by described probe and described testing cushion, if there is contact, there is defect in described testing cushion, if there is not contact, carries out next step;
Adjust described probe and penetrate in described testing cushion, be located at proper testing position;
Judge by the contact condition of described probe and described testing cushion whether testing cushion exists defect, well illustrate that testing cushion does not exist defect if probe contacts with described testing cushion, exist deviation to illustrate that testing cushion exists defect if probe contacts with described testing cushion.
2. the detection method of 3 D stereo chip testability as claimed in claim 1, is characterized in that, the safe distance of adjusting described probe comprises step:
One standard chips is provided, and all there is not defect in the standard testing pad on described standard chips;
Zero clearing is carried out in the position of described probe and rise pin, guarantee that described probe all contacts with described standard testing pad;
Adjust described probe, in the time that described probe and described standard testing pad all depart from, record the now distance value of probe and standard chips, on the basis of described distance value, add an empirical value as safe distance.
3. the detection method of 3 D stereo chip testability as claimed in claim 2, is characterized in that, checks by the automatic needle tracking audit function of probe station whether pin trace judges in standard testing pad whether probe all contacts with standard testing pad.
4. whether the detection method of 3 D stereo chip testability as claimed in claim 2, is characterized in that, all connect and judge whether probe all contacts with standard testing pad with standard testing pad by detecting board detector probe.
5. the detection method of 3 D stereo chip testability as claimed in claim 2, is characterized in that, observes pin trace whether disappear to judge whether probe and standard testing pad all depart from by the automatic needle tracking audit function of probe station.
6. whether the detection method of 3 D stereo chip testability as claimed in claim 2, is characterized in that, all disconnected and judged whether probe and standard testing pad all depart from by detection board detector probe and standard testing pad.
7. the detection method of 3 D stereo chip testability as claimed in claim 1 or 2, it is characterized in that, after in probe penetrates testing cushion, described probe is observed pin trace with the contact condition of described testing cushion by the automatic needle tracking audit function of probe station and whether in testing cushion, is judged whether probe is good with contacting of testing cushion.
8. the detection method of 3 D stereo chip testability as claimed in claim 1 or 2, it is characterized in that, after in probe penetrates testing cushion, whether described probe is all connected and is judged whether probe contacts with testing cushion good with testing cushion by detecting board detector probe with the contact condition of described testing cushion.
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| CN109444713A (en) * | 2018-11-13 | 2019-03-08 | 无锡中微腾芯电子有限公司 | A kind of wafer test contact fault diagnostic method |
| CN110045269A (en) * | 2019-05-09 | 2019-07-23 | 肇庆学院 | A kind of apparatus for testing chip and method |
| CN113945830A (en) * | 2021-10-21 | 2022-01-18 | 上海华岭集成电路技术股份有限公司 | Detection method of integrated circuit |
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