CN104025262B - Air gap interconnection and the method formed with cap layer - Google Patents

Air gap interconnection and the method formed with cap layer Download PDF

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Publication number
CN104025262B
CN104025262B CN201180075949.2A CN201180075949A CN104025262B CN 104025262 B CN104025262 B CN 104025262B CN 201180075949 A CN201180075949 A CN 201180075949A CN 104025262 B CN104025262 B CN 104025262B
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China
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interconnection
layer
dielectric layer
air gap
cap layer
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CN201180075949.2A
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Chinese (zh)
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CN104025262A (en
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K·费希尔
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英特尔公司
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Priority to PCT/US2011/067906 priority Critical patent/WO2013101096A1/en
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Publication of CN104025262B publication Critical patent/CN104025262B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclose the air gap interconnection structure with cap layer and the method for forming this air gap interconnection structure.There is provided the substrate with dielectric layer, the dielectric layer has the multiple interconnection formed wherein.It is closed that each interconnection is blocked layer.Hard mask is formed on the dielectric layer, and patterns the hard mask to expose the dielectric layer of the expectation air gap between adjacent interconnection.Dielectric layer is etched to form at least a portion of groove, the wherein other etch stop layer of the etch process, with a part for the side surface for exposing each adjacent copper-connection.On the expose portion that cap layer chemistry is plated to the expose portion of top surface and side surface, to reseal interconnection.Clearance seal dielectric layer is formed on device, so that sealed groove is to form air gap.

Description

Air gap interconnection and the method formed with cap layer

Technical field

The present invention relates generally to the manufacture of semiconductor devices.Especially, embodiments of the invention, which are related to have, prevents interconnection The diffusion and electromigration of material are interconnected with the air gap for improving the cap layer of interlinking reliability.

Background technology

As microprocessor becomes faster and smaller, integrated circuit (IC), which becomes more complicated and part, to be become more to encrypt Collection.By sending and/or receiving the conductive trace and via (referred to collectively as " interconnection ") connection IC parts that electric signal passed through.It is logical Cross mosaic technology and be typically formed interconnection, thus conductive material is deposited to the hole being etched in Semiconductor substrate and groove In.Each interconnection and neighbouring interconnection are electrically insulated by adjacent material.However, the dielectric resistance matter of backing material enable to it is adjacent Interconnection between Capacitance Coupled, which increase chip power requirement and to signal transmit interference.

As device size reduces, interconnection dimensions and spacing also reduce, and this causes the current density and resistance of increase, and The greater risk of electromigration, Capacitance Coupled and RC retardation ratio.In addition, interconnection material can be spread in surrounding dielectric material, from And reduce dielectric insulation ability and cause to produce crosstalk between adjacent interconnection and part.Although can be by using stop Layer is closed to be interconnected to control diffusion and electromigration, but additional barrier material may increase the resistance and size of interconnection.

Nearest innovation solves Capacitance Coupled by being incorporated to air gap between neighbouring interconnection.Air has extremely low Jie Electric constant (about 1, compared to silica about 4), and therefore can more effectively isolate adjacent mutual than solid dielectric material Even.

Brief description of the drawings

Figure 1A shows the sectional view of cover (hood) layer mutually connected in air gap according to an embodiment of the invention.

Figure 1B shows the sectional view of the conformal lining and cap layer mutually connected in air gap according to an embodiment of the invention.

Fig. 2A -2N show to be used to form the method that the air gap with cap layer is interconnected according to an embodiment of the invention.

Fig. 3 A show the sectional view of the groove between being interconnected according to an embodiment of the invention at two, wherein will stop Layer is removed completely from the interconnection side wall adjacent with groove.

Fig. 3 B show mutually connecting the sectional view for the cap layer to be formed, wherein cap layer covering phase according to an embodiment of the invention The whole side surface of adjacent interconnection.

Fig. 3 C show cap layer according to an embodiment of the invention shown in Fig. 3 B have be increased it is adjacent mutual to be enclosed in The sectional view of the extra play of air gap between even.

Fig. 4 A show the sectional view of the conformal lining formed according to an embodiment of the invention on cap layer and in air gap.

Fig. 4 B show what is formed according to an embodiment of the invention on the air gap interconnection with cap layer and conformal lining The sectional view of additional dielectric layer.

Fig. 5 shows computing device according to an embodiment of the invention.

Embodiment

Describe for the air gap interconnection structure in integrated circuit with cap layer and this with cap layer for being formed The process of air gap interconnection.Describe embodiments of the invention for detail to provide the thoroughly reason to the present invention Solution.It will be understood by those skilled in the art that the present invention can be put into practice in the case of these no details.In other examples In, known semiconductor technology and equipment are not had a detailed description, so as not to unnecessarily obscure the present invention.In addition, The not be the same as Example shown in figure be it is illustrative expression and be not drawn necessarily to scale.

Interconnected there is disclosed herein the air gap interconnection structure with cap layer and for forming this air gap with cap layer Method.Must be prevented by one or more barrier seal interconnection surfaces interconnection material be diffused into adjacent dielectric layer and In device layer, prevent due to the electromigration of interconnection material caused by electric current, and prevent the oxidation of interconnection material, all this It may cause device fault a bit.In addition, air gap is used for by using the air with low-down dielectric constant (k=~1) To replace dielectric substance (k=~4) to reduce the Capacitance Coupled between adjacent interconnection.In order to form air gap, patterning is hard Dielectric substance is etched away to produce groove by mask to expose the dielectric surface between adjacent interconnection.Etch work Skill may also remove the part on barrier layer, so that exposure interconnection surface.In order to reseal interconnection after the etching, in interconnection Cap layer is optionally deposited on exposed surface.A part for the top surface of cap layer covering interconnection and the side adjacent with groove of interconnection The part on surface, and by preventing diffusion, electromigration and oxidation from improving device reliability.On whole interconnection structure Thickness deposition clearance seal dielectric layer, so as to shrink (pinch off) on groove, air gap is formed with sealed groove.

Another embodiment of the present invention also includes conformal lining, and it is by sealing hard mask/cap layer and cap layer/barrier layer Interface prevents interconnection material to be diffused into the Additional Protection in surrounding dielectric material to provide.Conformal lining be it is non-selective and On the other surfaces for being conformally deposited on the inside of hard mask, cap layer and restriction groove.Expose and mutually connecting in groove In the embodiment of the part on barrier layer, conformal lining covering barrier layer surface is to prevent oxidation.Additional conformal lining may be used also To improve the reliability of air gap interconnection.

Figure 1A -1B show the air gap interconnection structure according to an embodiment of the invention on substrate.Air gap is interconnected A part for structure comprising the multi-stage devices for forming integrated circuit.Air gap is interconnected for by the not at the same level of integrated circuit Connect active and passive device.It should be appreciated that the integrated circuit including air gap interconnection structure is also included within comprising air gap interconnection The extra play of the layer above and below of structure.However, for discussion purposes, only showing air gap interconnection structure in figure.

Air gap interconnection structure 100 according to an embodiment of the invention is shown in figure ia, and wherein air gap 104 is arranged on phase Between adjacent interconnection 102A, to reduce the Capacitance Coupled that interconnection is subjected to.In embodiment, pass through the covering interconnection of cap layer 105 102A Top surface 116 and side surface 117 a part, to prevent being diffused into surrounding dielectric material of interconnection material, prevent mutually Connect the electromigration of material and prevent the oxidation of interconnection surface.Some interconnection 102 have the mistake for the lower floor for being connected to integrated circuit Hole, such as via 140.Interconnection 102B is opened remote enough with adjacent interconnection barriers, this interconnection will not be from due to air gap Separate and huge benefit.Air gap interconnection structure 100 also includes the dielectric 101 supported by substrate 118, the shape in dielectric 101 Into interconnection 102.Additional metal level can be formed on the substrate 118 of the above and below of dielectric 101.

By cap layer 105, barrier layer 109 and hard mask 103 come closed interconnection 102A, to prevent interconnection material to be diffused into neighbour Electromigration in the material and element that connect, to prevent interconnection material and prevent the oxidation of interconnection surface.Hard mask 103 is covered A part for the top surface of dielectric 101 and interconnection 102A top surface 116.In embodiment, cap layer 105 formed exposed to In interconnection surface firmly between mask 103 and barrier layer 109.In embodiment, the covering interconnection of cap layer 105 102A two surfaces A part, for example, top surface 116 and side surface 117.In another embodiment, the covering of cap layer 105 interconnection 102A three tables The part in face, such as two side surfaces 117 and top surface 116.In embodiment, cap layer 105 provides required protection, With the diffusion and electromigration of the interconnection material for preventing from being formed the surface where cap layer 105.

In embodiment, cap layer 105 is selectively formed on interconnection 102A exposed surface, to improve interconnection Reliability.Cap layer 105 can be can be by any materials of chemical plating.Cap layer 105 can also can be prevented in interconnection 102A Material diffusion, any materials of electromigration and/or oxidation.In an embodiment of the present invention, cap layer 105 is cobalt or cobalt alloy, Such as, but not limited to tungsten-cobalt alloy, cobalt tungsten phosphide or cobalt boron phosphide.Cap layer 105, which has, to be enough to prevent the diffusion of interconnection material With the uniform thickness of electromigration, but it is sufficiently thin with not excessively increase interconnection 102A electric capacity.The thickness of cap layer may be typically smaller than 20nm, and more typically from 5-15nm.In embodiment, the thickness of cap layer 105 is 10nm.

Air gap 104 is located between adjacent interconnection 102A, and the adjacent interconnection 102A is closely spaced and therefore by extremely low K materials separation and benefit.Embodiments in accordance with the present invention, air gap 104 is filled with the air of low-k (k=~1), To reduce the Capacitance Coupled between adjacent interconnection.In another embodiment, air gap 104 is about 1 filled with dielectric constant Gas.

In embodiment, as shown in Figure 1A, air gap 104 is extended to below interconnection 102A basal surface.In another embodiment In, the depth 120 that air gap 104 is extended between interconnection 102A.The width of air gap 104 can be typically from 40 to 100nm, and gas The depth of gap 104 can be from 50 to 200nm scope.Air gap can be used for the interconnection for being smaller than 160nm.

In an embodiment of the present invention, the air gap 104 served as a contrast is done without dielectric substance.As shown in Figure 1A, in particular implementation In example, barrier layer 103 and cap layer 105 are in only material layer between air gap and interconnection.In another specific embodiment, cover Layer 105 is will to interconnect the sole material separated with air gap.

In embodiment, the top table of the covering dielectric 101 of clearance seal dielectric layer 107, hard mask 103 and cap layer 105 Face, and further define and seal the top of air gap 104.Clearance seal dielectric layer 107 can right and wrong conformally deposit Any dielectric substance, such as silica, carbon doped silicon oxide and porous carbon of the usual dielectric constant in the range of 2 to 4 is mixed Miscellaneous silica.In embodiment, clearance seal dielectric layer is used for the next stage for forming interconnection or device.

In another embodiment, the additional coverage gap encapsulated dielectric layer 107 of body interlayer dielectric (ILD) 108, with Extra insulation is provided between the interconnection layer and any top or the device layer of bottom shown.In embodiment, body ILD108 Dielectric constant be less than clearance seal dielectric layer 107 dielectric constant.Can be by being suitable for mitigating in the device subsequently formed Any materials (e.g., including low k materials of carbon doped oxide, porous dielectric, Fluorin doped oxide etc. of crosstalk between layer Material) form body ILD108.In addition, body ILD108 can be used for the next stage to form interconnection or device.

Figure 1B shows the sectional view of another embodiment of the present invention, wherein conformal lining 106 is alternatively also provided by preventing Only the supplementary protection of diffusion and the electromigration of interconnection material improves interlinking reliability.In embodiment, conformal lining 106 is in cover Continuous sealing is formed on layer/hard mask interface 121 and on cap layer/stop bed boundary 122.In embodiment, conformal lining Layer 106 is situated between with the surface of hard mask 103 and cap layer 105, the arbitrary portion of exposure in air gap 104 on barrier layer 109 and electricity The arbitrary portion of the exposure between adjacent interconnection 102A of matter 101 is conformal (conform).In an embodiment of the present invention, it is conformal Lining 106 have the material that is enough that hermetic seal is produced on cap layer/hard mask interface 121 or cap layer/stop bed boundary 122 and Thickness.In embodiment, conformal lining 106 is and the hard identical material of mask 103.In another embodiment, conformal lining 106 It is the materials different from hard mask 103.Conformal lining 106 is SiNC in embodiment.In another embodiment, conformal lining 106 be SiN or SiC or Al2O3.In embodiment, conformal lining 106 have be enough to prevent barrier layer 109 with the phase of air gap 104 The material and thickness of adjacent arbitrary portion oxidation.The thickness of conformal lining 106 can be 2-12nm.In embodiment, conformal lining The thickness of layer is 5nm.

Fig. 2A -2N show the embodiment for forming the method that the air gap with cap layer is interconnected.Air gap interconnection structure can be with , will such as transistor, capacitor, resistor and inductor in multilevel interconnection structure or microelectromechanical systems (MEMS) Various active and passive devices be electrically interconnected into functional circuit, so as to form integrated circuit.Form the cover in interconnection surface Layer improves the reliability of interconnection.

There is provided the substrate 200 by air gap interconnection is formed wherein as shown in Figure 2 A.Semiconductor structure can include partly leading Body substrate 218, such as, but not limited to monocrystalline silicon, germanium, SiGe and/or iii-v composite semiconductor, such as GaAs and InP.Substrate 200 can also include any metallization formed before and dielectric alternating layer.

Embodiments in accordance with the present invention, substrate 200 also includes dielectric 201.Dielectric 201 can be adapted for serving as being used for Any materials of the substrate of multiple air gap interconnection.In an embodiment of the present invention, dielectric 201 is silica.Replaceable In embodiment, dielectric 201 can include low k dielectric material, for example silicate, carbon doped oxide, Fluorin doped oxide, Porous dielectric material etc..Any appropriate technique (for example inlay, dual damascene or subtract method) can be passed through in substrate 200 Form interconnection.

In embodiment, as shown in Fig. 2 B-C, mosaic technology is used to form interconnection 102, and plurality of groove 250 is etched And filled with conductive material.First, as shown in Figure 2 B, etched in dielectric 201 in the position that will form interconnection multiple Groove 250.Some grooves can have via, to be connected to following device or layer.Groove is formed in the dielectric material to exist It is known in semiconductor applications, such as, is sheltered and etch process by a series of.

Next, as shown in Figure 2 C, barrier layer 209 is conformally deposited on the surface of groove 250.Can be by electricity Jie Arbitrarily suitable technology (such as physical vapour deposition (PVD) (PVD), the chemistry of conformal or almost conformal layer is provided on matter 201 Vapour deposition (CVD) or ald (ALD)) form barrier layer 209.Barrier layer 209 includes being suitable to prevent in interconnection Electromigration, the oxidation for preventing interconnection, provide in electroplating technology for nucleation surface and prevent interconnection material to be diffused into week Enclose any material in part.In embodiment, barrier layer 209 includes tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or its combination.Resistance Barrier 209 has the thickness from 1 to 25nm for being enough to prevent that interconnection material from spreading.In embodiment, the thickness on barrier layer 209 is 2nm。

Interconnection 202 is formed in the groove 250 served as a contrast is done by barrier layer 109.Interconnection 202 includes being capable of any suitable of conduction Material.In one embodiment, interconnection 202 is made up of copper, aluminium, silver or its alloy.Can be by known in the art any Suitable technique (such as plating, CVD, PVD) forms interconnection 202.For example, in mosaic technology, first via plating or change Learn and plate copper blanket deposit over the entire structure.Unnecessary copper is polished off, copper is left in the trench to form interconnection.Such as Fig. 2 C institutes Show, interconnection 202 can be that 20-100nm is wide and 30-160nm is deep.In embodiment, interconnection 202 is that 40nm is wide and 80nm It is deep.Interconnection 102 can be spaced apart 16-100nm.In embodiment, interconnection 202 is spaced apart 40nm.

Implementation as shown in Figure 2 D is exemplified, and hard mask 203 is then formed on body structure surface.Hard mask 203 includes Suitable for serving as etch stop by protecting the low portion of dielectric 201 and interconnection 102 during subsequent etch process Any materials.Mask 203 can also include being suitable to by preventing a barrier type layer for bottom interconnection material diffusion and electromigration firmly Effect any materials.In an embodiment of the present invention, hard mask 203 includes SiNC.Hard mask 203, which has, is enough to act as erosion Carve the thickness thick from 5-20nm for stopping and also preventing interconnection material from spreading.In embodiment, the thickness of hard mask 203 is 8nm. Hard mask 203 can be formed by arbitrarily suitable technique (such as via CVD blanket deposit).

Next, being sheltered and etching technique using known, covered firmly with being limited on the dielectric 201 for will be formed air gap Film 203, such as in interconnection tight spacing and by from the region to benefit is separated by low-down k dielectric.Show in Fig. 2 E In the specific embodiment gone out, photoetching stack layer 214 is formed on hard mask 203.Photoetching stack layer 214 can firmly be covered including carbon Film 210, anti-reflecting layer 211, photoresist 212 or other photoetching materials known in the art.

In embodiment, carbon hardmask 210 is formed on the surface in hard mask 203.Carbon hardmask 210 can be with Any material in the case that the etch process of etching air gap is selective to the dielectric substance on carbon hardmask material Material, such as porous amorphous carbon.Carbon hardmask 210, which has, to be enough to keep out dielectric and interconnection of the etch process without exposure bottom The thickness on surface.In embodiment, carbon hardmask 210 is 1000nm thick.Can by arbitrarily suitable technique (for example spinning or CVD) carbon hardmask 210 is formed.

Anti-reflecting layer 211 is formed on the surface in carbon hardmask 210.Anti-reflecting layer 211 can be used for by absorbing The wavelength of the light of lithography process prevents any materials of light scattering and the distortion of photoengraving pattern, such as spin-on-glass material. In embodiment, the thickness of anti-reflecting layer 211 is 350nm.

In embodiment, photoresist 212 is formed on anti-reflecting layer 211.Embodiment according to Fig. 2 E, makes With it is known shelter, exposed and developed technique patterns photoresist 212, to limit with the opening for expecting air gap interconnection 230 mask.Opening 230 is aligned in being removed on the part for the groove that air gap is expected with formation for dielectric 201, example Such as, between the interconnection for the close interval that will benefit from improved isolation.

Next, as shown in Figure 2 F, anti-reflecting layer 211 alignedly being etched with photoresist 212 and is covered firmly with exposing carbon Film 210.Arbitrarily suitable technology (such as plasma etching) etching anti-reflecting layer 211 can be used.In fig 2g, according to this hair Bright embodiment, carbon hardmask 210 is alignedly etched with anti-reflecting layer 211, to expose hard mask 203.Dry method can be passed through Plasma etching, carbon hardmask 210 is etched using epoxide chemical characteristic.

In the embodiment shown in Fig. 2 H, anti-reflecting layer is alignedly etched with the opening 230 that is limited by carbon hardmask 210 211st, hard mask 203 and dielectric 201.A part for dielectric 201 is removed, to form groove between adjacent interconnection 202 215.The depth of groove 215 can be that, from 35 to 200nm, the spacing generally to the interconnection for this layer is proportional.In embodiment In, as illustrated in figure 2h, groove 215 is extended to below the basal surface of interconnection 202.In another embodiment, such as the dotted line in Fig. 2 H Shown, groove 215 is extended at the depth 220 between interconnection 202.

Groove 215 is etched using any appropriate chemical characteristic (such as fluorine based chemistry characteristic) known in the art.Erosion Carving technology removes at least a portion on barrier layer 209, with least a portion for the side surface 217 for exposing interconnection 202.Change erosion Carve chemical characteristic and can control the amount that barrier layer 209 is etched.In embodiment, such as CxHyFzEtch depth chemical characteristic work as It etches dielectric 201 to form during groove 215 deposited polymer layer on barrier layer 209.Polymeric layer protects barrier layer 209 A part from etch process chemical composition.In embodiment, as illustrated in figure 2h, the sputtering composition of etch process removes resistance A part for barrier 209 and the drift angle that interconnection 202 can be chamfer.

Embodiments in accordance with the present invention, as shown in figure 2i, then remove the residue of carbon hardmask 210.In embodiment, Carbon hardmask 210 is removed by cineration technics.In an embodiment of the present invention, the hard mask 203 of lower floor is not removed.As being applicable, Structure can be cleaned, to remove the etch residues for being included in any polymer formed on trenched side-wall.

Next, as shown in fig. 2j, after etching groove 215, forming cap layer 205 to reseal interconnection surface. In embodiment, cap layer 205 is formed selectively on the more than one surface of interconnection 202, to prevent the spreading of interconnection material, electricity Migration and oxidation.In embodiment, it is formed selectively on the top surface 216 of interconnection 202 and the expose portion of side surface 217 Cap layer 205.In embodiment, cap layer 205 is formed selectively by chemical plating, wherein the structure is placed into chemical plating fluid In.Electroless chemical plating is selected, with exposed interconnection surface but not in hard mask 203, barrier layer 209 or dielectric The cover material layer of depositing homogeneous thickness on 201 exposed surface.

Cap layer 205 can be can be by any materials of chemical plating.Cap layer 205, which can also be, can prevent interconnection material Diffusion and any materials of electromigration.Material for cap layer 205 can also be resistance to oxidation and prevent the oxygen of the interconnection 202 of bottom Any materials of change.In an embodiment of the present invention, cap layer 205 is cobalt or cobalt alloy, for example but is not restricted to cobalt tungsten alloy, cobalt Tungsten phosphide or cobalt boron phosphide.Cap layer 205, which has, to be enough to prevent the uniform thickness of interconnection material diffusion and electromigration, but enough The thin resistance not excessively to increase interconnection 202.In embodiment, cap layer 205 is thicker than barrier layer 209.The thickness of cap layer 205 can With from 5-15nm.In embodiment, the thickness of cap layer 205 is 10nm.

Next, as shown in figure 2k, clearance seal dielectric layer 207 is by blanket deposit in hard mask 203 and cap layer 205 On top surface and sealing air gap 204.Clearance seal dielectric layer 207 can by can on the surface of the structure non-general character Any materials composition of ground formation so that the material shrinks on groove 215.In an embodiment of the present invention, clearance seal Dielectric layer 207 includes silica.In alternative embodiments, clearance seal dielectric layer 207 includes silicon nitride, silicic acid Salt, carbon doped oxide, Fluorin doped oxide, porous dielectric material etc..The thickness of clearance seal dielectric layer 207 can be 80 to 300nm.In embodiment, the thickness of clearance seal dielectric layer 207 is 160nm.Foot known in the art can be passed through Clearance seal dielectric layer 207 is formed to form dielectric layer and be not filled with any means of groove.

Embodiments of the invention according to Fig. 2 L, optionally form sacrifice on clearance seal dielectric layer 207 Light absorbing material (SLAM) layer 213 so that the surface planarisation of structure.SLAM layers 213 and clearance seal dielectric layer 207 A part is etched by covering as shown in figure 2m.Times for being enough to planarize body structure surface being known in the art can be used Meaning etch process, such as, but not limited to non-selective dry method etch technology.

Body ILD208 can be formed on clearance seal dielectric 207, is electrically isolated as needed positioned at shown layer The device layer of above and below.Body ILD208 can be by suitable for mitigating the string between interconnection 202 and the device layer subsequently formed Any materials disturbed are formed.In an embodiment of the present invention, body ILD208 is silica.In alternative embodiments, body ILD208 includes silica, silicon nitride, silicate, carbon doped oxide, Fluorin doped oxide, porous dielectric material etc.. Body ILD208 can be formed by arbitrarily suitable method (such as CVD).

In the another embodiment of the present invention shown in Fig. 3 A-C, cap layer 305 forms the whole side surface in interconnection 302 On 317.Fig. 3 A show that it includes substrate 318, dielectric for example as the structure prepared by the above-mentioned technique on Fig. 2A -2I 301st, hard mask 303 and interconnection 302, the interconnection 302 can have via 340.In the embodiment shown in Fig. 3 A, use Etch process that all or essentially all of barrier layer 309 is removed from side surface 317 and etching chemistry characteristic etch groove 315.Such as NF can be passed through3Fluorine based etch etch groove 315, it does not form protectiveness polymer on etching surface Layer, and therefore can completely or almost completely etch stop layer 309, so as to expose the lower side surfaces 317 of interconnection 302. In embodiment, as shown in Figure 3A, the sputtering composition of etch process can chamfer the drift angle adjacent with groove 315 of interconnection 302.

Next, as shown in Figure 3 B, the optionally deposition shield in a part for top surface 316 and whole side surfaces 317 Layer 105.In embodiment, as described by above with respect to Fig. 2 J, electroless deposition cap layer 305 is used.Shown in Fig. 3 C Embodiment in, can be sealed formed by as described by above with respect to Fig. 2 K by clearance seal dielectric layer 307 Air gap 305.As described by above with respect to Fig. 2 L-2N body can be formed on clearance seal dielectric layer 307 ILD308。

Fig. 4 A-4B show another embodiment of the present invention, as described by above with respect to Figure 1B, wherein in structural table Conformally depositing conformal lining 406 on face and in groove 415, to prevent interconnection material from wearing hard mask/He of cap layer interface 421 Pass through the diffusion of cap layer/stop bed boundary 422.In Figure 4 A, conformal liner deposition above with respect to Fig. 2A -2J for example as retouched Formed by stating on structure, and the structure includes substrate 418, dielectric 401, hard mask 403 and interconnection 402, the interconnection 402 can have via 440.Can be by producing any of the layer conformal or almost conformal with the exposed surface of structure 400 Suitable technology (such as ALD or CVD) forms conformal lining 406.

Next, as shown in Figure 4 B, 407 and body ILD408 of clearance seal layer can be formed on conformal lining 406.Root According to embodiments of the invention, clearance seal dielectric layer 407 seals the top of the groove limited by conformal lining 406, to be formed Air gap 404.For formed the material and process of clearance seal dielectric layer 407 and body ILD408 such as above with respect to Figure 1A -1B and As 2K-2N is discussed.

Fig. 5 shows the computing device 500 of an implementation according to the present invention.The accommodates plate 502 of computing device 500.Plate 502 can include a variety of parts, including but not limited to processor 504 and at least one communication chip 506.The physics of processor 504 Be electrically coupled to plate 502.In some implementations, at least one communication chip 506 is also physically and electrically coupled to Plate 502.In other implementation, communication chip 506 is a part for processor 504.

According to its application, computing device 500 can include physically and electrically being coupled to its of plate 502 Its part.These other parts include but is not limited to volatile memory (for example, DRAM), nonvolatile memory (for example, ROM), flash memory, graphics processor, digital signal processor, cipher processor, chipset, antenna, display, touch-screen are shown Device, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) equipment, compass, accelerometer, gyroscope, loudspeaker, camera and mass-memory unit (such as hard disk drive, light Disk (CD), digital versatile disc (DVD) etc.).

Communication chip 506 can realize the radio communication for the transmission that computing device 500 is come and gone for data.Term " wireless " And its derivative can be used for description can be come by using the modulated electromagnetic radiation via non-solid medium communication data circuit, Equipment, system, method, technology, communication port etc..The term does not imply that the equipment of correlation does not include any electric wire, although They can not include electric wire in some embodiments.Communication chip 506 can realize any one in a variety of wireless standards or agreement, Including but not limited to Wi-Fi (IEEE802.11 series), WiMAX (IEEE802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, its growth with And it is designated as any other wireless protocols in 3G, 4G, 5G and Geng Gao generation.Computing device 500 can include multiple communication chips 506.For example, the first communication chip 506 can be exclusively used in relatively short distance radio communication, such as Wi-Fi and bluetooth, and the second communication core Piece 506 can be exclusively used in the radio communication of relatively long distance, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO.

The processor 504 of computing device 500 includes the integrated circuit lead being encapsulated in processor 504.The present invention's In some implementations, the integrated circuit lead of processor includes having cover according to the one or more of implementation of the present invention The air gap interconnection of layer.Term " processor " can refer to electronic data of the processing from register and/or memory with by the electronics Any equipment or the part of equipment of the data conversion into the other electronic data being storable in register and/or memory.

Communication chip 506 also includes the integrated circuit lead being encapsulated in communication chip 506.According to another reality of the present invention Existing mode, the integrated circuit lead of communication chip includes one or more gas with cap layer of the implementation according to the present invention Gap is interconnected.

In other implementation, another part being contained in computing device 500 can include integrated circuit lead, It includes one or more air gap interconnection with cap layer of the implementation according to the present invention.

In different implementations, computing device 500 can be laptop computer, netbook computer, notebook meter Calculation machine, super notebook, smart phone, tablet PC, personal digital assistant (PDA), super mobile PC, mobile phone, on table Type computer, server, printer, scanner, monitor, set top box, amusement control unit, digital camera, portable music Player or digital video recorder.In other implementation, computing device 500 can be any other of processing data Electronic equipment.

Claims (18)

1. a kind of semiconductor devices, including:
Substrate with dielectric layer, the dielectric layer has multiple interconnection formed therein, wherein each interconnection has Top surface and side surface;
Air gap between adjacent interconnection;
Multiple conductive cap layer, wherein each conduction cap layer contacts the top table of the corresponding interconnection in the adjacent interconnection At least a portion of each in face and the side surface;And
Cover the barrier layer of a part for the side surface each interconnected.
2. semiconductor devices according to claim 1, wherein what the free Co and Co alloys of the conductive shield layer choosing were constituted Group.
3. semiconductor devices according to claim 1, wherein the thickness of conductive shield layer is 5-15nm.
4. semiconductor devices according to claim 1, wherein the adjacent interconnection is copper.
5. semiconductor devices according to claim 1, is additionally included in the clearance seal dielectric above the conductive cap layer Layer, wherein the clearance seal dielectric layer seals the air gap.
6. semiconductor devices according to claim 1, wherein the barrier layer be selected from by tantalum, tantalum nitride, titanium, titanium nitride, The group constituted with ruthenium.
7. semiconductor devices according to claim 1, in addition to conformal lining, wherein the conformal lining and the conduction Between interface and the air gap and the dielectric layer between the top surface of cap layer, the conductive cap layer and the air gap Interface it is conformal.
8. a kind of method for forming semiconductor devices, including:
The substrate with dielectric layer is provided, the dielectric layer has multiple interconnection formed therein, wherein each interconnection With top surface and side surface;
Hard mask is formed on said dielectric layer, and patterns the hard mask to expose the institute between adjacent interconnection State dielectric layer surface;
It is etched in the dielectric layer between two adjacent interconnection to form groove, wherein the etch process exposes often At least a portion of the side surface of individual adjacent interconnection;And
On the part exposed that cap layer chemistry is plated to the part exposed of the top surface and each side surface.
9. method according to claim 8, wherein by the trench etch to the feather edge in the adjacent interconnection with Under depth.
10. method according to claim 8, wherein by the trench etch to the feather edge in the adjacent interconnection with On depth.
11. method according to claim 8, wherein the cap layer is selected from the group being made up of Co and Co alloys.
12. method according to claim 8, wherein the thickness of the cap layer is 5-15nm.
13. method according to claim 8, wherein the adjacent interconnection is copper.
14. method according to claim 8, in addition to:
Barrier layer is formed on the side surface;And
At least a portion on the barrier layer is etched, to expose the side surface.
15. method according to claim 14, wherein the barrier layer is selected from by tantalum, tantalum nitride, titanium, titanium nitride and ruthenium The group constituted.
16. method according to claim 8, is additionally included in formation clearance seal dielectric layer above the groove, wherein The clearance seal dielectric layer seals the groove to form air gap.
17. method according to claim 8, in addition to conformal lining is formed, wherein the conformal lining and the cap layer Top surface and the groove edge it is conformal.
18. a kind of method for forming semiconductor devices, including:
The substrate with dielectric layer is provided, the dielectric layer has multiple copper-connections formed therein, wherein each copper Interconnection has top surface and side surface, and wherein described side surface is blocked layer covering;
Hard mask is formed on said dielectric layer;
The hard mask is patterned with the part on the surface for exposing the dielectric layer between adjacent copper-connection;
The dielectric layer between the adjacent copper-connection is etched in form groove, wherein the etch process etches institute At least a portion on barrier layer is stated with a part for the side surface for exposing each adjacent copper-connection;
On the part exposed that cobalt cap layer chemistry is plated to the part of the exposure of the top surface and each side surface;
Clearance seal dielectric layer is formed on the hard mask, the cobalt cap layer and the groove, wherein the clearance seal Dielectric layer seals the groove to form air gap.
CN201180075949.2A 2011-12-29 2011-12-29 Air gap interconnection and the method formed with cap layer CN104025262B (en)

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