CN104022091B - 半导体芯片封装 - Google Patents

半导体芯片封装 Download PDF

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CN104022091B
CN104022091B CN201410070947.XA CN201410070947A CN104022091B CN 104022091 B CN104022091 B CN 104022091B CN 201410070947 A CN201410070947 A CN 201410070947A CN 104022091 B CN104022091 B CN 104022091B
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contact element
interarea
die package
semiconductor die
chip
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CN104022091A (zh
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K.侯赛因
J.马勒
R.沃姆巴赫
T.沃夫拉
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Infineon Technologies Austria AG
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Abstract

半导体芯片封装包括：载体；半导体芯片，包括第一主面和与第一主面相反的第二主面，芯片接触元件被设置在半导体芯片的第一或第二主面的一个或多个上；密封层，覆盖半导体芯片的第一主面，密封层包括面对载体的第一主面和远离载体的第二主面；第一接触元件，被设置在密封层的第二主面上，第一接触元件中的每一个连接到芯片接触元件中的一个；以及第二接触元件，被设置在密封层的第一主面上，第二接触元件中的每一个连接到芯片接触元件中的一个。

Description

半导体芯片封装
技术领域
本发明涉及半导体芯片封装。
背景技术
在半导体芯片封装的制造领域中，可以观察到对于以半导体芯片封装满足消费者的个体需要的方式来制造它们的增加的期望。工业消费者具有对于高效地将半导体封装附着到像印刷电路板（PCB）这样的板和在销售之前对板的性能和功能进行质量检查的期望。半导体芯片在它们的一个或多个表面上包括接触焊盘或接触元件。在半导体芯片封装中，半导体芯片嵌入或容纳在芯片封装内，并且半导体芯片的接触焊盘连接到芯片封装的外部接触元件。期望制造半导体芯片封装使得它们的外部接触元件允许在将半导体芯片封装附着到板方面的更高灵活度，并且还允许半导体芯片封装的模块化适用性，具体地允许将另外的器件连接到半导体芯片封装的可能性。
附图说明
附图被包括来提供对实施例的进一步理解，并且被并入本说明书和构成本说明书的一部分。这些图图示了实施例并且与说明书一起用来解释实施例的原理。将容易意识到其他实施例和实施例的许多意图的优点，因为它们通过参考以下详细描述而得到更好的理解。图中的元件不一定是相对于彼此按比例的。相同的参考数字指明对应的类似部分。
图1A和1B示出了用于图示半导体芯片封装的示例的示意性顶视图表示（图1A）和横截面侧视图表示（图1B），该半导体芯片封装具有与附加的外部接触引脚连接的附加的外围接触区；
图2A-2C示出了用于图示半导体芯片封装的示例的示意性横截面侧视图表示，其中，与图1A和1B的示例相比较，用密封材料填充载体与外部接触引脚之间的空间；
图3A-3C示出了用于图示半导体芯片封装的示例的示意性横截面侧视图表示，其中，与图1A和1B及图2的示例相比较，外部接触引脚被暴露；
图4A-4C示出了用于图示半导体芯片封装的示例的示意性横截面侧视图表示，该半导体芯片封装包括另外的接触区；
图5A-5C示出了用于图示半导体芯片封装的示例的示意性横截面侧视图表示，除了图4的示例之外，该半导体芯片封装包括另外半导体芯片施加的接触区；以及
图6A-6C示出了用于图示半导体芯片封装的示例的示意性横截面侧视图表示，除了图4的示例之外，该半导体芯片封装包括施加于接触区的另外器件。
具体实施方式
现在参考附图来描述各方面和实施例，其中，相同的参考数字一般贯穿全文用于指代相同的元件。在下面的描述中，出于解释的目的，阐述了许多具体细节以便提供对实施例的一个或多个方面的透彻理解。然而，对于本领域技术人员可以清楚的是，可以在较少程度的具体细节的情况下实践实施例的一个或多个方面。在其他实例中，以示意形式示出了已知结构和元件以便利于描述实施例的一个或多个方面。应理解，在不脱离本发明的范围的情况下可以利用其他实施例并且可以做出结构或逻辑改变。还应注意，附图并不是按比例或不一定是按比例的。
另外，尽管可以仅关于若干实现之一来公开实施例的具体特征或方面，但是如对于任何给定或具体应用可以期望的并且有利的，此类特征或方面可以与其他实现的一个或多个特征或方面相组合。此外，就措辞“包括”、“具有”、“带有”或它们的其他变体用在详细描述或权利要求中而言，此类措辞意图以类似于措辞“包含”类似的方式是包含性的。可以使用措辞“耦合”和“连接”及其派生词。应当理解，这些措辞可以用于指示两个元件彼此协作或交互，而不管它们是直接物理或电接触还是它们不是彼此直接接触。此外，措辞“示例性”仅仅意为示例而非最佳或最优。因此，不以限制意义进行以下详细描述，并且本发明的范围由所附权利要求来限定。
半导体芯片封装的实施例可以使用各种类型的半导体芯片或合并在半导体芯片中的半导体芯片模块或电路，其中包括逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS（微电机系统）、功率集成电路、带有集成无源元件的芯片、像续流（flyback）二极管这样的二极管等等。实施例还可以使用这样的半导体芯片，该半导体芯片包括MOS晶体管结构或垂直晶体管结构像例如IGBT（绝缘栅双极晶体管）结构，或者一般地包括其中至少一个电接触焊盘布置在半导体芯片的第一主面上并且至少一个其他电接触焊盘布置在半导体芯片的第二主面上的晶体管或其他结构或器件，该第二主面与半导体芯片的第一主面相反。半导体芯片还可以包括像诸如发光二极管、激光二极管或光学接收机二极管这样的光学器件。
半导体芯片可以在它们的一个或多个外表面上包括接触元件或接触焊盘，其中接触元件用于电接触半导体芯片。接触元件可以具有任何期望的形式或形状。例如，它们可以具有岸面形式，即在半导体芯片的外表面上的平坦接触层。接触元件或接触焊盘可以由任何导电材料或导电有机材料或导电半导体材料制成，所述导电材料例如像诸如铝、金或铜这样的金属或金属合金。接触元件还可以形成为上述材料中的一个或多个的层堆叠。
半导体芯片封装的实施例可以包括密封剂或密封材料，其具有嵌入在其中的半导体芯片或半导体芯片模块。密封材料可以是任何电绝缘材料，例如像任何种类的模制材料、任何种类的树脂材料或任何种类的环氧树脂材料。密封材料还可以是聚合物材料、聚酚亚胺材料、热塑性塑料材料、硅酮材料、陶瓷材料以及玻璃材料。密封材料还可以包括上述材料中的任何一种，并且进一步包括嵌入在其中的填充材料，例如像导热增量（increment）。这些填充增量可以例如由AlO或Al2O3、AlN、BN或SiN制成。通过该方法的实施例制作的半导体芯片面板可以具有晶片的形式，即圆形形式，但是并不限于晶片的形式和形状，而是可以具有嵌入在其中的半导体芯片或半导体芯片模块的任何尺寸和形状以及任何合适的布置。
半导体器件的实施例可以包括单独半导体芯片或半导体芯片模块中的一个或多个。半导体芯片模块可以包括一个或多个半导体芯片，具体地功率晶体管芯片，并且它们可以包括至少一个另外的半导体芯片，该另外的半导体芯片可以包括逻辑电路或驱动器电路中的一个或多个。具体地，半导体芯片模块可以包括所谓的智能功率模块（IPM）。半导体器件还可以包括如上面所提及的任何其他种类的半导体芯片。半导体器件可以包括以堆叠配置布置，即以一个在另一个之上的不同级别布置的半导体芯片。半导体器件还可以包括彼此连接以形成桥电路的半导体芯片，该桥电路即诸如用于功率开关模块的那些的半桥电路或全桥电路。
图1示出了顶视图表示（图1A）和沿线A-A、B-B以及C-C的三个不同横截面侧视图表示（图1B）的半导体芯片封装10的示例。半导体芯片封装10包括载体11、半导体芯片12以及芯片接触元件12A、12B和12C，半导体芯片12包括上部第一主面和与上部第一主面相反的下部第二主面以及连接第一和第二主面的侧面，芯片接触元件12A、12B和12C设置在第一或第二主面的一个或多个上。半导体芯片12可以在第二下部主面面对面对载体11的情况下施加在载体11上。半导体芯片封装10还包括覆盖半导体芯片12的上部第一主面和侧面的密封层13，密封层13包括面对载体11的下部第一主面13A和远离载体11的上部第二主面13B。半导体芯片封装10还包括设置在密封层13的上部第二主面13B上的第一接触元件14A、14B和14C，其中第一接触元件14A、14B和14C中的每一个连接到芯片接触元件12A、12B和12C中的一个。半导体芯片封装10还包括设置在密封层13的下部第一主面13A上的第二接触元件15A、15B和15C，其中第二接触元件15A、15B和15C中的每一个连接到芯片接触元件12A、12B和12C中的一个。
如将在下文进一步详细概述的，图1的和在本申请中示出的进一步示例的半导体芯片封装10在将半导体芯片封装连接到像印刷电路板（PCB）这样的板的可能方式方面并且还在将另外的器件连接到半导体芯片封装的可能方式方面包括增加的功能性、实用性和有用性。半导体芯片封装10可以以表面安装器件（SMD）的形式来制作，其中第一电接触元件可以用作用于将半导体芯片封装连接到板的装置。半导体芯片封装10还可以制作为通孔器件，其中第二电接触元件15A-C可以用作用于将半导体芯片封装10连接到板的装置。此外，第一电接触元件14A-C或第三电接触元件（在图1A和1B中未示出）可以用作用于将半导体芯片封装10连接到另外的器件的装置。
根据图1的半导体芯片封装10的实施例，第一电接触元件14A-C被配置为施加在密封层13的第二主面13B上的接触层。要用于第一电接触元件14A-C的材料可以是任何导电材料，例如像铜或铜合金，并且可以通过例如流电镀（galvanic plating）、电镀或无电镀来沉积这些层。
根据图1的半导体芯片封装10的实施例，第二电接触元件15A-C被配置为细长的线性元件，例如像引线、引脚或杆。
根据图1的半导体芯片封装10的实施例，第二电接触元件15A-C设置在一个且与载体11相同的平面中并且在该平面中延伸。具体地，第二电接触元件之一（15C）可以形成为载体11的延伸，并且其还可以与载体11邻接地被形成。
根据图1的半导体芯片封装10的实施例，第二电接触元件15A-C可以设置在一个且相同的平面内并且包括相同厚度。具体地，第二电接触元件15A-C可以包括布置在一个且相同的平面内的上部表面和布置在一个且相同的平面内的下部表面。此外，载体11也可以布置在一个且与第二电接触元件15A-C相同的平面内，并且可以具有与第二电接触元件15A-C的上部表面共面的上部表面和与第二电接触元件15A-C的下部表面共面的下部表面。具体地，载体11和第二电接触元件15A-C可以源自一个且相同的引线框架，该引线框架在制作过程开始时是邻接的并且然后在制作过程期间分离成不同部分。
根据图1的半导体芯片封装10的实施例，第二电接触元件15A-C中的每一个通过形成在密封层13中的电贯穿连接13.1、13.2或13.3连接到第一接触元件14A-C中的一个。
根据图1的半导体芯片封装10的实施例，半导体芯片12包括电器件，该电器件包括在半导体芯片12的第一主面处的至少一个接触元件和在半导体芯片12的第二主面处的至少一个接触元件。
根据图1的半导体芯片封装10的实施例，半导体芯片12包括垂直晶体管、MOS晶体管、IGB（绝缘栅双极）晶体管以及功率晶体管中的一个或多个。具体地，半导体芯片12包括设置在第一主面上的源极接触元件、设置在第一主面上的栅极接触元件以及设置在第二主面上的漏极接触元件。
根据图1的半导体芯片封装10的实施例，半导体芯片12包括范围从5μm-150μm的厚度。
根据图1的半导体芯片封装10的实施例，密封层13包括绝缘材料、模制材料、层压板（laminate）、聚合物材料、聚酚亚胺材料、树脂材料、环氧树脂材料、硅酮材料、陶瓷材料以及玻璃材料中的一个或多个，其中这些材料中的每一个可以包括嵌入在其中的填充增量。
根据图1的半导体芯片封装10的实施例，第一接触元件14A-C可以与图1A和1B中所示出的在密封层13的第二主面13B上的电贯穿连接13.1-13.3右侧的外围接触区相连接。
根据图1的半导体芯片封装10的实施例，半导体芯片封装10还包括设置在密封层13的第二主面上的第三接触元件。具体地，第三接触元件中的每一个可以通过形成在密封层13中的电贯穿连接而连接到第二接触元件15A-C中的一个。这将在下文的示例中进一步详细示出。
根据图1的半导体芯片封装10的实施例，如果可用的话，半导体芯片封装10还包括设置在第一接触元件的一个或多个上或者在第三接触元件的一个或多个上的至少一个另外的器件。具体地，该另外的器件包括半导体芯片、集成电路、无源器件、电容器、电感器、线圈、电阻器以及散热器中的一个或多个。
图2A-2C图示了半导体芯片封装20的进一步示例。图2的半导体芯片封装与图1A和1B中示出的半导体芯片封装类似，从而将不再次描述具有相同参考符号的元件。相对于图1A和1B的半导体芯片封装10的差异在于密封层13包括突起13C和13D，突起13C和13D在垂直向下方向从密封层13延伸到在载体11与第二接触元件15A和15B之间的空间中。这可以通过使密封材料流入在载体11与第二接触元件15A和15B之间的空的空间中来实现。通过该措施，可以增强器件的耐电击穿。
图3A-3C图示了半导体芯片封装30的进一步示例。作为与之前示例的差异，图3的半导体芯片封装30包括暴露在外部的第二电接触元件35A-C。因此以通孔器件的形式来制作半导体芯片封装30，该通孔器件可以通过通孔技术（THT）安装在板上，其中第二电接触元件35A-C被推入通过或插入通过板。图3的半导体芯片封装30可以例如通过将第二电接触元件35A-C激光焊接到密封层13的下部表面13A来制作。
图4A-4C图示了半导体芯片封装40的进一步示例。作为与之前示例的差异，图4的半导体芯片40包括以接触层的形式布置在密封层13的第二主面13B上的第三电接触元件41A-C。第三电接触层41A-C中的每一个可以通过形成在密封层13中的电贯穿连接42A、42B或42C与第二电接触元件15A-C中的一个相连接。第三电接触元件41A-C可以用作用于在其上安装另外的器件的电接触层。
图5A-5C示出了半导体芯片封装50的进一步示例。作为与图4A-4C中示出的示例的差异，图5的半导体芯片50包括另外的电器件。具体地，半导体芯片封装50包括安装在第一电接触元件14A上的第一集成电路芯片51和安装在第一电接触元件14C上的第二集成电路芯片52。第一和第二集成电路芯片51和52之一或二者可以用作用于控制半导体芯片12的性能的控制器芯片。集成电路芯片51和52之一或二者也可以安装在第三电接触元件41A-C的一个上。
图6A-6C示出了半导体芯片封装60的进一步示例。作为与图5A-5C中示出的示例的差异，将其他器件安装在第一电接触元件14A和14C上。散热器61安装在第一电接触元件14A上。散热器61可以例如由铜或铜合金的块构成，并且可以意图消散半导体芯片12中生成的热。此外，例如像电容器这样的无源器件62安装在第一电接触元件14C上。再次，器件61和62中的一个或多个也可以施加在第三电接触元件41A-C的一个上。
尽管已经关于一个或多个实现图示和描述了本发明，但是可以在不脱离所附权利要求的精神和范围的情况下对所示的示例做出更改和/或修改。特别关于上面描述的部件或结构（组件、器件、电路、系统等）执行的各种功能，除非另有所指，否则用于描述此类部件的术语（包括对“装置”的引用）意图对应于执行所描述的部件的特定功能的任何部件或结构（例如，功能上等同的部件或结构），即使这些部件或结构与所公开的、执行本文所示的本发明示例性实现中的功能的结构在结构上并不等同。

Claims (18)

1.一种半导体芯片封装，包括：
载体；
半导体芯片，包括第一主面和与第一主面相反的第二主面，其中，芯片接触元件被设置在半导体芯片的第一或第二主面的一个或多个上，并且其中，半导体芯片被设置在载体上；
密封层，覆盖半导体芯片的第一主面，密封层包括面对载体的第一主面和远离载体并与第一主面相反的第二主面，其中，密封层不覆盖载体的至少一个侧面；
第一接触元件，被设置在密封层的第二主面上，第一接触元件中的每一个连接到芯片接触元件中的一个；以及
第二接触元件，被设置在密封层的第一主面上，第二接触元件中的每一个连接到芯片接触元件中的一个，
其中，所有第二电接触元件被设置和完全延伸在与载体相同的平面中，并且第二接触元件中的至少一个与载体连续地形成；并且
其中，第一和第二接触元件被布置在半导体芯片封装的相反的主面上。
2.根据权利要求1所述的半导体芯片封装，其中，第一电接触元件被配置为施加在密封层的第二主面上的接触层。
3.根据权利要求1所述的半导体芯片封装，其中，第二电接触元件被配置为引脚。
4.根据权利要求1所述的半导体芯片封装，其中，第二接触元件中的每一个通过形成在密封层中的电贯穿连接而连接到第一接触元件中的一个。
5.根据权利要求1所述的半导体芯片封装，其中，半导体芯片包括垂直晶体管、MOS晶体管、IGB晶体管或功率晶体管。
6.根据权利要求5所述的半导体芯片封装，其中，半导体芯片包括设置在第一主面上的源极接触元件、设置在第一主面上的栅极接触元件以及设置在第二主面上的漏极接触元件。
7.根据权利要求1所述的半导体芯片封装，其中，载体和第二接触元件从一个且相同的引线框架制作。
8.根据权利要求1所述的半导体芯片封装，还包括设置在第一接触元件中的一个或多个上的另外的器件。
9.根据权利要求8所述的半导体芯片封装，其中，所述另外的器件包括半导体芯片、集成电路、电容器、电感器、线圈、电阻器或散热器。
10.根据权利要求1所述的半导体芯片封装，还包括设置在密封层的第一主面上的第三接触元件。
11.根据权利要求10所述的半导体芯片封装，其中，第三接触元件中的每一个通过形成在密封层中的电贯穿连接而连接到第二接触元件中的一个。
12.一种半导体芯片封装，包括：
半导体芯片，包括第一主面和与第一主面相反的第二主面，半导体芯片还包括设置在第一或第二主面的一个或多个上的芯片接触元件；
第一外部接触元件，被配置为接触层，其中，接触层中的每一个与芯片接触元件中的一个相连接；以及
第二外部接触元件，被配置为接触引脚，其中，接触引脚中的每一个与芯片接触元件中的一个相连接，并且其中，半导体芯片封装被配置为表面安装器件并且还被配置为通孔安装器件。
13.根据权利要求12所述的半导体芯片封装，其中，第一外部接触元件被布置在半导体芯片的平面的一侧，并且第二外部接触元件被布置在半导体芯片的所述平面的另一侧。
14.根据权利要求12所述的半导体芯片封装，其中，半导体芯片包括范围从5μm-150μm的厚度。
15.一种半导体芯片封装，包括：
载体，
设置在所述载体上的半导体芯片；
密封层，覆盖半导体芯片，密封层包括第一主面和与第一主面相反的第二主面；
第一外部接触元件，被设置在密封层的第二主面上并且与半导体芯片相连接；以及
第二外部接触元件，被设置在密封层的第一主面上并且与半导体芯片相连接，其中，载体和第二外部接触元件由同一引线框架制造，并且其中，第二外部接触元件完全延伸平行于载体及与载体相同的平面中。
16.根据权利要求15所述的半导体芯片封装，其中，第一外部接触元件被配置为接触层，并且第二外部接触元件被配置为引脚。
17.根据权利要求15所述的半导体芯片封装，还包括：第三外部接触元件，被设置在密封层的第二主面上并且与半导体芯片相连接。
18.根据权利要求17所述的半导体芯片封装，其中，第三外部接触元件被配置为接触层并且被设置在一个且与第一外部接触元件相同的平面中。
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