CN103987212A - Supporting substrate for manufacturing multilayer wiring substrate and multilayer wiring substrate manufacturing method - Google Patents
Supporting substrate for manufacturing multilayer wiring substrate and multilayer wiring substrate manufacturing method Download PDFInfo
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- CN103987212A CN103987212A CN201310488460.9A CN201310488460A CN103987212A CN 103987212 A CN103987212 A CN 103987212A CN 201310488460 A CN201310488460 A CN 201310488460A CN 103987212 A CN103987212 A CN 103987212A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
The invention provides a supporting substrate for manufacturing a multilayer wiring substrate and a multilayer wiring substrate manufacturing method, wherein the supporting substrate is capable of increasing yield, reducing manufacturing cost, and improving manufacturing efficiency. The supporting substrate (70) used when the multilayer wiring substrate is manufactured comprises a supporting substrate body (71) and a stacked metallic sheet body (81). The supporting substrate body (71) comprises substrate main surface (72). The stacked metallic sheet body (81) is configured on the substrate main surface (72) and is formed in a manner that a base side metal layer (82) and a surface side metal layer (83) can be tightly contacted in strippable states. In addition, the profile dimension of the side metal layer (82) is set larger than that of the surface side metal layer (83).
Description
Technical field
The present invention relates to have by the supporting substrates of the multi-layer wire substrate manufacture use of multiple resin insulating barriers and the structure that multiple conductor layer is alternately laminated and multiple stratification forms and used the manufacture method of the multi-layer wire substrate of supporting substrates.
Background technology
The semiconductor integrated circuit element (IC chip) using as the microprocessor of computer etc. is just constantly high speed, multifunction in recent years, accompanies therewith, and number of terminals increases, and the spacing between terminal also exists the tendency narrowing.In general, on the bottom surface of IC chip, be array-like ground and dispose thick and fast multiple terminals, this terminal group is connected with the form of flip-chip and the terminal group of motherboard side.But because the spacing between the terminal in the terminal group of IC chip side and the terminal group of motherboard side exists larger difference, it is more difficult therefore IC chip being directly connected on motherboard.Therefore, employing making is a kind of is conventionally mounted in gimmick such on motherboard in IC chip carrying by the semiconductor package body forming on circuit board and by this semiconductor package body by IC chip carrying.
As the IC chip carrying circuit board that forms this packaging body, practical application has a kind of surface at core substrate and the back side to be formed with the multi-layer wire substrate of lamination (Japanese: PVC Le De ア ッ プ) layer.In this multi-layer wire substrate, as core substrate, for example, use the resin substrate (glass epoxy substrate etc.) that resin-dipping is formed in reinforcing fibre.And, utilize the rigidity of this core substrate, by the alternately laminated resin insulating barrier in the surface at core substrate and the back side and conductor layer, thereby form lamination layer.That is, in this multi-layer wire substrate, core substrate plays the effect of reinforcement, forms very thickly compared with lamination layer.In addition, in core substrate, run through the wiring (specifically, being via conductors etc.) being formed with for realizing the conducting between the lamination layer being formed on surface and the back side.
But in recent years, being accompanied by the high speed of semiconductor integrated circuit element, the signal frequency using becomes high frequency band.In this case, the wiring that runs through core substrate contributes to produce larger inductance, causes the transmission loss of high-frequency signal, the generation of circuit erroneous action, has hindered high speed.Therefore, proposed multi-layer wire substrate to be made as the technology that there is no the centreless of core substrate circuit board.So, thereby owing to omitting relatively thick core substrate, overall length of arrangement wire is shortened, therefore the transmission loss of high-frequency signal reduces, and can make semiconductor integrated circuit element move at high speed.
In addition, centreless circuit board for example utilizes following gimmick manufacture to form (for example, with reference to patent documentation 1).As shown in figure 10, first, prepare the supporting substrates 101 being formed by glass epoxy resin and the laminated metal lamellar body 104(peelable type Copper Foil that base side metal forming 102 and top layer side metal forming 103 are formed with the state close contact that can peel off).Then the laminated metal sheet that, carries out arranging at the board main 105 of supporting substrates 101 and substrate back 106 laminated metal lamellar body 104 arranges operation.Afterwards, by carrying out on laminated metal lamellar body 104 multiple resin insulating barriers and multiple conductor layer is alternately laminated and the stacked operation of multiple stratification (lamination operation), obtain lit-par-lit structure body (lamination layer).And then, by the removing step of carrying out removing together with supporting substrates 101 than the periphery of product area position being in the outer part positioned in lit-par-lit structure body, the interface (interface between base side metal forming 102 and top layer side metal forming 103) of peeling off of laminated metal lamellar body 104 is exposed.Afterwards, by carrying out the separation circuit of the interfacial separation between base side metal forming 102 and top layer side metal forming 103, separate stacked tectosome from supporting substrates 101, obtain the slim multi-layer wire substrate that there is no core substrate.
Patent documentation 1: TOHKEMY 2007-214427 communique (paragraph [0055], Figure 12 etc.)
But the laminated metal lamellar body 104 shown in Figure 10 is formed by following mode.First, on each face 105,106 of supporting substrates 101, configure duplexer 109(with reference to Figure 11), this duplexer 109 is made up of with the metal forming 107,108 that area and the shape of face 105,106 equate area and shape.Then, in metal forming 108, carry out the lamination operation of lamination as the dry film (diagram is omitted) of etching mask.And then, carry out making the exposure process of dry film exposure and dry film after exposure being developed and remove the developing procedure of the peripheral part of dry film across photomask, make the peripheral part of duplexer 109 be exposed to surface.Then the peripheral part, carrying out by carrying out etching and removing metal forming 107,108 makes the peripheral part of face 105,106 be exposed to surperficial etching work procedure.Afterwards, remove the dry film removing step of dry film, thereby form the laminated metal lamellar body 104 shown in Figure 10.
But if carry out the etching to metal forming 107,108, etching solution likely enters the interface between metal forming 107 and metal forming 108, therefore exist the rising of substandard products generation rate and rate of finished products to reduce such problem.For example, utilizing manufacturing line to carry supporting substrates 101 while carry out in etched situation, the meeting such as deflector roll sometimes contacts with the outer peripheral edges of metal forming 107,108.Now, if the outer peripheral portion of metal forming 108 is crispaturaed, metal forming 108 will be peeled off quickly, therefore exists a large amount of etching solutions to enter the such problem in interface.In addition, in the time forming laminated metal lamellar body 104, need to carry out the so multiple operations of lamination operation, exposure process, developing procedure, etching work procedure, dry film removing step (amounting to five operations), therefore exist increase man-hour inevitable, manufacturing cost rises, manufacture the such problem of Efficiency Decreasing.
Summary of the invention
The present invention completes in view of the above problems, and its 1st object is to provide a kind of supporting substrates that reduces, manufactures the multi-layer wire substrate manufacture use of efficiency raising that can improve rate of finished products and can realize manufacturing cost.In addition, the 2nd object is to provide a kind of manufacture method of the preferred multi-layer wire substrate that has used above-mentioned supporting substrates.
As the technical scheme addressing the above problem (technical scheme 1), a kind of supporting substrates of multi-layer wire substrate manufacture use is provided, it uses in the time that thereby manufacture has the multi-layer wire substrate of the structure that multiple resin insulating barriers and the alternately laminated multiple stratification of multiple conductor layer are formed, it is characterized in that, this supporting substrates comprises: supporting substrates main body, and it has board main; And laminated metal lamellar body, it is disposed at aforesaid substrate first type surface, and this laminated metal lamellar body is by making base side metal level and top layer side metal level form with the state close contact that can peel off; The overall dimension of above-mentioned base side metal level is set greatlyr than the overall dimension of above-mentioned top layer side metal level.
Thereby, according to the supporting substrates of the multi-layer wire substrate manufacture use of technical scheme 1, laminated metal lamellar body is a kind ofly to remove mechanically the peripheral part of top layer side metal level and the overall dimension of base side metal level is formed greatlyr than the overall dimension of top layer side metal level and the structure that obtains., even if therefore the structure that the peripheral part that laminated metal lamellar body is the removal top layer side metal levels such as such as etching of a kind of unfavorable use also can obtain, himself can not produce etching solution and enter the problems such as the interface between base side metal level and top layer side metal level.Therefore, substandard products generation rate is suppressed must be lower, and therefore the rate of finished products of the multi-layer wire substrate of manufacturing improves.In addition, in the situation that forming laminated metal lamellar body by machining, only depend on and cut off the operation of top layer side metal level, the operation of removing the peripheral part of the top layer side metal level that cuts off just can complete.Its result, compared with carrying out etching and form the situation of laminated metal lamellar body, reduce man-hour, therefore can reduce the manufacturing cost of multi-layer wire substrate, and the manufacture efficiency of multi-layer wire substrate improves.
In addition, above-mentioned multi-layer wire substrate is considered cost-effectivenes, processability, insulating properties, mechanical strength etc. and can suitably be selected.As multi-layer wire substrate, thereby use the multi-layer wire substrate with the structure that multiple resin insulating barriers and the alternately laminated multiple stratification of multiple conductor layer are formed.In addition, except this multi-layer wire substrate, for example, also allow to use to have the lamination multi-layer wire substrate of resin insulating barrier and the alternately laminated lamination layer forming of conductor layer in the one or two sides of core substrate.As long as so arrange, will be easy to realize the densification of multi-layer wire substrate.
The multiple resin insulating barriers that form multi-layer wire substrate are considered insulating properties, thermal endurance, moisture-proof etc. and can suitably select.As the preferred example of macromolecular material that is used to form each resin insulating barrier, can enumerate the thermoplastic resins such as the heat-curing resins such as epoxy resin, phenolic resins, polyurethane resin, silicone resin, polyimide resin, polycarbonate resin, allyl resin, polyacetal resin, acrylic resin etc.
The multiple conductor layers that form multi-layer wire substrate are mainly made up of copper, utilize so known gimmicks such as subraction, semi-additive process, full additive method to form.Specifically, for example apply the gimmick such as etching, electroless copper or electrolytic copper plating of Copper Foil.In addition, also can after utilize the gimmick such as sputter, CVD formation film, form conductor layer or form conductor layer by printing conductive paste etc. by carrying out etching.
And the supporting substrates of multi-layer wire substrate manufacture use comprises the supporting substrates main body with board main.As supporting substrates main body, both can use the resin plate being formed by the resin material having solidified completely, also can use the metallic plate being formed by metal material.In addition, as the resin material, the metal material that are used to form supporting substrates main body, as long as use low cost and relatively hard material.But in the case of stacked multiple resin insulating barriers are cut off together with supporting substrates main body with the lit-par-lit structure body that multiple conductor layers form, will hold scissile resin substrate is good as supporting substrates.
And supporting substrates comprises laminated metal lamellar body, this laminated metal lamellar body is disposed at board main, and by base side metal level and top layer side metal level are formed with the state close contact that can peel off.At this, the thickness of base side metal level and top layer side metal level is not particularly limited, but as long as the thickness of top layer side metal level is formed greatlyr than the thickness of base side metal level,, when from base side metal level overburden removing side metal level, top layer side metal level is just difficult to break.
In addition, can be also, supporting substrates main body comprises board main and the substrate back that is positioned at a side contrary with board main, and laminated metal lamellar body is disposed at respectively board main and substrate back.As long as so arrange, just can utilize a supporting substrates to manufacture two multi-layer wire substrates, therefore the manufacture efficiency of multi-layer wire substrate further improves.
As another technical scheme for addressing the above problem (technical scheme 2), a kind of manufacture method of multi-layer wire substrate is provided, its supporting substrates by the multi-layer wire substrate manufacture use described in technique scheme 1 is manufactured multi-layer wire substrate, it is characterized in that, the manufacture method of multi-layer wire substrate comprises following operation: laminated metal sheet arranges operation, and above-mentioned laminated metal lamellar body is set on aforesaid substrate first type surface; Periphery metal level removing step, removes the peripheral part of above-mentioned top layer side metal level mechanically, thereby makes the peripheral part of above-mentioned base side metal level and above-mentioned top layer side metal level be exposed to surface; Stacked operation, stacked above-mentioned multiple resin insulating barriers and above-mentioned multiple conductor layer, obtain the lit-par-lit structure body on the peripheral part of above-mentioned base side metal level and on the side metal level of above-mentioned top layer with the wiring laminated portion that should become above-mentioned multi-layer wire substrate; Removing step, after above-mentioned stacked operation, removes together with above-mentioned supporting substrates main body the periphery being positioned at than above-mentioned wiring laminated portion position in the outer part from above-mentioned lit-par-lit structure body; And separation circuit, the above-mentioned wiring laminated portion of interfacial separation and above-mentioned supporting substrates main body between above-mentioned base side metal level and above-mentioned top layer side metal level.
Thereby, according to the manufacture method of the multi-layer wire substrate of technical scheme 2, by adopting mechanical system to remove the peripheral part of top layer side metal level, form the overall dimension laminated metal lamellar body larger than the overall dimension of top layer side metal level of base side metal level in periphery metal level removing step.That is, even if the peripheral part of top layer side metal level is removed in such as etching of unfavorable use etc., also can obtain laminated metal lamellar body, therefore himself can not produce etching solution and enter the problems such as interface between base side metal level and top layer side metal level.Therefore, substandard products generation rate is suppressed must be lower, and therefore the rate of finished products of the multi-layer wire substrate of manufacturing improves.In addition, owing to carrying out machining in periphery metal level removing step, therefore the periphery metal level removing step that only depends on the operation of the peripheral part that carries out the top layer side metal level being cut off by operation and the removal of cut-out top layer side metal level to form, just can form laminated metal lamellar body.Its result, compared with carrying out etching and form the situation of laminated metal lamellar body, reduce man-hour, therefore can reduce the manufacturing cost of multi-layer wire substrate, and the manufacture efficiency of multi-layer wire substrate improves.
The manufacture method of multi-layer wire substrate is described below.
Arrange in operation at laminated metal sheet, laminated metal lamellar body is set in the board main of supporting substrates main body.
In ensuing periphery metal level removing step, remove mechanically the peripheral part of top layer side metal level, thereby make the peripheral part of base side metal level and top layer side metal level be exposed to surface.At this, as the method for peripheral part of mechanically removing top layer side metal level, can list the method for the surface of the method for the peripheral part that cuts off top layer side metal level, peripheral part to top layer side metal level grinding etc.As the method for peripheral part of cutting off top layer side metal level, there is cut-out processing, the perforation processing that has used hole punched device, the laser processing that has used laser aid etc. that utilize cutting tool to carry out.In addition, the method for grinding as the surface of the peripheral part to top layer side metal level, can enumerate sandblast, utilize grinding that sand paper carries out etc.
In addition, in periphery metal level removing step, also can be, in cutting off the peripheral part of top layer side metal level, position under the outer peripheral edges that are positioned at top layer side metal level on base side metal level is formed with the notch at the surface opening of base side metal level, makes the periphery edge basad side metal level lateral bend of top layer side metal level.As long as so arrange, the interface between base side metal level and top layer side metal level will be pressed in notch, therefore can prevent reliably that top layer side metal level from peeling off from base side metal level.Therefore, substandard products generation rate is lowlyer suppressed, and therefore the rate of finished products of the multi-layer wire substrate of manufacturing further improves.
And, in periphery metal level removing step, both notch can be formed as to the degree of depth of the degree that arrives supporting substrates main body, also notch can be formed as to the degree of depth of the degree of not blocking base side metal level.In the case of notch being formed as the degree of depth of the degree that arrives supporting substrates main body, interface between base side metal level and top layer side metal level is deeper pressed in notch, therefore can further prevent reliably that top layer side metal level from peeling off from base side metal level.On the other hand, in the case of notch being formed as the degree of depth of the degree of not blocking base side metal level, can prevent the strength decreased by the supporting substrates main body that the darker otch of supporting substrates main body incision is caused.And, as long as the degree of depth of notch is made as to the degree of not blocking substrate metal layer in advance, just can, by substrate metal layer as crystal seed layer, therefore can omit the formation operation of crystal seed layer.
In ensuing stacked operation, stacked multiple resin insulating barriers and multiple conductor layer, obtain the lit-par-lit structure body on the peripheral part of base side metal level and on the side metal level of top layer with the wiring laminated portion that should become multi-layer wire substrate.
In addition, can be, multi-layer wire substrate have core substrate yet, the via conductor that is formed at multiple resin insulating barriers in each layer of resin insulating barrier to same direction hole enlargement., multi-layer wire substrate can be also to form, also only utilize the centreless circuit board that connects each conductor layer to the via conductor of same direction hole enlargement using identical resin insulating barrier as main body.As long as so arrange, by omitting relatively thick core substrate, thereby the length of arrangement wire of wiring shortens, and therefore the transmission loss of high-frequency signal reduces, and can make semiconductor integrated circuit element move at high speed.
In removing step after stacked operation, the periphery being positioned at than the wiring laminated portion of main body position is in the outer part removed from lit-par-lit structure body together with supporting substrates.In ensuing separation circuit, the wiring laminated portion of interfacial separation and supporting substrates main body between base side metal level and top layer side metal level.Now, can obtain the multi-layer wire substrate of expectation.
Brief description of the drawings
Fig. 1 is the general profile chart that represents the schematic configuration of the semiconductor package body in present embodiment.
Fig. 2 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 3 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 4 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 5 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 6 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 7 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 8 is the key diagram that represents the manufacture method of multi-layer wire substrate.
Fig. 9 is the key diagram that represents the manufacture method of the multi-layer wire substrate in other execution modes.
Figure 10 is the key diagram that represents the manufacture method of multi-layer wire substrate of the prior art.
Figure 11 is the key diagram that represents the manufacture method of multi-layer wire substrate of the prior art.
Embodiment
Below, describe with reference to the accompanying drawings the execution mode that the present invention has been specialized in detail.
As shown in Figure 1, the semiconductor package body 10 of present embodiment is the BGA(BGA Package forming by multi-layer wire substrate 11 with as the IC chip 21 of semiconductor integrated circuit element).In addition, the form of semiconductor package body 10 is not merely defined in BGA, for example, can be also PGA(contact pin grid array packages), LGA(Background Grid array packages) etc.IC chip 21 is rectangular flat shapes of long 15.0mm × wide 15.0mm × thick 0.8mm, and the silicon that is 4.2ppm/ DEG C by thermal coefficient of expansion forms.
On the other hand, multi-layer wire substrate 11 does not have core substrate, and has wiring laminated portion 40, and this wiring laminated portion 40 is by by four layers of resin insulating barrier that are made up of epoxy resin 43,44,45,46 with the conductor layer 51 that is made up of copper is alternately laminated and multiple stratification forms.The wiring laminated portion 40 of present embodiment is the rectangular shape of overlooking of long 50.0mm × wide 50.0mm × thick 0.4mm.In the present embodiment, the thermal coefficient of expansion of resin insulating barrier 43～resin insulating barrier 46 is 10ppm/ DEG C～60ppm/ DEG C left and right (being specifically 20ppm/ DEG C of left and right).In addition, the thermal coefficient of expansion of resin insulating barrier 43～resin insulating barrier 46 refers to the mean value of the measured value between 30 DEG C～vitrification point (Tg).
As shown in Figure 1, on the first type surface 41 of wiring laminated portion 40, (on the surface of the resin insulating barrier 46 of the 4th layer) is array-like and disposes terminal pad 52.And, on the surface of terminal pad 52, be equipped with multiple solder bumps 54.Be connected with the terminal 22 of IC chip 21 at each solder bump 54 faces., IC chip 21 is equipped on first type surface 41 sides of wiring laminated portion 40.In addition, the region that is formed with each terminal pad 52 and each solder bump 54 is the IC chip carrying region 23 that can carry IC chip 21.
On the other hand, on the back side 42 of wiring laminated portion 40, (on the lower surface of the resin insulating barrier 43 of the 1st layer) is array-like and is equipped with pad 53 for BGA.In addition, the roughly entirety of the lower surface of resin insulating barrier 43 is covered by solder resist 47.Be formed with the peristome 48 that BGA pad 53 is exposed at the regulation position of solder resist 47.The multiple solder bumps 55 that are equipped with motherboard connection use on surface at each BGA with pad 53, wiring laminated portion 40 is arranged on not shown motherboard by means of each solder bump 55.
As shown in Figure 1, in each resin insulating barrier 43～resin insulating barrier 46, be respectively equipped with via 56 and via conductor 57.Each via 56 is formed as truncated conical shape, by each resin insulating barrier 43～resin insulating barrier 46 is applied and used the Drilling operation of YAG laser or carbon dioxide laser to form.Each via conductor 57 has the shape to same direction (below in Fig. 1 being) hole enlargement in each layer of resin insulating barrier 43～resin insulating barrier 46, and each conductor layer 51, terminal pad 52 and BGA are electrically connected mutually with pad 53.
The manufacture method of multi-layer wire substrate 11 then, is described.
First, prepare to have the supporting substrates (glass epoxy substrate etc.) of abundant intensity, laminated resin insulating barrier 43～resin insulating barrier 46 and conductor layer 51 on this supporting substrates and form wiring laminated portion 40.
In detail, first, by pasting prepreg 75 on the two sides at base material 74, thereby obtain the supporting substrates main body 71(being formed by base material 74 and prepreg 75 with reference to Fig. 2).In addition, prepreg 75 impregnated in glass fabric and forms by making not contain Packed resin (in the present embodiment, being the epoxy resin as heat-curing resin).In addition, supporting substrates main body 71 comprises board main 72 and the substrate back 73 that is positioned at a side contrary with board main 72.
Then, carry out laminated metal sheet operation is set, laminated metal lamellar body 81(is set in supporting substrates main body 71 with reference to Fig. 2).In addition, laminated metal lamellar body 81 is to make base side Copper Foil 82(base side metal level) and side Copper Foil 83(top layer, top layer side metal level) form with the state close contact that can peel off, adhesive linkage be provided with at the whole back side of base side Copper Foil 82 (face contacting with prepreg 75).In addition, the thickness of base side Copper Foil 82 is set as 3 μ m, and the thickness of top layer side Copper Foil 83 is set as 18 μ m, and therefore the thickness of the Thickness Ratio base side Copper Foil 82 of top layer side Copper Foil 83 is large.
In ensuing periphery metal level removing step, remove mechanically the peripheral part of top layer side Copper Foil 83, thereby make the peripheral part of base side Copper Foil 82 and top layer side Copper Foil 83 be exposed to surface (with reference to Fig. 3, Fig. 4).Specifically, in using cutting tool to cut off the peripheral part of top layer side Copper Foil 83, the position under the outer peripheral edges 84 that are positioned at top layer side Copper Foil 83 on base side Copper Foil 82 is formed on the notch 86(of surface 85 openings of base side Copper Foil 82 with reference to Fig. 4).Accompany therewith, basad side Copper Foil 82 lateral bends in periphery edge 87 of top layer side Copper Foil 83, and interface between base side Copper Foil 82 and top layer side Copper Foil B3 is pressed in notch 86.In addition, because the notch 86 of present embodiment is formed as the degree of depth of the degree of not blocking base side Copper Foil 82, (m), therefore notch 86 can not arrive supporting substrates main body 71 to 2 μ.Afterwards, as long as remove the peripheral part of top layer side Copper Foil 83, the peripheral part of base side Copper Foil 82 and top layer side Copper Foil B3 will be exposed to surface.Now, the overall dimension of base side Copper Foil 82 is larger than the overall dimension of top layer side Copper Foil 83.
In ensuing stacked operation, the insulating resin base material of laminates shape on two stacked sheet metal bodies 81, after use vacuum compressing hot press (diagram is omitted) carries out pressurized, heated under vacuum, it is solidified, thereby the peripheral part of formation covering base side Copper Foil 82 and the resin insulating barrier 46(of the 4th layer of top layer side Copper Foil 83 are with reference to Fig. 5).Then, by implementing laser processing, form via 56 in the position of the regulation of resin insulating barrier 46, then remove the de-smear (Japanese: デ ス ミ ア) of the glue slag (Japanese: ス ミ ア) in each via 56 and process.
Then, carry out electroless copper and electrolytic copper plating according to known gimmick in the past, thereby at the interior formation via of each via 56 conductor 57.And then, utilize known gimmick (for example semi-additive process) in the past to carry out etching, thereby pattern form conductor layer 51 on resin insulating barrier 46.
In addition, the resin insulating barrier 43～resin insulating barrier 45 of the 1st layer～the 3rd layer and conductor layer 51 also utilize the gimmick identical with conductor layer 51 with the resin insulating barrier 46 of above-mentioned the 4th layer to form, and are layered on resin insulating barrier 46.Then, by being coated with photonasty epoxy resin on the resin insulating barrier 43 being formed with BGA pad 53 and it being solidified, thereby form solder resist 47.Then, under the state of mask that has configured regulation, expose and develop, on solder resist 47, pattern forms peristome 48.By above manufacturing process, be formed on the both sides of supporting substrates 70 respectively stacked the lit-par-lit structure body 90(of laminated metal lamellar body 81, resin insulating barrier 43～resin insulating barrier 46 and conductor layer 51 with reference to Fig. 6).In addition, as shown in Figure 6, in lit-par-lit structure body 90, being positioned at the region (being specifically positioned on top layer side Copper Foil 83) on laminated metal lamellar body 81 becomes wiring laminated portion 40.
In removing step after stacked operation, utilize cutter sweep (diagram is omitted) to cut off this lit-par-lit structure body 90, the periphery 91 being positioned at than wiring laminated portion 40 position is in the outer part removed from lit-par-lit structure body 90 together with supporting substrates main body 71.Now, the boundary part (with reference to the single-point line in Fig. 6) between wiring laminated portion 40 and periphery 91, cuts off (with reference to Fig. 7) by wiring laminated portion 40 together with supporting substrates 70.By this cut-out, the outer edge of the top layer side Copper Foil 83 being sealed by resin insulating barrier 46 becomes the state of exposure.
In ensuing separation circuit, lit-par-lit structure body 90 is separated into wiring laminated portion 40 and supporting substrates 70, base side Copper Foil 82 and top layer side Copper Foil 83 are exposed.Specifically, laminated metal lamellar body 81 is peeled off at the interface between base side Copper Foil 82 and top layer side Copper Foil 83, from supporting substrates 70 wires apart laminated section 40(with reference to Fig. 8).
Then, on the resin insulating barrier 46 of the 4th layer, form terminal pad 52.Specifically, by being positioned at the wiring laminated 40(of portion resin insulating barrier 46) first type surface 41 on top layer side Copper Foil 83 pattern that carries out being implemented by etching form, thereby in the region on the first type surface 41 of resin insulating barrier 46, form terminal pad 52.
And then, on the multiple terminal pads 52 on the resin insulating barrier 46 that is formed at top layer, form the solder bump 54 that IC chip 21 connects use.Specifically, after the not shown solder ball mounting device of use has configured solder ball on each terminal pad 52, solder ball is heated to the temperature of regulation and carries out Reflow Soldering, thereby form solder bump 54 on each terminal pad 52.Similarly, on the multiple BGA pad 53 being formed on resin insulating barrier 43, form solder bump 55.
Afterwards, in the IC of wiring laminated portion 40 chip carrying region 23, load IC chip 21.Now, the terminal 22 of IC chip 21 sides and the solder bump 54 of wiring laminated portion 40 sides are carried out to contraposition.Then, heat and each solder bump 54 is carried out to Reflow Soldering, thereby terminal 22 is engaged with solder bump 54, IC chip 21 is equipped on to wiring laminated portion 40.
Thereby, according to present embodiment, can obtain following effect.
(1) according to the manufacture method of the multi-layer wire substrate 11 of present embodiment, by mechanically remove the peripheral part of top layer side Copper Foil 83 in periphery metal level removing step, thus the overall dimension laminated metal lamellar body 81 larger than the overall dimension of top layer side Copper Foil 83 of formation base side Copper Foil 82.That is, even if the peripheral part of top layer side Copper Foil 83 is removed in such as etching of unfavorable use etc., also can obtain laminated metal lamellar body 81, therefore himself can not produce etching solution and enter the problems such as interface between base side Copper Foil 82 and top layer side Copper Foil 83.Therefore, substandard products generation rate is suppressed to lower, and the rate of finished products of the multi-layer wire substrate 11 of therefore manufacturing improves.
In addition, owing to carrying out machining in periphery metal level removing step, therefore only depend on and carry out, by cutting off the operation of top layer side Copper Foil 83 and removing the periphery metal level removing step that the operation of the peripheral part of the top layer side Copper Foil 83 after cutting off forms, just can forming laminated metal lamellar body 81.Its result, compared with carrying out etching and form the situation of laminated metal lamellar body, reduce man-hour, therefore can reduce the manufacturing cost of multi-layer wire substrate 11, and the manufacture efficiency of multi-layer wire substrate 11 improves.
(2) in the periphery metal level removing step of present embodiment, in cutting off the peripheral part of top layer side Copper Foil 83, position under the outer peripheral edges 84 that are positioned at top layer side Copper Foil 83 on base side Copper Foil 82 forms notch 86, makes basad side Copper Foil 82 lateral bends in periphery edge 87 of top layer side Copper Foil 83.Its result, the interface between base side Copper Foil 82 and top layer side Copper Foil 83 is pressed in notch 86, therefore can prevent reliably that top layer side Copper Foil 83 from peeling off from base side Copper Foil 82.Therefore, substandard products generation rate is lowlyer suppressed, and the rate of finished products of the multi-layer wire substrate 11 of manufacturing further improves.
(3) in the present embodiment, the external diameter of the Copper Foil of downside (base side Copper Foil 82) is larger than the external diameter of the Copper Foil of upside (top layer side Copper Foil 83), and the Copper Foil of upside is configured on supporting substrates 70 in the mode of peripheral part of the Copper Foil that do not exceed downside.In this case, even press insulating resin base material from upside, also can guarantee fully the flatness of the Copper Foil of upside.Thereby, form the surperficial top layer side Copper Foil 83 that is exposed to wiring laminated portion 40 by pattern, can form the terminal pad 52 that flatness is higher, can guarantee fully the connection reliability of terminal pad 52.
(4) in the present embodiment, form the top layer side Copper Foil 83 utilizing for wires apart laminated section 40 and supporting substrates 70 by pattern, thereby be formed with terminal pad 52.As long as so arrange,, compared with utilizing the situation of other Copper Foils or copper facing formation terminal pad 52, can suppress the manufacturing cost of multi-layer wire substrate 11.
In addition, also can as below, change present embodiment.
In the periphery metal level removing step of above-mentioned execution mode, formed notch 86 by the peripheral part that utilizes cutting tool to cut off top layer side Copper Foil 83, but the formation method of notch is not limited thereto, and also can form notch with additive method.For example, also can be by forming notch 186(with reference to Fig. 9 with the peripheral part of laser cutting top layer side Copper Foil 183).And, as long as notch 186 is formed as to the degree of depth of the degree that arrives supporting substrates main body 171, the outer peripheral edges 184 of top layer side Copper Foil 183 and the outer peripheral edges 185 of base side Copper Foil 182 be just connected under the effect of the heat of laser (with reference to the region Al of Fig. 9).Its result, prevents that top layer side Copper Foil 183 from peeling off from base side Copper Foil 182 reliably, and therefore substandard products generation rate is lowlyer suppressed, and the rate of finished products of the multi-layer wire substrate 11 of manufacturing further improves.
In the periphery metal level removing step of above-mentioned execution mode, notch 86 is formed as to the degree of depth of the degree of not blocking base side Copper Foil 82, but also can be formed as the degree of depth of the degree that arrives supporting substrates main body 71.In this case, as long as utilizing cutting tool to cut off the peripheral part of top layer side Copper Foil 83, interface between base side Copper Foil 82 and top layer side Copper Foil 83 deeper will be pressed in notch 86, therefore can further prevent reliably that top layer side Copper Foil 83 from peeling off from base side Copper Foil 82.
In the above-described embodiment, formed wiring laminated portion 40 in the both sides of supporting substrates 70, but also can be only in the wiring laminated portion 40 of one-sided formation of supporting substrates 70.
In the above-described embodiment, form top layer side Copper Foil 83 by pattern and formed terminal pad 52, but be not limited thereto.For example, in stacked operation, on top layer side Copper Foil 83, pattern forms terminal pad 52 in advance.Then,, after separation circuit, utilize etching to remove to be completely exposed to the top layer side Copper Foil 83 of the first type surface 41 of wiring laminated portion 40.Like this, also can produce the multi-layer wire substrate that there is no core substrate.
In the above-described embodiment, conductor layer 51, terminal pad 52 and BGA utilize along with going and the via conductor 57 of hole enlargement interconnects towards the back side 42 sides from first type surface 41 sides with pad 53, but are not limited thereto.As long as via conductor is the shape to same direction hole enlargement, also can utilize along with going and the via conductor of hole enlargement interconnects conductor layer 51, terminal pad 52 and BGA pad 53 towards first type surface 41 sides from the back side 42 sides.
The overall dimension of the base side Copper Foil 82 of the laminated metal lamellar body 81 of above-mentioned execution mode is set greatlyr than the overall dimension of top layer side Copper Foil 83.But, also can change to the laminated metal lamellar body that the overall dimension of base side Copper Foil 82 and the overall dimension of top layer side Copper Foil 83 are equal to each other.
Then, below enumerate the technological thought of grasping according to above-mentioned execution mode.
(1) in technique scheme 1, a kind of supporting substrates of multi-layer wire substrate manufacture use is provided, it is characterized in that, position under the outer peripheral edges that are positioned at above-mentioned top layer side metal level on above-mentioned base side metal level is formed with the notch at the surface opening of above-mentioned base side metal level, and the degree of depth of above-mentioned notch is set as arriving the degree of above-mentioned supporting substrates main body.
(2) a kind of supporting substrates of multi-layer wire substrate manufacture use, it uses in the time that thereby manufacture has the multi-layer wire substrate of the structure that multiple resin insulating barriers and the alternately laminated multiple stratification of multiple conductor layer are formed, it is characterized in that, this supporting substrates comprises: supporting substrates main body, and it has board main; And laminated metal lamellar body, it is disposed at aforesaid substrate first type surface, and this laminated metal lamellar body is by making base side metal level and top layer side metal level form with the state close contact that can peel off; Position under the outer peripheral edges that are positioned at above-mentioned top layer side metal level on above-mentioned base side metal level is formed with the notch at the surface opening of above-mentioned base side metal level.
description of reference numerals
11 ... multi-layer wire substrate; 40 ... wiring laminated portion; 43,44,45,46 ... resin insulating barrier; 51 ... conductor layer; 57 ... via conductor; 70 ... supporting substrates; 71,171 ... supporting substrates main body; 72 ... board main; 73 ... substrate back; 81 ... laminated metal lamellar body; 82,182 ... as the base side Copper Foil of base side metal level; 83,183 ... as the top layer side Copper Foil of top layer side metal level; 84,184 ... the outer peripheral edges of top layer side metal level; 85 ... the surface of base side metal level; 86,186 ... notch; 87 ... the periphery edge of top layer side metal level; 90 ... lit-par-lit structure body; 91 ... periphery.
Claims (11)
1. the supporting substrates of a multi-layer wire substrate manufacture use, thereby it has multiple resin insulating barriers (43～46) and multiple conductor layers (51) in manufacture uses when the multi-layer wire substrate (11) of the structure that alternately laminated multiple stratification forms, it is characterized in that, this supporting substrates (70) comprising:
Supporting substrates main body (71,171), it has board main (72); And
Laminated metal lamellar body (81), it is disposed at aforesaid substrate first type surface (72), and this laminated metal lamellar body (81) is by making base side metal level (82,182) and top layer side metal level (83,183) form with the state close contact that can peel off;
The overall dimension of above-mentioned base side metal level (82,182) is set greatlyr than the overall dimension of above-mentioned top layer side metal level (83,183).
2. the supporting substrates of multi-layer wire substrate manufacture use according to claim 1, is characterized in that,
The outer peripheral edges (84 that are positioned at above-mentioned top layer side metal level (83,183) on above-mentioned base side metal level (82,182), 184) position under is formed with at above-mentioned base side metal level (82,182) notch (86,186) of surface (85) opening
The periphery edge (87) of above-mentioned top layer side metal level (83,183) is to that curving of above-mentioned base side metal level (82,182).
3. the supporting substrates of multi-layer wire substrate manufacture use according to claim 1 and 2, is characterized in that,
Above-mentioned supporting substrates main body (71,171) comprises aforesaid substrate first type surface (72) and is positioned at the substrate back (73) of a side contrary with aforesaid substrate first type surface (72),
Above-mentioned laminated metal lamellar body (81) is disposed at respectively aforesaid substrate first type surface (72) and the aforesaid substrate back side (73).
4. the supporting substrates of multi-layer wire substrate manufacture use according to claim 2, is characterized in that,
Above-mentioned notch (86) does not block above-mentioned base side metal level (82).
5. according to the supporting substrates of the multi-layer wire substrate manufacture use described in any one in claim 1,2 and 4, it is characterized in that,
The thickness of above-mentioned top layer side metal level (83,183) is greater than the thickness of above-mentioned base side metal level (82,182).
6. the supporting substrates of multi-layer wire substrate manufacture use according to claim 3, is characterized in that,
The thickness of above-mentioned top layer side metal level (83,183) is greater than the thickness of above-mentioned base side metal level (82,182).
7. the manufacture method of a multi-layer wire substrate, its right to use requires the supporting substrates (70) of the manufacture of the multi-layer wire substrate (11) described in any one use in 1 to 6 to manufacture multi-layer wire substrate (11), it is characterized in that, the manufacture method of this multi-layer wire substrate comprises following operation:
Laminated metal sheet arranges operation, and above-mentioned laminated metal lamellar body (81) is set on aforesaid substrate first type surface (72);
Periphery metal level removing step, removes the peripheral part of above-mentioned top layer side metal level (83,183) mechanically, thereby makes the peripheral part of above-mentioned base side metal level (82,182) and above-mentioned top layer side metal level (83,183) be exposed to surface;
Stacked operation, stacked above-mentioned multiple resin insulating barriers (43～46) and above-mentioned multiple conductor layer (51), obtain at above-mentioned base side metal level (82,182) on peripheral part and on above-mentioned top layer side metal level (83,183), have and should become the lit-par-lit structure body of the wiring laminated portion of above-mentioned multi-layer wire substrate (11) (40) (90);
Removing step, after above-mentioned stacked operation, will be positioned at than the periphery (91) of above-mentioned wiring laminated portion (40) position in the outer part and remove from above-mentioned lit-par-lit structure body (90) together together with above-mentioned supporting substrates main body (71,171); And
Separation circuit, the above-mentioned wiring laminated portion of interfacial separation (40) between above-mentioned base side metal level (82,182) and above-mentioned top layer side metal level (83,183) and above-mentioned supporting substrates main body (71,171).
8. the manufacture method of multi-layer wire substrate according to claim 7, is characterized in that,
In above-mentioned periphery metal level removing step, cutting off above-mentioned top layer side metal level (83,183) when peripheral part, at above-mentioned base side metal level (82,182) on, be positioned at above-mentioned top layer side metal level (83,183) outer peripheral edges (84,184) position under is formed with at above-mentioned base side metal level (82,182) notch (86 of surface (85) opening, 186), make the periphery edge (87) of above-mentioned top layer side metal level (83,183) to that curving of above-mentioned base side metal level (82,182).
9. the manufacture method of multi-layer wire substrate according to claim 8, is characterized in that,
In above-mentioned periphery metal level removing step, above-mentioned notch (186) is formed as to the degree of depth of the degree that arrives above-mentioned supporting substrates main body (171).
10. the manufacture method of multi-layer wire substrate according to claim 8, is characterized in that,
In above-mentioned periphery metal level removing step, above-mentioned notch (86) is formed as to the degree of depth of the degree of not blocking above-mentioned base side metal level (82).
11. according to the manufacture method of the multi-layer wire substrate described in any one in claim 7 to 10, it is characterized in that,
Above-mentioned multi-layer wire substrate (11) does not have core substrate, the via conductor (57) that is formed at above-mentioned multiple resin insulating barrier (43～46) in each layer of above-mentioned resin insulating barrier (43～46) to same direction hole enlargement.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013-025100 | 2013-02-13 | ||
| JP2013025100A JP2014154794A (en) | 2013-02-13 | 2013-02-13 | Support substrate for manufacturing multilayer wiring board, method of manufacturing multilayer wiring board |
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| Publication Number | Publication Date |
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| CN103987212A true CN103987212A (en) | 2014-08-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310488460.9A Pending CN103987212A (en) | 2013-02-13 | 2013-10-17 | Supporting substrate for manufacturing multilayer wiring substrate and multilayer wiring substrate manufacturing method |
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| Country | Link |
|---|---|
| JP (1) | JP2014154794A (en) |
| KR (1) | KR20140102144A (en) |
| CN (1) | CN103987212A (en) |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009032918A (en) * | 2007-07-27 | 2009-02-12 | Shinko Electric Ind Co Ltd | Wiring substrate, manufacturing method thereof, electronic component device, and manufacturing method thereof |
| US20110056614A1 (en) * | 2009-09-10 | 2011-03-10 | Samsung Electro-Mechanics Co., Ltd. | Manufacturing method of circuit board |
| US20120102732A1 (en) * | 2010-10-27 | 2012-05-03 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multilayer wiring substrate |
| CN102448250A (en) * | 2010-10-04 | 2012-05-09 | 三星电机株式会社 | Method of manufacturing printed circuit board |
-
2013
- 2013-02-13 JP JP2013025100A patent/JP2014154794A/en active Pending
- 2013-10-17 CN CN201310488460.9A patent/CN103987212A/en active Pending
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- 2014-02-11 KR KR1020140015265A patent/KR20140102144A/en active IP Right Grant
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009032918A (en) * | 2007-07-27 | 2009-02-12 | Shinko Electric Ind Co Ltd | Wiring substrate, manufacturing method thereof, electronic component device, and manufacturing method thereof |
| US20110056614A1 (en) * | 2009-09-10 | 2011-03-10 | Samsung Electro-Mechanics Co., Ltd. | Manufacturing method of circuit board |
| CN102448250A (en) * | 2010-10-04 | 2012-05-09 | 三星电机株式会社 | Method of manufacturing printed circuit board |
| US20120102732A1 (en) * | 2010-10-27 | 2012-05-03 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multilayer wiring substrate |
Also Published As
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| TWI507109B (en) | 2015-11-01 |
| JP2014154794A (en) | 2014-08-25 |
| TW201438538A (en) | 2014-10-01 |
| KR20140102144A (en) | 2014-08-21 |
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