CN103984586B - Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system - Google Patents
Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system Download PDFInfo
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Abstract
The invention discloses an interface drive method for an EMIF (external memory interface) and an FPGA (field programmable gate array) under an embedded type Linux system, belongs to the field of data transmission and solves a problem that existing EMIF and FPGA interfaces of a DSP (data signal processor) under the Linux system cannot realize image data transmission. The drive interface method comprises the following steps: firstly, realizing loading of an EMIF drive module on a drive equipment loading function and unloading on an unloading function; secondly, by virtue of the EMIF drive module, carrying out writing operation onto FIFO (first in, first out) in the FPGA in a sending device by an EMIF end port of the DSP in the sending device; thirdly, performing an interrupt processing process and awaking a reading process after the DSP in the receiving device receives an interrupt signal; and finally, by virtue of the EMIF drive module, carrying out reading operation onto FIFO in the FPGA in a receiving device by the EMIF port of the DSP in the receiving device. The interface drive method disclosed by the invention is used for realizing data communication between the EMIF port and the FPGA interface.
Description
Technical field
The invention belongs to field of data transmission.
Background technology
With the development of growth in the living standard and scientific and technological level, the requirement more and more higher to image procossing for the people, such as regard
Frequency meeting, video monitoring, video calling etc..But, before Leonardo da Vinci (Davinci) technology occurs, for different needs,
Developer needs to be grasped the exploitation knowledge of different picture processing chips and software, this considerably increases the difficulty of new product development
And the construction cycle.For above-mentioned situation, on the basis of DSP technology, in conjunction with ARM, image codec standards, TI programs for TI company
Specification etc. proposes Davinci technology framework.Davinci Technical Architecture greatly reduces the complexity of image procossing, shortens product
The R&D cycle of product, and can also enhance product performance.
Improve perfect with developing instrument with DSP processing speed, its range of application is more and more extensive.Due in DSP
Portion RAM is limited, so the collection of mass data to be realized and process, needs the RAM of DSP is extended.
In addition, during radio communication, the often serial data of transmission, but due to DSP hardware principle itself
With the feature instructing so that DSP can not be seamlessly connected with Wireless Telecom Equipment.
It is attached with FPGA by the EMIF interface of DSP, so that DSP obtains larger external memory space.With
When, because FPGA has the characteristics that flexible in programming so that DSP can be seamlessly connected with numerous module devices, so
Just significantly expand the range of application of DSP.
Content of the invention
The present invention is cannot to realize picture number in order to solve the EMIF of existing DSP under linux system with FPGA interface
According to the problem of transmission, the invention provides a kind of interface driver method of the EMIF under embedded Linux system and FPGA.
The interface driver method of the EMIF under embedded Linux system and FPGA, it is based on following dispensing devices and reception
Device is realized, and the data signal output of dispensing device is connected with the data signal input of reception device,
Dispensing device includes DSP and FPGA, wherein, described DSP write enable control signal outfan with
The write enable signal input of FPGA connects, and the write clock signal outfan of DSP is connected with the write clock signal input of FPGA,
The data signal output of DSP is connected with the data signal input of FPGA, the data signal output of FPGA in dispensing device
Data signal output as dispensing device;
Reception device includes DSP and FPGA, wherein, the reading of described FPGA enable control signal input with
The reading of DSP enables signal output part and connects, and the read clock signal input of FPGA is connected with the read clock signal outfan of DSP,
The interrupt trigger signal outfan of FPGA is connected with the interrupt signal input of DSP, and the data signal output of FPGA is with DSP's
Data signal input connects, and in reception device, the data signal input of FPGA inputs as the data signal of reception device
End;
The DSP in DSP and reception device in dispensing device is the DSP containing EMIF port,
The DSP in DSP and reception device in dispensing device all embedded in (SuSE) Linux OS and EMIF drive module,
Under a linux operating system, EMIF drive module is used for realizing the communication of DSP and FPGA,
Being embedded in the realization of the EMIF drive module within the DSP in dispensing device to the method for FPGA interface driving is,
Step 1:Realize EMIF drive module and function is unloaded to the loading of driving equipment loading function and this driving equipment
Unloading,
Step 2:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, by FIFO's
Write operation is mapped as the write operation to described memory address, and the EMIF port realizing DSP in dispensing device is to dispensing device
In FPGA in FIFO carry out write operation,
Step 3:After DSP in reception device receives interrupt trigger signal, execute interrupt handling program, make reception device
In the FIFO of FPGA from reception device for the EMIF port of DSP in read the byte specifying number, and store Linux behaviour
Make in the buffer area of system kernel, wake up reading process;
Step 4:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, by FIFO's
Read operation is mapped as the read operation to described memory address, and the EMIF port realizing DSP in reception device is to reception device
In FPGA in FIFO carry out read operation, that is, complete the data communication between EMIF port and the interface of FPGA.
Described EMIF drive module of realizing unloads function to the loading of driving equipment loading function and this driving equipment
In unloading, EMIF drive module to the loading procedure of driving equipment loading function is:
During EMIF drive module is driven to driving equipment, first, device number is applied for, and will
EMIF drive module is registered in (SuSE) Linux OS, and (SuSE) Linux OS determines the corresponding EMIF of this equipment by device number
Drive module, completes the loading to driving equipment loading function for the EMIF drive module,
EMIF drive module to driving equipment unload function uninstall process be:
Device number is discharged, and the internal memory shared by corresponding for driving equipment EMIF drive module is discharged,
And return I/O resource to system, complete the unloading that EMIF drive module unloads function to driving equipment.
The EMIF port of the described DSP realizing in dispensing device carries out write operation to FIFO in the FPGA in dispensing device
Detailed process be,
The FPGA that will be copied in DSP from dispensing device for the data in dispensing device by write operation write () function
FIFO in.
The EMIF port of the described DSP realizing in reception device carries out read operation to FIFO in the FPGA in reception device
Detailed process be,
By read operation read () function by the data duplication in the kernel cache area of DSP in reception device to user's space.
After DSP in described reception device receives interrupt trigger signal, the detailed process of execution interrupt handling program
For,
Step 4-1:Removing interrupt identification, execution step 4-2,
Step 4-2:Using I/O operation function by the data duplication of FIFO in the FPGA of reception device to reception device
The buffer area of the kernel spacing of DSP, execution step 4-3,
Step 4-3:Judge whether the buffer area of kernel spacing expires half, result is yes, execution step 4-4, and result is no,
Execution step 4-5,
Step 4-4:Wake up the reading process of the user's space blocking, execution step 4-5;
Step 4-5:Interrupt returning.
Described by read operation read () function by the data duplication in the kernel cache area of DSP in reception device to user
The detailed process in space is:
Step 5-1:Whether the kernel cache area judging DSP in reception device is empty, and result be yes, execution step 5-2, ties
Fruit is no, execution step 5-3,
Step 5-2:Reading process dormancy, until buffer area is not space-time, execution step 5-3,
Step 5-3:Wake-up reading process, execution step 5-4,
Step 5-4:By read operation read () function by the data duplication in the kernel cache area of DSP in reception device to use
Family space, execution step 5-5,
Step 5-5:Release semaphore.
Described will be copied in dispensing device in DSP from dispensing device for the data by write operation write () function
The FIFO of FPGA in detailed process be:
Step 3-1:After the kernel spacing application buffer area of DSP in dispensing device, execution step 3-2,
Step 3-2:By the buffer area of the data duplication of user's space to kernel spacing, execution step 3-3,
Step 3-3:By write operation write () function, kernel spacing buffer area content is copied in dispensing device
In the FIFO of FPGA, execution step 3-4;
Step 3-4:Release semaphore.
The DSP in DSP and reception device in described dispensing device all chips using model TMS320DM365 are real
Existing.In whole system, 3 test points A, B, C are set, are tested, test point A, B, C position in systems is as shown in Figure 4.
In test process, first in dispensing device, TMS320DM365 sends data to FPGA in this device, then sends
In device, FPGA sends the data to FPGA in reception device, and in last reception device, FPGA sends the data to reception device again
Middle TMS320DM365.The FPGA waveform of wherein tri- test points of A, B and C respectively as shown in Fig. 6,7 and 8, by comparing
The data of TMS320DM365 transmission and reception is it was demonstrated that the Interface design between TMS320DM365 and FPGA is correct.
The beneficial effect that the present invention brings is it is achieved that the EMIF of DSP under linux system realizes image with FPGA interface
Data transfer.
Brief description
Fig. 1 is the principle schematic of the dispensing device described in specific embodiment one and reception device;
Fig. 2 is in specific embodiment six, by read operation read () function by the kernel cache area of DSP in reception device
Data duplication to user's space flow chart;
Fig. 3 is in specific embodiment seven, by write operation write () function by DSP from dispensing device for the data
Copy to the flow chart in the FIFO of the FPGA in dispensing device;
Fig. 4 is in specific embodiment eight, and test point A, B, the C position relationship in dispensing device and reception device is illustrated
Figure;
Fig. 5 is in specific embodiment five, after the DSP in described reception device receives interrupt trigger signal, execution
The flow chart of interrupt handling program;
Fig. 6 is the waveform diagram of test point A;
Fig. 7 is the waveform diagram of test point B;
Fig. 8 is the waveform diagram of test point C.
Specific embodiment
Specific embodiment one:Referring to Fig. 1, present embodiment is described, the embedded Linux system described in present embodiment
Under EMIF and FPGA interface driver method, it is realized based on following dispensing devices and reception device, the number of dispensing device
It is connected with the data signal input of reception device according to signal output part,
Dispensing device includes DSP and FPGA, wherein, described DSP write enable control signal outfan with
The write enable signal input of FPGA connects, and the write clock signal outfan of DSP is connected with the write clock signal input of FPGA,
The data signal output of DSP is connected with the data signal input of FPGA, the data signal output of FPGA in dispensing device
Data signal output as dispensing device;
Reception device includes DSP and FPGA, wherein, the reading of described FPGA enable control signal input with
The reading of DSP enables signal output part and connects, and the read clock signal input of FPGA is connected with the read clock signal outfan of DSP,
The interrupt trigger signal outfan of FPGA is connected with the interrupt signal input of DSP, and the data signal output of FPGA is with DSP's
Data signal input connects, and in reception device, the data signal input of FPGA inputs as the data signal of reception device
End;
The DSP in DSP and reception device in dispensing device is the DSP containing EMIF port,
The DSP in DSP and reception device in dispensing device all embedded in (SuSE) Linux OS and EMIF drive module,
Under a linux operating system, EMIF drive module is used for realizing the communication of DSP and FPGA,
Being embedded in the realization of the EMIF drive module within the DSP in dispensing device to the method for FPGA interface driving is,
Step 1:Realize EMIF drive module and function is unloaded to the loading of driving equipment loading function and this driving equipment
Unloading,
Step 2:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, by FIFO's
Write operation is mapped as the write operation to described memory address, and the EMIF port realizing DSP in dispensing device is to dispensing device
In FPGA in FIFO carry out write operation,
Step 3:After DSP in reception device receives interrupt trigger signal, execute interrupt handling program, make reception device
In the FIFO of FPGA from reception device for the EMIF port of DSP in read the byte specifying number, and store Linux behaviour
Make in the buffer area of system kernel, wake up reading process;
Step 4:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, by FIFO's
Read operation is mapped as the read operation to described memory address, and the EMIF port realizing DSP in reception device is to reception device
In FPGA in FIFO carry out read operation, that is, complete the data communication between EMIF port and the interface of FPGA.
Specific embodiment two:Under present embodiment and the embedded Linux system described in specific embodiment one
The difference of the interface driver method of EMIF and FPGA is, described realizes EMIF drive module to driving equipment loading function
Load and this driving equipment unload in the unloading of function,
EMIF drive module to the loading procedure of driving equipment loading function is:
During EMIF drive module is driven to driving equipment, first, device number is applied for, and will
EMIF drive module is registered in (SuSE) Linux OS, and (SuSE) Linux OS determines the corresponding EMIF of this equipment by device number
Drive module, completes the loading to driving equipment loading function for the EMIF drive module,
EMIF drive module to driving equipment unload function uninstall process be:
Device number is discharged, and the internal memory shared by corresponding for driving equipment EMIF drive module is discharged,
And return I/O resource to system, complete the unloading that EMIF drive module unloads function to driving equipment.Specific embodiment three:
The interface driver side of the EMIF under present embodiment and the embedded Linux system described in specific embodiment one or two and FPGA
The difference of method is, the EMIF port of the described DSP realizing in dispensing device is carried out to FIFO in the FPGA in dispensing device
The detailed process of write operation is,
The FPGA that will be copied in DSP from dispensing device for the data in dispensing device by write operation write () function
FIFO in.
Specific embodiment four:Under present embodiment and the embedded Linux system described in specific embodiment three
The difference of the interface driver method of EMIF and FPGA is, the EMIF port of the described DSP realizing in reception device is to reception
The detailed process that in FPGA in device, FIFO carries out read operation is,
By read operation read () function by the data duplication in the kernel cache area of DSP in reception device to user's space.
Specific embodiment five:Referring to Fig. 5 present embodiment is described, present embodiment and specific embodiment one, two or
The difference of the interface driver method of the EMIF under the embedded Linux system and FPGA described in four is, described reception device
In DSP receive interrupt trigger signal after, execution interrupt handling program detailed process be,
Step 4-1:Removing interrupt identification, execution step 4-2,
Step 4-2:Using I/O operation function by the data duplication of FIFO in the FPGA of reception device to reception device
The buffer area of the kernel spacing of DSP, execution step 4-3,
Step 4-3:Judge whether the buffer area of kernel spacing expires half, result is yes, execution step 4-4, and result is no,
Execution step 4-5,
Step 4-4:Wake up the reading process of the user's space blocking, execution step 4-5;
Step 4-5:Interrupt returning.
Specific embodiment six:Illustrate described in present embodiment, present embodiment and specific embodiment four referring to Fig. 2
The difference of the interface driver method of the EMIF under embedded Linux system and FPGA is, described by read operation read ()
The detailed process of data duplication to the user's space in the kernel cache area of DSP in reception device is by function:
Step 5-1:Whether the kernel cache area judging DSP in reception device is empty, and result be yes, execution step 5-2, ties
Fruit is no, execution step 5-3,
Step 5-2:Reading process dormancy, until buffer area is not space-time, execution step 5-3,
Step 5-3:Wake-up reading process, execution step 5-4,
Step 5-4:By read operation read () function by the data duplication in the kernel cache area of DSP in reception device to use
Family space, execution step 5-5,
Step 5-5:Release semaphore.
Specific embodiment seven:Illustrate described in present embodiment, present embodiment and specific embodiment three referring to Fig. 3
The difference of the interface driver method of the EMIF under embedded Linux system and FPGA is, described by write operation write ()
Function by copying to the detailed process in the FIFO of the FPGA in dispensing device in DSP from dispensing device for the data is:
Step 3-1:After the kernel spacing application buffer area of DSP in dispensing device, execution step 3-2,
Step 3-2:By the buffer area of the data duplication of user's space to kernel spacing, execution step 3-3,
Step 3-3:By write operation write () function, kernel spacing buffer area content is copied in dispensing device
In the FIFO of FPGA, execution step 3-4;
Step 3-4:Release semaphore.
Specific embodiment eight:Present embodiment with embedded described in specific embodiment one, two, four, six or seven
The difference of the interface driver method of the EMIF under linux system and FPGA is, the DSP in described dispensing device and reception fill
DSP in putting all is realized using the chip of model TMS320DM365.
In present embodiment, during the hardware of the TMS320DM365 and FPGA of dispensing device is connected,It is
The chip selection signal of TMS320DM365 output, as in FPGA FIFO write enable, and Low level effective;EM_D is
The bidirectional data line of TMS320DM365, is data-out bus under this pattern, is connected with FPGA input FIFO;For
The write enable signal of TMS320DM365 output, as in FPGA FIFO write clock, from the sequential of writing of EMIF interface, several
Exist according to meetingRising edge be stored into dispensing device the FIFO of FPGA in;
During the hardware of the TMS320DM365 and FPGA of reception device is connected,It is the piece of TMS320DM365 output
Select signal, the reading as FIFO in FPGA enables, and Low level effective;EM_D is the bidirectional data line of TMS320DM365, this mould
It is data input bus (DIB) under formula, be connected with FPGA output FIFO;Reading for TMS320DM365 output enables signal,
Reading clock as FIFO in FPGA.From the reading sequential of EMIF interface,Rising edge video data is led to
Cross EMIF interface by the FIFO write TMS320DM365 of FPGA.
In present embodiment, in whole system, 3 test points A, B, C are set, are tested, test point A, B, C are in system
In position as shown in Figure 4.
In test process, first in dispensing device, TMS320DM365 sends data to FPGA in this device, then sends
In device, FPGA sends the data to FPGA in reception device, and in last reception device, FPGA sends the data to reception device again
Middle TMS320DM365.The FPGA waveform of wherein tri- test points of A, B and C respectively as shown in Fig. 6,7 and 8, by comparing
The data of TMS320DM365 transmission and reception is it was demonstrated that the Interface design between TMS320DM365 and FPGA is correct.
Claims (8)
1. the interface driver method of the EMIF under embedded Linux system and FPGA is it is characterised in that it is based on following transmission dresses
Put and reception device realization, the data signal output of dispensing device is connected with the data signal input of reception device,
Dispensing device includes DSP and FPGA, and wherein, described writing of DSP enables control signal outfan and FPGA
Write enable signal input connect, the write clock signal outfan of DSP is connected with the write clock signal input of FPGA, DSP
Data signal output be connected with the data signal input of FPGA, the data signal output conduct of FPGA in dispensing device
The data signal output of dispensing device;
Reception device includes DSP and FPGA, and wherein, the reading of described FPGA enables control signal input and DSP
Reading enable signal output part and connect, the read clock signal input of FPGA is connected with the read clock signal outfan of DSP, FPGA
Interrupt trigger signal outfan be connected with the interrupt signal input of DSP, the data signal output of FPGA and the data of DSP
Signal input part connects, and in reception device, the data signal input of FPGA is as the data signal input of reception device;
The DSP in DSP and reception device in dispensing device is the DSP containing EMIF port,
The DSP in DSP and reception device in dispensing device all embedded in (SuSE) Linux OS and EMIF drive module,
Under (SuSE) Linux OS, EMIF drive module is used for realizing the communication of DSP and FPGA,
Being embedded in the realization of the EMIF drive module within the DSP in dispensing device to the method for FPGA interface driving is,
Step 1:Realize the unloading that EMIF drive module unloads function to the loading of driving equipment loading function and this driving equipment,
Step 2:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, behaviour will be write to FIFO
It is mapped as the write operation to described memory address, the EMIF port realizing DSP in dispensing device is in dispensing device
In FPGA, FIFO carries out write operation,
Step 3:After DSP in reception device receives interrupt trigger signal, execute interrupt handling program, make in reception device
The EMIF port of DSP reads, in the FIFO of FPGA from reception device, the byte specifying number, and stores Linux operation system
In the buffer area of system kernel, wake up reading process;
Step 4:By EMIF drive module, the FIFO of FPGA is mapped as a memory address of DSP, by the reading behaviour to FIFO
It is mapped as the read operation to described memory address, the EMIF port realizing DSP in reception device is in reception device
In FPGA, FIFO carries out read operation, that is, complete the data communication between EMIF port and the interface of FPGA.
2. the interface driver method of the EMIF under embedded Linux system according to claim 1 and FPGA, its feature exists
In described realizes the unloading that EMIF drive module unloads function to the loading of driving equipment loading function and this driving equipment
In,
EMIF drive module to the loading procedure of driving equipment loading function is:
During EMIF drive module is driven to driving equipment, first, device number is applied for, and EMIF is driven
Dynamic model block is registered in (SuSE) Linux OS, by device number, (SuSE) Linux OS determines that the corresponding EMIF of this equipment drives mould
Block, completes the loading to driving equipment loading function for the EMIF drive module,
EMIF drive module to driving equipment unload function uninstall process be:
Device number is discharged, and the internal memory shared by corresponding for driving equipment EMIF drive module is discharged, and returned
Return I/O resource to system, complete the unloading that EMIF drive module unloads function to driving equipment.
3. the interface driver method of the EMIF under embedded Linux system according to claim 1 and 2 and FPGA, it is special
Levy and be, the EMIF port of the described DSP realizing in dispensing device carries out write operation to FIFO in the FPGA in dispensing device
Detailed process be,
By write operation write () function by the FPGA's copying in DSP from dispensing device for the data in dispensing device
In FIFO.
4. the interface driver method of the EMIF under embedded Linux system according to claim 3 and FPGA, its feature exists
In the EMIF port of the described DSP realizing in reception device carries out the tool of read operation to FIFO in the FPGA in reception device
Body process is,
By read operation read () function by the data duplication in the kernel cache area of DSP in reception device to user's space.
5. the interface driver method of EMIF and FPGA under the embedded Linux system according to claim 1,2 or 4, its
It is characterised by, after the DSP in described reception device receives interrupt trigger signal, the detailed process of execution interrupt handling program
For,
Step 4-1:Removing interrupt identification, execution step 4-2,
Step 4-2:Using I/O operation function by the DSP's of the data duplication of FIFO in the FPGA of reception device to reception device
The buffer area of kernel spacing, execution step 4-3,
Step 4-3:Judge whether the buffer area of kernel spacing expires half, result is yes, execution step 4-4, and result is no, execution
Step 4-5,
Step 4-4:Wake up the reading process of the user's space blocking, execution step 4-5;
Step 4-5:Interrupt returning.
6. the interface driver method of the EMIF under embedded Linux system according to claim 4 and FPGA, its feature exists
In, described by read operation read () function by the data duplication in the kernel cache area of DSP in reception device to user's space
Detailed process be:
Step 5-1:Whether the kernel cache area judging DSP in reception device is empty, and result is yes, execution step 5-2, and result is
No, execution step 5-3,
Step 5-2:Reading process dormancy, until buffer area is not space-time, execution step 5-3,
Step 5-3:Wake-up reading process, execution step 5-4,
Step 5-4:By read operation read () function, the data duplication in the kernel cache area of DSP in reception device is empty to user
Between, execution step 5-5,
Step 5-5:Release semaphore.
7. the interface driver method of the EMIF under embedded Linux system according to claim 3 and FPGA, its feature exists
In the described FPGA that will be copied in DSP from dispensing device for the data in dispensing device by write operation write () function
FIFO in detailed process be:
Step 3-1:After the kernel spacing application buffer area of DSP in dispensing device, execution step 3-2,
Step 3-2:By the buffer area of the data duplication of user's space to kernel spacing, execution step 3-3,
Step 3-3:By write operation write () function, kernel spacing buffer area content is copied to the FPGA's in dispensing device
In FIFO, execution step 3-4;
Step 3-4:Release semaphore.
8. the interface driver side of EMIF and FPGA under the embedded Linux system according to claim 1,2,4,6 or 7
Method is it is characterised in that the DSP in DSP and reception device in described dispensing device is all using model TMS320DM365
Chip is realized.
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