CN103972236B - 包含鳍式场效电晶体装置的集成电路及其制造方法 - Google Patents

包含鳍式场效电晶体装置的集成电路及其制造方法 Download PDF

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CN103972236B
CN103972236B CN201410044017.7A CN201410044017A CN103972236B CN 103972236 B CN103972236 B CN 103972236B CN 201410044017 A CN201410044017 A CN 201410044017A CN 103972236 B CN103972236 B CN 103972236B
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CN103972236A (zh
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蔡秀雨
谢瑞龙
A·卡基菲鲁兹
程慷果
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GlobalFoundries Inc
International Business Machines Corp
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Abstract

本发明涉及包含鳍式场效电晶体装置的集成电路及其制造方法，提供数种集成电路及用以制造集成电路的方法。在一实施例中，集成电路包含半导体基板。彼此毗邻地从该半导体基板延伸的第一鳍片及第二鳍片。该第一鳍片有第一上半段以及该第二鳍片有第二上半段。第一磊晶部覆于该第一上半段上以及第二磊晶部覆于该第二上半段上。第一硅化物层覆于该第一磊晶部上以及第二硅化物层覆于该第二磊晶部上。该第一及该第二硅化物层彼此隔开以定义横向间隙。介电间隔体由介电材料形成以及跨越该横向间隙。接触形成材料覆于该介电间隔体以及该第一及该第二硅化物层横向在该介电间隔体上方的部分上。

Description

包含鳍式场效电晶体装置的集成电路及其制造方法
技术领域
本发明所属的技术领域大体有关于集成电路及集成电路的制造方法，且更特别的是，有关于包含有较低接触电阻和降低寄生电容的鳍式场效晶体管装置的集成电路以及此类集成电路的制造方法。
背景技术
晶体管，例如金属氧化物半导体场效晶体管(MOSFET)或单单场效晶体管(FET)或MOS晶体管，为绝大多数半导体集成电路(IC)的核心建构块。FET包含源极和漏极区，在施加至覆在通道上的栅极电极的偏压的影响下，电流可在源极和漏极区之间流动通过。有些半导体IC，例如高效能微处理器，可包含数百万个FET。对于此类IC，减少晶体管尺寸从而增加晶体管密度在半导体制造工业有传统高度优先性。不过，即使晶体管尺寸减少，仍须维持晶体管效能。
鳍式场效晶体管为对减少晶体管大小同时维持晶体管效能的目标帮助的一种晶体管。鳍式场效晶体管为形成于由半导体基板向上伸出的细鳍片中的非平面三维晶体管。实现鳍式场效晶体管的重要挑战之一是形成至鳍片的非平面源极/漏极区的接触。形成用于鳍式场效晶体管的接触有以下两种方法：形成至合并鳍片(merged fin)的接触与形成分离鳍片(un合并鳍片)的接触。
至于合并鳍片，是在鳍片上成长一层磊晶硅。该磊晶成长致使毗邻鳍片合并。所得接触面积变大以及缺乏形貌变化。因此，现有硅化制程可用来在合并鳍片的正面上成功地形成硅化物接触。
至于分离鳍片，在每个鳍片上面成长个别的磊晶掺杂硅或硅锗层而不是合并毗邻鳍片的磊晶成长。分离鳍片，例如，对于静态随机存取记忆体(SRAM)装置及其类似者是必要的。分离鳍片允许SRAM单元有更紧的间距使得整体晶片布局更小。介面电阻率(Rs)为集成电路的总接触电阻的重要因子，以及多个分离鳍片提供更多接触形成面积，因为有更多表面积暴露于硅化制程。接触的总电阻可明显小于鳍片的合并集合(他们有较小的接触表面积而有较高的电阻)。不过，在形成接触期间，导电接触形成材料可沉积于分离鳍片的下半段之间而产生较高的寄生电容。压低许多小分离鳍片的接触电阻及减少寄生电容可使电路效能有显著的差异。
因此，最好提供包含具有较低接触电阻和降低寄生电容的鳍式场效晶体管装置的集成电路以及制造此类集成电路的方法。此外，最好提供包含具有较低接触电阻分离鳍片同时不增加寄生电容的鳍式场效晶体管装置的集成电路。此外，由以下结合附图及本段内容的详细说明及权利要求书可明白本发明的其他合意特征及特性。
发明内容
本文提供数种集成电路及用以制造集成电路的方法。根据一示范具体实施例，一种集成电路制造方法，其包含下列步骤：形成彼此毗邻地从半导体基板延伸的第一鳍片与第二鳍片。在该第一及该第二鳍片上选择性磊晶成长含硅材料，以形成覆于该第一鳍片的第一上半段上的第一磊晶部以及覆于该第二鳍片的第二上半段上的第二磊晶部。该第一及该第二磊晶部彼此隔开。形成覆于该第一磊晶部上的第一硅化物层，以及形成覆于该第二磊晶部上的第二硅化物层。该第一及该第二硅化物层彼此隔开以定义横向间隙。沉积覆于该第一及该第二硅化物层上的介电材料以形成跨越该横向间隙的介电间隔体。移除覆于该第一及该第二硅化物层横向在该介电间隔体上方的部分上的该介电材料，并且使该介电间隔体保持完整。沉积覆该介电间隔体及该第一及该第二硅化物层的该等部分上的接触形成材料。
根据另一示范具体实施例，提供一种用于制造集成电路的方法。该方法包括：形成彼此毗邻地从半导体基板延伸的第一鳍片与第二鳍片。在该第一及该第二鳍片上选择性磊晶成长含硅材料，以形成配置于该第一鳍片的第一上半段上的第一菱形截面磊晶部(firstdiamond-shaped/cross-section epi-portion)以及配置于该第二鳍片的第二上半段上的第二菱形截面磊晶部。该第一菱形截面磊晶部有第一上表面与第一下表面。该第二菱形截面磊晶部有第二上表面与第二下表面。该第一及该第二菱形截面磊晶部彼此隔开。形成沿着该第一菱形截面磊晶部的该第一上表面及该第一下表面的第一硅化物层，以及形成沿着该第二菱形截面磊晶部的该第二上表面及该第二下表面的第二硅化物层。该第一及该第二硅化物层彼此隔开以定义横向间隙。沉积覆于该第一及该第二硅化物层上的介电材料以形成封闭该横向间隙的介电间隔体。蚀刻该介电材料，以暴露该第一及该第二硅化物层各自覆于该第一及该第二菱形截面磊晶部的该第一及该第二上表面上的上半部，并且使该介电间隔体保持完整。沉积由绝缘材料组成的ILD层，其覆于该介电间隔体与该第一及该第二硅化物层上的该等上半部。蚀刻该ILD层以形成穿过该ILD层以暴露该第一及该第二硅化物层的该等上半部的接触开口。沉积接触形成材料于该接触开口内。
根据另一示范具体实施例，提供一种集成电路。该集成电路包含半导体基板。彼此毗邻地从该半导体基板延伸的第一鳍片及第二鳍片。该第一鳍片有第一上半段以及该第二鳍片有第二上半段。第一磊晶部覆于该第一上半段上以及第二磊晶部覆于该第二上半段上。该第一及该第二磊晶部彼此隔开。第一硅化物层覆于该第一磊晶部上以及第二硅化物层覆于该第二磊晶部上。该第一及该第二硅化物层彼此隔开以定义横向间隙。介电间隔体由介电材料形成以及跨越该横向间隙。接触形成材料覆于该介电间隔体以及该第一及该第二硅化物层横向在该介电间隔体上方的部分上。
附图说明
以下结合附图描述各种具体实施例，其中类似的元件用相同的元件符号表示：
图1图示鳍式场效晶体管的部分剖开透视图；以及
图2至图9的横截面图根据一示范具体实施例图示在不同制造阶段的集成电路及集成电路制造方法。
主要组件符号说明
10 鳍式场效晶体管集成电路(IC)
12、14 鳍片 16 半导体基板
18 栅极电极 20、24、26、28 末端
22、30 鳍式场效晶体管 32 氧化物层
34 侧壁 36 顶部
38 箭头 40、42 阱区
44、46 磊晶部 48、50 上半段
52、54 分离鳍片 56a、56b、58a、58b 上表面
60a、60b、62a、62b 下表面 61、63 硅化物层
64 横向间隙 66、68 中间转角
70、72 电介质膜 74a、74b、76a、76b 上半部
78a、78b、80a、80b 下半部
82 介电间隔体 84、86 电介质膜上半段
88、90 电介质膜下半段 92 空腔
94、96 下半段 98 氮化物蚀刻层
100 ILD层 102 接触开口
103 接触形成材料 104 接触插塞
106、108 最上部。
具体实施方式
以下详细说明本质上只是示范说明而非旨在限制各个具体实施例及其应用和用途。此外，不希望受限于在【背景技术】或【具体实施方式】中提及的任何理论。
可设计有数百万个晶体管的集成电路(IC)。许多IC是用金属氧化物半导体(MOS)晶体管设计，也习称场效晶体管(FET)或MOSFET。尽管用语“MOS晶体管”正确是指具有金属栅极及氧化物栅极绝缘体的装置，然而此用语在本文意指包含安置于栅极绝缘体(不论是氧化物还是其他绝缘体)上方的导电栅极(不论是金属还是其他导电材料)的任何装置，其中栅极绝缘体是安置于半导体基板上方。使用于IC设计的一种MOS晶体管是鳍式场效晶体管，它制造成P型通道晶体管或N型通道晶体管，以及也可制造成具有或没有移动率增强用应力特征。利用带有应力及没有应力的P型通道及N型通道、鳍式场效晶体管及其他种类MOS晶体管，电路设计者可混合及匹配装置类型，以在最适合所设计的电路时利用每种装置类型的最佳特性。
以下提供简要解释以确定鳍式场效晶体管的一些独特特征。图1的剖开透视图图示鳍式场效晶体管集成电路(IC)10的一部分。如图示，IC 10包含由半导体基板16(例如，块体半导体基板或绝缘体上硅(SOI)半导体基板)形成及由其向上延伸的两个鳍片12、14。栅极电极18覆于这两个鳍片12及14上以及用栅极绝缘体(未图示)与鳍片12及14电绝缘。用杂质适当地掺杂鳍片12的末端20以形成鳍式场效晶体管22的源极，用杂质适当地掺杂鳍片12的末端24以形成鳍式场效晶体管22的漏极。同样，鳍片14的末端26及28各自形成另一鳍式场效晶体管30的源极及漏极。
因此，IC 10的图示部分包含有共用栅极电极18的两个鳍式场效晶体管22及30。在另一组构中，如果形成源极的末端20及26电耦合在一起以及形成漏极的末端24及28电耦合在一起，则该结构是栅极宽度为鳍式场效晶体管22或者是30的两倍的两鳍片鳍式场效晶体管。按照所实现的电路的需要，氧化物层32(例如，如果半导体基板16为块体半导体基板，其沉积于半导体基板16上，或者，如果半导体基板16为SOI半导体基板，它为半导体基板16的一部分)形成鳍片12及14之间与毗邻装置之间的电气隔离。鳍式场效晶体管22的通道沿着鳍片12在栅极电极18下方的侧壁34，鳍片12的顶部36，以及本透视图看不到的相对侧壁延伸。鳍式场效晶体管结构的优点在于：尽管鳍片12有如箭头38所示的狭窄宽度，然而在氧化物层32上方，通道的宽度至少为鳍片12的高度的两倍。因此，通道宽度可远大于鳍片宽度。
鳍片12及14用现有制程形成。例如，在用SOI半导体基板作为半导体基板16时，部分蚀刻或以其他方式移除半导体基板16的上硅层留下由留在底下氧化物层32的硅形成的鳍片12及14。如图示，形成横越鳍片12及14的栅极电极18。在形成栅极电极18之前，在鳍片12及14上面可沉积栅极氧化物及/或氮化物覆盖层(未图示)。栅极电极18用典型的微影加工法形成。
图2至图9根据各种具体实施例图示用于形成IC 10的方法。特别是，图2至图9的横截面图图示在制造IC 10的各个顺序阶段的鳍片12及14(图示于图1)的源极区20、26或漏极区24、28。提及制程步骤、程序及材料应被视为该等示范具体实施例只是设计成用来向本技艺一般技术人员图解说明用于实施本文所设想到的方法的方法；该等方法不受限于该等示范具体实施例。IC 10的图示部分只图示两个鳍式场效晶体管22及30，然而熟谙此艺者会认识到实际IC可包含大量的此类晶体管。制造IC的各种步骤为众所周知，为求简洁，本文只简述或完全省略许多现有的步骤而不提供众所周知的加工细节。
图2的横截面图根据一示范具体实施例图示处于中间制造阶段的IC 10的一部分。如上述，已彼此毗邻地形成从半导体基板16伸出在氧化物层32上方延伸的鳍片12及14。进一步的图案化、植入及退火制程在半导体基板16中用来在鳍片12及14下方形成阱区40及42。选择性磊晶成长制程用来成长覆于鳍片12及14的上半段48及50上的含硅材料以各自形成磊晶部44及46。在一示范具体实施例中，该含硅材料为用于N型鳍式场效晶体管的硅磷(SiP)或用于P型鳍式场效晶体管的硅锗(SiGe)。
磊晶部44及46彼此隔开使得鳍片12及14不合并以定义分离鳍片52及54。如图示，磊晶部44及46组构成有“菱形截面”。磊晶部44及46形成菱形截面的原因是含硅材料在鳍片12及14(111)的表面上的成长速率比较慢。同样地，磊晶部44及46有对应上表面56a、56b、58a及58b和下表面60a、60b、62a及62b。下表面60a、60b、62a及62b面向半导体基板16，以及上表面56a、56b、58a及58b是安置在越过下表面60a、60b、62a及62b而背向半导体基板16处。
图3的横截面图根据一示范具体实施例图示在更进一步制造阶段的IC 10的一部分。用硅化制程，各自在磊晶部44及46上面形成硅化物层61及63。硅化物层61及63的形成是通过沉积覆于磊晶部44及46的上表面56a、56b、58a及58b及下表面60a、60b、62a及62b上的硅化物成形金属，以及加热该硅化物成形金属，例如用快速热退火(RTA)法，以造成硅化物成形金属与磊晶部44及46的暴露含硅材料反应。硅化物成形金属的实施例包含(但不受限于)：镍、钴及彼等的合金。例如可用溅镀法沉积厚约3至10纳米(例如，约7纳米)的硅化物成形金属。例如，用湿蚀刻以过氧化氮/硫酸或硝酸/盐酸溶液，可移除任何未反应的硅化物成形金属。在一示范具体实施例中，硅化物层61及63各自厚约3至10纳米。值得注意的是，在菱形磊晶部44及46的上下方形成硅化物有助于最大化接触表面积从而减少接触电阻。
如图示，硅化物层61及63彼此隔开借此在紧邻磊晶部44及46的菱形截面的中间转角66及68的硅化物层61及63之间定义横向间隙64。在一示范具体实施例中，该横向间隙约有3至7纳米。
制程继续，如图4所示，沉积介电材料于氧化物层32及包含硅化物层61及63的分离鳍片52及54上面。在一示范具体实施例中，该介电材料用原子层沉积(ALD)制程沉积以及包含氮化硅(SiN)，它可掺杂碳原子(C)、氮原子(N)及/或氧原子(O)。
在沉积期间，该介电材料累积于硅化物层61及63的上、下半部74a、74b、76a、76b、78a、78b、80a及80b和周遭区域上以形成电介质膜70及72。随着电介质膜70及72的厚度增加，紧邻磊晶部44及46的菱形截面的中间转角66及68的电介质膜70及72会合并在一起以一体形成介电间隔体82(以虚线图示)。如图示，介电间隔体82跨越及封闭横向间隙64。
在一示范具体实施例中，介电间隔体82有至少约3纳米的横向尺寸，例如约3至约10纳米，例如约3至约7纳米，以封闭横向间隙64。如图示，如以下所详述的，为了促进介电间隔体82在后续加工期间保持完整，与各自覆于硅化物层61及63的下半部78a、78b、80a及80b上的电介质膜下半段88及90相比，例如用过度成长的方式形成比较厚的电介质膜上半段84及86(各自覆于硅化物层61及63的上半部74a、74b、76a及76b上)。在一示范具体实施例中，形成各自厚约5至15纳米的电介质膜上半段84及86以及形成各自厚约2至7纳米的电介质膜下半段88及90。如图示，在介电间隔体82下方，配置空腔92于半导体基板16、鳍片12及14的下半段94及96和电介质膜下半段88及90之间。值得注意的是，在一示范具体实施例中，空腔92使得空气能困在介电间隔体82下方，以及与介电间隔体82的低k特性一起产生极低的寄生电容。
图5的横截面图根据一示范具体实施例图示在更进一步制造阶段的IC 10的一部分。通过蚀刻介电材料以暴露硅化物层61及63的上半部74a、74b、76a及76b同时让介电间隔体82保持完整，来移除电介质膜上半段84及86(参考图4)。在一具体实施例中，用干蚀刻制程，例如电浆蚀刻制程，例如反应性离子蚀刻(RIE)，来移除该介电材料。在另一具体实施例中，用湿蚀刻制程，例如热磷酸蚀刻制程，以约160至约170℃的温度，来蚀刻该介电材料。通过使介电间隔体82保持完整，空腔92有保护性覆盖以减少、最小化或防止进一步沉积任何传导材料(例如，接触形成材料，例如钨及/或类似者)于鳍片12及14的下半段94及96附近及其间，否则寄生电容可能增加。
该方法继续，如图6及图7所示，形成覆于介电间隔体82及硅化物层61及63的上半部74a、74b、76a及76b上的氮化物蚀刻层98。然后，沉积覆于氮化物蚀刻终止层98上由绝缘材料(例如，氧化硅)组成的ILD层100。在一示范具体实施例中，ILD层100是用低压化学气相沉积(LPCVD)制程沉积。然后，平坦化ILD层100，例如，用化学机械平坦化(CMP)制程。
图8至图9的横截面图根据一示范具体实施例图示在更进一步制造阶段的IC 10的一部分。该方法继续蚀刻穿过ILD层100及氮化物蚀刻终止层98以形成接触开口102。如图示，接触开口102暴露介电间隔体82和硅化物层61及63的上半部74a、74b、76a及76b。沉积接触形成材料103(例如，导电金属)于接触开口102内以形成覆于介电间隔体82及硅化物层61及63的上半部74a、74b、76a及76b上的接触插塞(contact plug)104。在一示范具体实施例中，接触形成材料103为钨(W)。如图示，在沉积接触形成材料103期间被介电间隔体82覆盖而受保护的空腔92实质上没有接触形成材料103，从而与有分离鳍片的现有IC相比，可降低寄生电容。另外，接触插塞104大约从磊晶部44及46的中间转角66及68向上到硅化物层61及63的最上部106及108而与硅化物层61及63水平接触。同样地，鳍式场效晶体管22及30有更多接触面积从而接触电阻低于具有只能在鳍片最上端形成小接触的分离鳍片的现有鳍式场效晶体管装置。然后，用CMP移除配置于ILD层100上面的任何多余接触形成材料。
因此，已描述包含鳍式场效晶体管装置的集成电路以及用于制造此类集成电路的方法。在一示范具体实施例中，形成数个分离鳍片，其中第一鳍片有第一磊晶部以及第二鳍片有第二磊晶部。形成覆于第一磊晶部上的第一硅化物层以及形成覆于该第二磊晶部上的第二硅化物层。该第一及该第二硅化物层彼此隔开以定义横向间隙。沉积覆于该第一及该第二硅化物层上的介电材料以形成跨越该横向间隙的介电间隔体。移除覆于该第一及该第二硅化物层横向在该介电间隔体上方的部分上的介电材料同时使该介电间隔体保持完整。沉积覆于该介电间隔体及该第一及该第二硅化物层的部分上的接触形成材料。
尽管以上详细说明已陈述至少一个示范具体实施例，然而应了解，仍有有许多变体。也应了解，该(等)示范具体实施例并非旨在以任何方式限制本揭示内容的范畴、适用性或组构。反而，上述详细说明是要让熟谙此艺者有个方便的发展蓝图用来具体实作本揭示内容的示范具体实施例，应了解，示范具体实施例中提及的元件的功能及配置可做出不同的改变而不脱离如权利要求书所述的本揭示内容范畴。

Claims (20)

1.一种制造集成电路的方法，包含：
形成彼此毗邻地从半导体基板延伸的第一鳍片与第二鳍片；
在该第一及该第二鳍片上选择性磊晶成长含硅材料，以形成覆于该第一鳍片的第一上半段上的第一磊晶部以及覆于该第二鳍片的第二上半段上的第二磊晶部，其中，该第一及该第二磊晶部彼此隔开；
形成覆于该第一磊晶部上的第一硅化物层以及覆于该第二磊晶部上的第二硅化物层，其中，该第一及该第二硅化物层彼此隔开以定义横向间隙；
沉积覆于该第一及该第二硅化物层上的介电材料，以形成跨越该横向间隙的介电间隔体；
移除覆于该第一及该第二硅化物层横向在该介电间隔体上方的部分上的该介电材料，并且使该介电间隔体保持完整；以及
沉积覆于该介电间隔体及该第一及该第二硅化物层的该部分上的接触形成材料。
2.根据权利要求1所述的方法，其中，形成该第一及该第二硅化物层包括：形成具有一厚度使得该横向间隙为3至7纳米的该第一及该第二硅化物层。
3.根据权利要求1所述的方法，其中，沉积该介电材料包括：沉积包含掺杂碳原子(C)、氮原子(N)、氧原子(O)或其组合的氮化硅(SiN)的该介电材料。
4.根据权利要求1所述的方法，其中，沉积该介电材料包括：使用原子层沉积(ALD)制程沉积该介电材料。
5.根据权利要求1所述的方法，其中，移除该介电材料包括：使用电浆蚀刻制程移除该介电材料。
6.根据权利要求1所述的方法，其中，移除该介电材料包括：使用湿蚀刻制程移除该介电材料。
7.根据权利要求1所述的方法，其中，沉积该接触形成材料包括：沉积包括钨的该接触形成材料。
8.一种制造集成电路的方法，包含：
形成彼此毗邻地从半导体基板延伸的第一鳍片与第二鳍片；
在该第一及该第二鳍片上选择性磊晶成长含硅材料，以形成配置于该第一鳍片的第一上半段上的第一菱形截面磊晶部以及配置于该第二鳍片的第二上半段上的第二菱形截面磊晶部，其中，该第一菱形截面磊晶部具有第一上表面与第一下表面，以及该第二菱形截面磊晶部具有第二上表面与第二下表面，以及其中，该第一及该第二菱形截面磊晶部彼此隔开；
形成沿着该第一菱形截面磊晶部的该第一上表面及该第一下表面的第一硅化物层，以及沿着该第二菱形截面磊晶部的该第二上表面及该第二下表面的第二硅化物层，其中，该第一及该第二硅化物层彼此隔开以定义横向间隙；
沉积覆于该第一及该第二硅化物层上的介电材料，以形成封闭该横向间隙的介电间隔体；
蚀刻该介电材料，以暴露该第一及该第二硅化物层各自覆于该第一及该第二菱形截面磊晶部的该第一及该第二上表面上的上半部，并且使该介电间隔体保持完整；
沉积由绝缘材料组成的ILD层，其覆于该介电间隔体及该第一及该第二硅化物层上的该上半部；
蚀刻该ILD层以形成穿过该ILD层的接触开口，以暴露该第一及该第二硅化物层的该上半部；以及
沉积接触形成材料于该接触开口内。
9.根据权利要求8所述的方法，其中，该第一及该第二硅化物层各自具有覆于该第一及该第二菱形截面磊晶部的该第一及该第二下表面上的下半部，以及其中，沉积该介电材料包括：
形成覆于该第一硅化物层的该上及该下半部上的第一电介质膜；以及
形成覆于该第二硅化物层的该上及该下半部上的第二电介质膜。
10.根据权利要求9所述的方法，其中，沉积该介电材料包括：
形成具有各自覆于该第一硅化物层的该上及该下半部上的第一电介质膜上半段及第一电介质膜下半段的该第一电介质膜，其中，该第一电介质膜上半段比该第一电介质膜下半段厚；以及
形成具有各自覆于该第二硅化物层的该上及该下半部上的第二电介质膜上半段及第二电介质膜下半段的该第二电介质膜，其中，该第二电介质膜上半段比该第二电介质膜下半段厚。
11.根据权利要求10所述的方法，其中，沉积该介电材料包括：形成各自具有5至15纳米的厚度的该第一及该第二电介质膜上半段。
12.根据权利要求10所述的方法，其中，沉积该介电材料包括：形成各自具有2至7纳米的厚度的该第一及该第二电介质膜下半段。
13.根据权利要求10所述的方法，其中，该第一鳍片具有配置于该第一菱形截面磊晶部下方的第一下半段，以及该第二鳍片具有配置于该第二菱形截面磊晶部下方的第二下半段，以及其中，沉积该介电材料包括：以该介电间隔体封闭该横向间隙以形成被该半导体基板、该第一及该第二鳍片的该第一及该第二下半段、该第一及该第二电介质膜下半段及该介电间隔体包围的空腔。
14.根据权利要求8所述的方法，更包括：
在蚀刻该介电材料之后但是在沉积该ILD层之前，形成覆于该第一及该第二硅化物层的该上半部上的氮化物蚀刻终止层，其中，蚀刻该ILD层包括：蚀刻该氮化物蚀刻终止层以暴露该第一及该第二硅化物层的该上半部。
15.一种集成电路，包含：
半导体基板；
彼此毗邻地从该半导体基板延伸的第一鳍片与第二鳍片，其中，该第一鳍片具有第一上半段以及该第二鳍片具有第二上半段；
覆于该第一上半段上的第一磊晶部与覆于该第二上半段上的第二磊晶部，其中，该第一及该第二磊晶部彼此隔开；
覆于该第一磊晶部上的第一硅化物层与覆于该第二磊晶部上的第二硅化物层，其中，该第一及该第二硅化物层彼此隔开以定义横向间隙；
介电间隔体，其由介电材料形成以及跨越该横向间隙；以及
接触形成材料，其覆于该介电间隔体以及该第一及该第二硅化物层横向在该介电间隔体上方的部分上。
16.根据权利要求15所述的集成电路，其中，该第一磊晶部为具有第一上表面及第一下表面的第一菱形截面磊晶部，以及该第二磊晶部为具有第二上表面及第二下表面的第二菱形截面磊晶部，以及其中，该第一硅化物层沿着该第一菱形截面磊晶部的该第一上表面及该第一下表面配置，以及该第二硅化物层沿着该第二菱形截面磊晶部的该第二上表面及该第二下表面配置。
17.根据权利要求16所述的集成电路，其中，该第一及该第二硅化物层具有覆于该第一及该第二菱形截面磊晶部的该第一及该第二下表面上的下半部，以及其中，该集成电路更包含：
覆于该第一硅化物层的该下半部上的第一电介质膜；以及
覆于该第二硅化物层的该下半部上的第二电介质膜，其中，该介电间隔体与该第一及该第二电介质膜是一体成型。
18.根据权利要求17所述的集成电路，其中，该第一鳍片具有配置于该第一菱形截面磊晶部下方的第一下半段，以及该第二鳍片具有配置于该第二菱形截面磊晶部下方的第二下半段，以及其中，该半导体基板、该第一及该第二鳍片的该第一及该第二下半段、该第一及该第二电介质膜下半段、以及该介电间隔体一起围成空腔。
19.根据权利要求18所述的集成电路，其中，该空腔没有该接触形成材料。
20.根据权利要求15所述的集成电路，其中，该介电间隔体具有至少3纳米的横向尺寸以封闭该横向间隙。
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Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9397098B2 (en) 2012-03-08 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET-based ESD devices and methods for forming the same
US8779517B2 (en) 2012-03-08 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET-based ESD devices and methods for forming the same
US9147682B2 (en) 2013-01-14 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin spacer protected source and drain regions in FinFETs
US8921191B2 (en) * 2013-02-05 2014-12-30 GlobalFoundries, Inc. Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
US9385198B2 (en) * 2013-03-12 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for semiconductor devices and methods of forming the same
US9752251B2 (en) * 2013-04-15 2017-09-05 International Business Machines Corporation Self-limiting selective epitaxy process for preventing merger of semiconductor fins
US9054218B2 (en) * 2013-08-07 2015-06-09 International Business Machines Corporation Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same
US9214556B2 (en) 2013-08-09 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned dual-metal silicide and germanide formation
US20150087144A1 (en) * 2013-09-26 2015-03-26 Taiwan Semiconductor Manufacturing Company Ltd. Apparatus and method of manufacturing metal gate semiconductor device
US9472652B2 (en) * 2013-12-20 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
US9425310B2 (en) * 2014-03-04 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming wrap around contact
US9406804B2 (en) * 2014-04-11 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with contact-all-around
US9443769B2 (en) * 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9373550B2 (en) 2014-04-23 2016-06-21 International Business Machines Corporation Selectively degrading current resistance of field effect transistor devices
US9349649B2 (en) 2014-06-26 2016-05-24 Globalfoundries Inc. Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs
US9966471B2 (en) * 2014-06-27 2018-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Gate-All-Around FinFET and method forming the same
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
US9431303B2 (en) * 2014-10-17 2016-08-30 Globalfoundries Inc. Contact liners for integrated circuits and fabrication methods thereof
US9653605B2 (en) 2014-10-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9472470B2 (en) 2014-12-09 2016-10-18 GlobalFoundries, Inc. Methods of forming FinFET with wide unmerged source drain EPI
KR20160072476A (ko) * 2014-12-15 2016-06-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN105845725B (zh) * 2015-01-12 2019-01-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
KR102340329B1 (ko) 2015-03-25 2021-12-21 삼성전자주식회사 반도체 소자
KR102379267B1 (ko) 2015-04-01 2022-03-28 삼성전자주식회사 아이솔레이션 영역 상의 스페이서를 갖는 반도체 소자
US9443853B1 (en) 2015-04-07 2016-09-13 International Business Machines Corporation Minimizing shorting between FinFET epitaxial regions
KR102326316B1 (ko) * 2015-04-10 2021-11-16 삼성전자주식회사 반도체 소자의 제조 방법
KR102432268B1 (ko) * 2015-04-14 2022-08-12 삼성전자주식회사 반도체 소자 및 그 제조 방법.
KR102310076B1 (ko) 2015-04-23 2021-10-08 삼성전자주식회사 비대칭 소스/드레인 포함하는 반도체 소자
KR102400375B1 (ko) 2015-04-30 2022-05-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9954107B2 (en) 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US9741829B2 (en) * 2015-05-15 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10483262B2 (en) 2015-05-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Dual nitride stressor for semiconductor device and method of manufacturing
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
KR20160143942A (ko) 2015-06-04 2016-12-15 삼성전자주식회사 반도체 소자의 제조 방법
KR102258109B1 (ko) * 2015-06-08 2021-05-28 삼성전자주식회사 누설 전류를 차단할 수 있는 반도체 소자 및 그의 형성 방법
KR102310081B1 (ko) 2015-06-08 2021-10-12 삼성전자주식회사 반도체 장치의 제조 방법
US9722043B2 (en) 2015-06-15 2017-08-01 International Business Machines Corporation Self-aligned trench silicide process for preventing gate contact to silicide shorts
US9627278B2 (en) 2015-06-16 2017-04-18 International Business Machines Corporation Method of source/drain height control in dual epi finFET formation
US9680020B2 (en) 2015-07-09 2017-06-13 Globalfoundries Inc. Increased contact area for FinFETs
US9455331B1 (en) 2015-07-10 2016-09-27 International Business Machines Corporation Method and structure of forming controllable unmerged epitaxial material
KR102422430B1 (ko) * 2015-07-16 2022-07-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10158003B2 (en) 2015-08-12 2018-12-18 International Business Machines Corporation Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
US10366988B2 (en) * 2015-08-14 2019-07-30 International Business Machines Corporation Selective contact etch for unmerged epitaxial source/drain regions
US9620644B2 (en) * 2015-09-02 2017-04-11 International Business Machines Corporation Composite spacer enabling uniform doping in recessed fin devices
US9472620B1 (en) * 2015-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9564358B1 (en) 2015-09-09 2017-02-07 International Business Machines Corporation Forming reliable contacts on tight semiconductor pitch
US10103249B2 (en) 2015-09-10 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device and method for fabricating the same
US9831116B2 (en) 2015-09-15 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. FETS and methods of forming FETs
US9905641B2 (en) * 2015-09-15 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
WO2017052630A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Wrap-around source/drain method of making contacts for backside metals
US10032884B2 (en) 2015-10-22 2018-07-24 International Business Machines Corporation Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling
US10177143B2 (en) * 2015-10-28 2019-01-08 Taiwan Semiconductor Manufacturing Company Limited FinFET device and method for fabricating the same
US9601586B1 (en) 2015-11-02 2017-03-21 Samsung Electronics Co., Ltd. Methods of forming semiconductor devices, including forming a metal layer on source/drain regions
US10497701B2 (en) * 2015-12-16 2019-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR102399353B1 (ko) 2016-01-05 2022-05-19 삼성전자주식회사 식각 방법 및 이를 이용한 반도체 소자의 제조 방법
TWI707403B (zh) * 2016-01-06 2020-10-11 聯華電子股份有限公司 半導體元件及其製作方法
US10249502B2 (en) 2016-01-22 2019-04-02 International Business Machines Corporation Low resistance source drain contact formation with trench metastable alloys and laser annealing
US20170250268A1 (en) * 2016-02-25 2017-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9755019B1 (en) 2016-03-03 2017-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10205025B2 (en) * 2016-03-11 2019-02-12 Samsung Electronics Co., Ltd. Methods to achieve strained channel finFET devices
CN107369621B (zh) * 2016-05-13 2020-03-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
US10157918B2 (en) 2016-08-03 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9837407B1 (en) 2016-09-06 2017-12-05 International Business Machines Corporation Semiconductor device with increased source/drain area
US9805989B1 (en) 2016-09-22 2017-10-31 International Business Machines Corporation Sacrificial cap for forming semiconductor contact
US10535652B2 (en) * 2016-10-27 2020-01-14 International Business Machines Corporation Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction
US10872889B2 (en) * 2016-11-17 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component and fabricating method thereof
US10707328B2 (en) * 2016-11-30 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming epitaxial fin structures of finFET
KR102587891B1 (ko) 2016-12-22 2023-10-12 삼성전자주식회사 반도체 소자
WO2018195420A1 (en) * 2017-04-20 2018-10-25 Micromaterials Llc Methods and structures to reduce contact resistance for finfet devices
US10164065B1 (en) * 2017-05-31 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Film deposition for 3D semiconductor structure
US10510875B2 (en) * 2017-07-31 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Source and drain structure with reduced contact resistance and enhanced mobility
US10541319B2 (en) * 2017-08-30 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures having varied fin heights for semiconductor device
KR102432467B1 (ko) * 2017-08-30 2022-08-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10763104B2 (en) 2017-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming differential etch stop layer using directional plasma to activate surface on device structure
US10347744B1 (en) 2018-01-09 2019-07-09 International Business Machines Corporation Method and structure of forming FinFET contact
CN110416297B (zh) * 2018-04-27 2023-07-04 中芯国际集成电路制造(上海)有限公司 N型鳍式场效应晶体管及其形成方法
US10373877B1 (en) 2018-05-22 2019-08-06 Globalfoundries Inc. Methods of forming source/drain contact structures on integrated circuit products
US10854716B2 (en) 2018-07-30 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with source/drain contact formed using bottom-up deposition
US10804368B2 (en) 2018-07-30 2020-10-13 International Business Machines Corporation Semiconductor device having two-part spacer
US10998241B2 (en) 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
DE102019118061A1 (de) * 2018-09-19 2020-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Selektive doppelsilizidherstellung unter verwendung eines maskenlosen herstellungsprozessablaufs
US10943818B2 (en) * 2018-10-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11121238B2 (en) * 2018-11-29 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11107752B2 (en) * 2020-01-03 2021-08-31 International Business Machines Corporation Half buried nFET/pFET epitaxy source/drain strap
US11164774B2 (en) * 2020-01-16 2021-11-02 International Business Machines Corporation Interconnects with spacer structure for forming air-gaps
US11244864B2 (en) 2020-04-21 2022-02-08 International Business Machines Corporation Reducing parasitic capacitance within semiconductor devices
US11450572B2 (en) * 2020-05-22 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11888064B2 (en) 2020-06-01 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11515165B2 (en) * 2020-06-11 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11502200B2 (en) * 2020-06-19 2022-11-15 Globalfoundries U.S. Inc. Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material
US11605673B2 (en) 2020-12-09 2023-03-14 International Business Machines Corporation Dual resistive random-access memory with two transistors
CN112582478B (zh) * 2020-12-30 2022-08-19 上海集成电路装备材料产业创新中心有限公司 鳍式场效应晶体管及其制备方法
KR20220135684A (ko) * 2021-03-31 2022-10-07 삼성전자주식회사 온도 센싱 장치 및 시스템 온 칩

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194755A (zh) * 2010-03-01 2011-09-21 台湾积体电路制造股份有限公司 鳍式场效晶体管及其制造方法
US8030108B1 (en) * 2008-06-30 2011-10-04 Stc.Unm Epitaxial growth of in-plane nanowires and nanowire devices

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7425500B2 (en) * 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US7560344B2 (en) * 2006-11-15 2009-07-14 Samsung Electronics Co., Ltd. Semiconductor device having a pair of fins and method of manufacturing the same
KR101225641B1 (ko) * 2006-12-27 2013-01-24 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2009032955A (ja) * 2007-07-27 2009-02-12 Toshiba Corp 半導体装置、およびその製造方法
US7910453B2 (en) * 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US8116121B2 (en) * 2009-03-06 2012-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing methods with using non-planar type of transistors
US8426923B2 (en) * 2009-12-02 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate semiconductor device and method
US8258572B2 (en) * 2009-12-07 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM structure with FinFETs having multiple fins
US8362572B2 (en) * 2010-02-09 2013-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Lower parasitic capacitance FinFET
US8263451B2 (en) * 2010-02-26 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy profile engineering for FinFETs
US8362574B2 (en) * 2010-06-04 2013-01-29 Kabushiki Kaisha Toshiba Faceted EPI shape and half-wrap around silicide in S/D merged FinFET
JP2012018968A (ja) 2010-07-06 2012-01-26 Elpida Memory Inc 半導体装置の製造方法
JP2013115272A (ja) * 2011-11-29 2013-06-10 Toshiba Corp 半導体装置とその製造方法
US8742457B2 (en) * 2011-12-16 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuses on semiconductor fins
US8377779B1 (en) * 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US9147765B2 (en) * 2012-01-19 2015-09-29 Globalfoundries Inc. FinFET semiconductor devices with improved source/drain resistance and methods of making same
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US20130221414A1 (en) * 2012-02-27 2013-08-29 Chao Zhao Semiconductor FET and Method for Manufacturing the Same
TWI449802B (zh) * 2012-06-06 2014-08-21 Univ Nat Chiao Tung 掺碳氮化矽薄膜及其製造方法與裝置
US10535735B2 (en) * 2012-06-29 2020-01-14 Intel Corporation Contact resistance reduced P-MOS transistors employing Ge-rich contact layer
US8846477B2 (en) * 2012-09-27 2014-09-30 Globalfoundries Inc. Methods of forming 3-D semiconductor devices using a replacement gate technique and a novel 3-D device
US8946029B2 (en) * 2012-11-12 2015-02-03 GlobalFoundries, Inc. Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
US9142633B2 (en) * 2012-12-13 2015-09-22 GlobalFoundries, Inc. Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
US8956942B2 (en) * 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US9812556B2 (en) * 2012-12-28 2017-11-07 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
KR102049774B1 (ko) * 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8921191B2 (en) * 2013-02-05 2014-12-30 GlobalFoundries, Inc. Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
KR102068980B1 (ko) * 2013-08-01 2020-01-22 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9214556B2 (en) * 2013-08-09 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned dual-metal silicide and germanide formation
US8999779B2 (en) * 2013-09-06 2015-04-07 International Business Machines Corporation Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
US9202918B2 (en) * 2013-09-18 2015-12-01 Globalfoundries Inc. Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
US9324790B2 (en) * 2013-11-19 2016-04-26 International Business Machines Corporation Self-aligned dual-height isolation for bulk FinFET
US9391077B2 (en) * 2014-02-10 2016-07-12 International Business Machines Corporation SiGe and Si FinFET structures and methods for making the same
US9871121B2 (en) * 2014-03-10 2018-01-16 Qualcomm Incorporated Semiconductor device having a gap defined therein
US9443769B2 (en) * 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030108B1 (en) * 2008-06-30 2011-10-04 Stc.Unm Epitaxial growth of in-plane nanowires and nanowire devices
CN102194755A (zh) * 2010-03-01 2011-09-21 台湾积体电路制造股份有限公司 鳍式场效晶体管及其制造方法

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