CN103972057A - Formation method for fine feature size graph of semiconductor - Google Patents

Formation method for fine feature size graph of semiconductor Download PDF

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Publication number
CN103972057A
CN103972057A CN201410228262.3A CN201410228262A CN103972057A CN 103972057 A CN103972057 A CN 103972057A CN 201410228262 A CN201410228262 A CN 201410228262A CN 103972057 A CN103972057 A CN 103972057A
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China
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layer
feature size
mask
pattern
forming
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CN201410228262.3A
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Chinese (zh)
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桑宁波
李润领
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上海华力微电子有限公司
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Priority to CN201410228262.3A priority Critical patent/CN103972057A/en
Publication of CN103972057A publication Critical patent/CN103972057A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask

Abstract

The invention provides a formation method for the fine feature size graph of a semiconductor. The formation method comprises the following steps: forming a mask layer on a semiconductor substrate; photoetching and etching the mask layer on the substrate to form a mask graph with a first feature size; depositing a layer of silicon nitride on the first graph as a conformal layer to cover the exposed substrate surface and the sidewall of the mask graph; depositing a filling layer on the basis of the silicon nitride conformal layer; levelling the filling layer and the silicon nitride conformal layer by chemical mechanical polishing until the top of the mask layer is exposed; selectively removing the mask layer and the filling layer, and only reserving the semiconductor substrate and the silicon nitride conformal layer; etching the substrate by using the silicon nitride conformal layer as an etching mask to form a mask graph with a second feature size which is less than the first feature size. The formation method provided by the invention is capable of breaking through the physical limits of photoetching to obtain a graph with a smaller size.

Description

一种半导体精细特征尺寸图形的形成方法 A method for forming a semiconductor fine feature size pattern

技术领域 FIELD

[0001] 本发明涉及半导体制造领域,更具体地说,本发明涉及一种半导体精细特征尺寸图形的形成方法。 [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly, the present invention relates to a method for forming a semiconductor fine feature size pattern.

背景技术 Background technique

[0002] 在半导体集成电路中,半导体工艺的特征尺寸在不断缩小,超大规模集成电路的特征尺寸按照摩尔定律的发展,已经发展到20纳米及以下的特征尺寸,以便在更小面积上增加半导体器件的容量并降低成本,形成具有更好的性能,更低的功耗的半导体器件。 [0002] In the semiconductor integrated circuit, the feature sizes in semiconductor process shrinking feature sizes of VLSI in accordance with Moore's Law, it has been developed to below 20 nm and feature size, so as to increase a smaller area on a semiconductor capacity of the device and reduce the cost, a semiconductor device having improved performance, lower power consumption. 每个器件的特征尺寸的收缩需要更复杂的技术。 Each device feature sizes shrink requires more sophisticated techniques.

[0003] 光刻法是常用的将器件及电路图案转移到衬底上的方法,线的宽度和间距是光刻工艺中最为关键的两个参数。 [0003] Photolithography is commonly used in the device and the circuit pattern is transferred onto a substrate, line width and spacing of the lithography process is the two most critical parameters. 间距被定义为两个相邻线的相同点之间的距离。 Pitch defined as the distance between two adjacent lines of the same points. 由于各种因素,如光学和光的波长等物理限制,现有的光刻技术具有最小间距在20纳米以下已不能满足集成电路的需求,低于该特定光刻技术极限的特征尺寸的图形已不能通过现有的光刻技术形成。 Feature size due to various factors, such as the optical and physical limitations of wavelength or the like, having a conventional photolithography technique can not meet the minimum pitch IC 20 nm, below which a particular photolithographic technique can not limit pattern formed by conventional photolithographic techniques.

[0004] 因此,本领域技术人员急需提供一种利用现有光刻技术同时又能满足特征尺寸需求的方法。 [0004] Thus, those skilled in the art an urgent need to provide a method using a prior art lithographic feature size while meeting the demand.

发明内容 SUMMARY

[0005] 本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种能够利用现有光刻技术同时又能满足特征尺寸需求的方法。 [0005] The present invention solves the technical problem is directed to a method which makes use of prior art lithographic feature size requirements while meeting the above-mentioned drawbacks present in the prior art, provided.

[0006] 本发明提供的一种半导体精细特征尺寸图形的形成方法,其特征在于,包括: [0006] A method for forming a semiconductor fine feature size pattern of the present invention provides, characterized by comprising:

[0007] 步骤SOl:在半导体衬底上形成掩模层; [0007] Step SOl: forming a mask layer on a semiconductor substrate;

[0008] 步骤S02:对衬底上的掩模层进行光刻并刻蚀,以形成具有第一特征尺寸的掩模图形; [0008] Step S02: mask layer on the substrate is subjected to photolithography and etching to form a mask pattern having a first feature size;

[0009] 步骤S03:在第一图形上沉积一层氮化娃作为共形层,覆盖暴露出来的衬底表面以及掩模图形的侧墙; [0009] Step S03: depositing a layer of nitride on the first pattern as a baby conformal layer covering the exposed surface of the substrate and the sidewall of the mask pattern;

[0010] 步骤S04:在所述氮化硅共形层的基础上沉积填充层; [0010] Step S04: depositing a layer of filling on the basis of the conformal silicon nitride layer;

[0011] 步骤S05:通过化学机械研磨对填充层及氮化硅共形层进行平坦化,直至暴露出掩模层的顶部; [0011] Step S05: by chemical mechanical polishing of the filling layer and the conformal layer of silicon nitride is planarized until the top of the mask layer is exposed;

[0012] 步骤S06:选择性的去除掩模层以及填充层,仅留下半导体衬底以及氮化硅共形层; [0012] Step S06: selective removal of the mask layer and a filling layer, leaving only the semiconductor substrate and a silicon nitride conformal layer;

[0013] 步骤S07:利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成具有小于第一特征尺寸的第二特征尺寸的掩模图形。 [0013] Step S07: using the silicon nitride conformal layer as an etch mask for etching the substrate, forming a mask pattern having a second size smaller than the first feature of the feature size.

[0014] 优选的,所述步骤SOl中,所述掩模层的材料包括氮化硅、多晶硅、二氧化硅其中的一种。 [0014] Preferably, the step SOl, the material of the mask layer include silicon nitride, polysilicon, silicon dioxide one of them.

[0015] 优选的,在所述掩膜层的基础上形成非晶碳薄膜层,且所述非晶碳薄膜层的厚度为半导体衬底厚度的1.5-2倍。 [0015] Preferably, the thin film layer forming an amorphous carbon layer on the basis of the mask, and the thickness of the amorphous carbon thin film layer is 1.5-2 times the thickness of the semiconductor substrate.

[0016] 优选的,所述步骤S03中,所述掩模图形侧壁上的氮化硅的厚度和掩模图形顶部的氮化硅厚度比大于90 %。 [0016] Preferably, the step S03, the thickness of the silicon nitride on top of the silicon nitride mask pattern and the mask pattern sidewall thickness ratio of greater than 90%.

[0017] 优选的,所述步骤S03中,通过原子层沉积工艺沉积所述氮化硅共形层,其厚度为第一特征尺寸的50%〜150%。 [0017] Preferably, the step S03, by atomic layer deposition process for depositing a conformal silicon nitride layer having a thickness of 50% ~150% of the first feature size.

[0018] 优选的,所述步骤S04中,所述填充层为光刻胶、ODL、SOC其中的一种或几种的组合。 [0018] Preferably, the step S04, the photoresist layer is filled, ODL, or a combination of several of which SOC. ODL(光学介电层,Optical dielectric layer),SOC(旋涂碳,spin on carbon)是40纳米以下光刻工艺常用的填充层,特征是经过填充能够将衬底高低起伏的形貌平整化。 ODL (optical dielectric layer, Optical dielectric layer), SOC (spin-on carbon, spin on carbon) was 40 nm or less conventional photolithographic process fill layer, wherein the topography of the substrate can be filled through the undulating planarization.

[0019] 优选的,所述填充层通过旋涂-凝胶工艺形成。 [0019] Preferably, the filling layer is formed by spin-coating - gel formed.

[0020] 优选的,所述步骤S05中,首先对掩模图形进行终点探测。 [0020] Preferably, in the step S05, first, a mask pattern for endpoint detection.

[0021] 优选的,所述步骤S06中,通过氧气灰化工艺选择性的去除掩模层以及填充层。 [0021] Preferably, the step S06, the mask layer is removed and a filling layer is formed by a selective oxygen ashing process.

[0022] 优选的,第二特征尺寸为第一特征尺寸的一半。 [0022] Preferably, the second half of the first feature size of feature size.

[0023] 与现有技术相比,通过采用本发明提供的一种半导体精细特征尺寸图形的形成方法可以将光刻的物理限制打破,得到更小尺寸的图形。 [0023] Compared with the prior art, can be broken by the physical limitations of the lithographic method for forming a semiconductor fine feature size pattern of the present invention provides, to give smaller size pattern.

附图说明 BRIEF DESCRIPTION

[0024] 为了更清楚地说明本发明实施例中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍;显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings are briefly introduced as required for use in the embodiments describing the embodiments; Apparently, the drawings in the following description are only some embodiments of the present invention. embodiment, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0025] 图1为本发明优选实施例的半导体精细特征尺寸图形的形成方法的流程图。 Flowchart of a semiconductor fine feature size pattern of embodiment [0025] FIG. 1 of the present invention is preferably formed.

[0026] 图2至图8为本发明优选实施例的半导体精细特征尺寸图形的形成方法的各个步骤。 [0026] Preferably 2 to 8 steps of the method of the semiconductor fine feature size pattern is formed according to the embodiment of the present invention.

具体实施方式 Detailed ways

[0027] 为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明的实施方式作进一步地详细描述。 [0027] To make the objectives, technical solutions, and advantages of the present invention will become apparent in conjunction with the following drawings, embodiments of the present invention will be described in further detail. 本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。 Those skilled in the art disclosed in this specification may readily understand the content of other advantages and effects of the present invention. 本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。 The present invention may also be implemented or applied through other different specific embodiments, the details of the specification may be carried out in various modified or changed without departing from the spirit of the invention based on various concepts and applications.

[0028] 上述及其它技术特征和有益效果,将结合实施例及附图1至图8对本发明的半导体精细特征尺寸图形的形成方法进行详细说明。 [0028] The above and other features and advantages of techniques, in conjunction with the accompanying drawings in Example 1 to 8 and a method of forming the semiconductor fine feature size pattern of the present invention will be described in detail embodiments. 图1为本发明优选实施例的半导体精细特征尺寸图形的形成方法的流程图。 Flowchart of a semiconductor fine feature size pattern of FIG. 1 of the present invention a preferred embodiment is formed. 图2至图8为本发明优选实施例的半导体精细特征尺寸图形的形成方法的各个步骤。 Steps of a method of the semiconductor fine feature size pattern is formed in the preferred embodiment of FIGS. 2 to 8 of the present invention.

[0029] 请参阅图1,在本实施例中,本发明提供的一种半导体精细特征尺寸图形的形成方法,包括: [0029] Referring to FIG. 1, in the present embodiment, a method for forming a semiconductor fine feature size pattern of the present invention provides, comprising:

[0030] 步骤SOl:在半导体衬底上形成掩模层(如图2所示)。 [0030] Step SOl: forming a mask layer (2) on a semiconductor substrate.

[0031] 其中,半导体衬底100的材料为单晶硅、氧化硅或非晶硅形成的硅材料,或是绝缘娃材料(Silicon on insulator,简称SOI),还可以是其它半导体材料或其它结构,在此不再赘述。 [0031] wherein the silicon material of the semiconductor substrate 100 made of monocrystalline silicon, silicon oxide or amorphous silicon, or an insulating material baby (Silicon on insulator, referred to as the SOI), also may be other semiconductor materials or other structure , not discussed here. 所述步骤SOl中,所述掩模层的材料包括氮化硅、多晶硅、二氧化硅其中的一种。 Said step SOl, the material of the mask layer include silicon nitride, polysilicon, silicon dioxide one of them. 优选的,所述掩膜层的基础上形成非晶碳薄膜层,且所述非晶碳薄膜层的厚度优选为半导体衬底厚度的1.5-2倍。 Preferably the base, the mask layer is formed on the amorphous carbon thin film layer and the amorphous carbon thin film layer has a thickness of preferably 1.5-2 times the thickness of the semiconductor substrate.

[0032] 步骤S02:对衬底上的掩模层进行光刻并刻蚀,以形成具有第一特征尺寸的掩模图形(如图3所示)。 [0032] Step S02: mask layer on the substrate is subjected to photolithography and etching to form a mask pattern having a first feature size (Figure 3).

[0033] 步骤S03:在第一图形上沉积一层氮化娃作为共形层,覆盖暴露出来的衬底表面以及掩模图形的侧墙(如图4所示)。 [0033] Step S03: depositing a layer of nitride on the first pattern as a baby conformal layer covering the exposed surface of the substrate, and the sidewall of the mask pattern (FIG. 4).

[0034] 其中,所述步骤S03中,优选通过原子层沉积工艺沉积所述氮化硅共形层,氮化硅共形层的厚度为第一特征尺寸的50%〜150%,进一步的,氮化硅共形层的厚度为第一特征尺寸的90%〜110%。 [0034] wherein, in the step S03, atomic layer deposition process, preferably by depositing a conformal layer of silicon nitride, silicon nitride conformal layer of a thickness of 50% ~150% of the first feature size, further, conformal layer of silicon nitride having a thickness of 90% ~110% of the first feature size. 所述掩模图形侧壁上的氮化硅的厚度和掩模图形顶部的氮化硅厚度比大于90%。 The mask pattern on the silicon nitride sidewall thickness of the top silicon nitride mask pattern and the thickness ratio of greater than 90%.

[0035] 步骤S04:在所述氮化硅共形层的基础上沉积填充层(如图5所示)。 [0035] Step S04: depositing a filling layer (5) on the basis of the conformal silicon nitride layer.

[0036] 其中,所述填充层为光刻胶、ODL、SOC其中的一种或几种的组合。 [0036] wherein, the photoresist layer is filled, ODL, a combination of one or more of the SOC therein. ODL(光学介电层,Optical dielectric layer),SOC (旋涂碳,spin on carbon)是40 纳米以下光刻工艺常用的填充层,特征是经过填充能够将衬底高低起伏的形貌平整化。 ODL (optical dielectric layer, Optical dielectric layer), SOC (spin-on carbon, spin on carbon) was 40 nm or less conventional photolithographic process fill layer, wherein the topography of the substrate can be filled through the undulating planarization. 优选的,填充层通过旋涂-凝胶工艺形成。 Preferably, the filling layer is formed by spin-coating - gel formed. 其中旋涂-凝胶(Spin-on PR Coating)方法包括静态涂胶(Static):娃片静止时,滴胶、加速旋转、甩胶、挥发溶剂;动态涂胶(Dynamic):娃片低速旋转、滴胶、加速旋转、甩胶、挥发溶剂。 Wherein spin coating - Gel (Spin-on PR Coating) comprising a static coating (Static): baby sheet when stationary, Epoxy, spin up, spin coater, a volatile solvent; adhesive dynamic (Dynamic): a low speed rotation baby , Epoxy, spin up, spin coater, a volatile solvent.

[0037] 步骤S05:通过化学机械研磨对填充层及氮化硅共形层进行平坦化,直至暴露出掩模层的顶部(如图6所示)。 [0037] Step S05: by chemical mechanical polishing of the filling layer and the conformal layer of silicon nitride is planarized until the top of the mask layer is exposed (as shown in Figure 6).

[0038] 其中,所述步骤S05中,首先对掩模图形进行终点探测,然后通过化学机械研磨对填充层及氮化硅共形层进行平坦化,直至暴露出掩模层的顶部,最终使得掩膜层、氮化硅共形层和填充层保持在一条水平线上。 [0038] wherein, in the step S05, first, a mask pattern for endpoint detection, and then planarized filling layer and the conformal layer of silicon nitride by chemical mechanical polishing until the top of the mask layer is exposed, such that the final the mask layer, a silicon nitride conformal layer and the filling layer held in a horizontal line.

[0039] 步骤S06:选择性的去除掩模层以及填充层,仅留下半导体衬底以及氮化硅共形层(如图7所示); [0039] Step S06: selective removal of the mask layer and a filling layer, leaving only the semiconductor substrate and a silicon nitride conformal layer (7);

[0040] 其中,通过灰化工艺选择性的去除掩模层以及填充层。 [0040] wherein, by selective ashing process for removing the mask layer and the filling layer. 优选的,通过氧气灰化工艺选择性的去除掩模层以及填充层。 Preferably, the mask layer is removed and a filling layer is formed by a selective oxygen ashing process.

[0041] 步骤S07:利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成具有小于第一特征尺寸的第二特征尺寸的掩模图形(如图8所示)。 [0041] Step S07: using the silicon nitride conformal layer as an etch mask for etching the substrate, forming a mask pattern having a second size smaller than the first feature of the feature size (Figure 8).

[0042] 优选的,第二特征尺寸为第一特征尺寸的一半。 [0042] Preferably, the second half of the first feature size of feature size.

[0043] 由此,本发明可以形成例如仅为第一特征尺寸一半的第二特征尺寸的图形。 [0043] Accordingly, the present invention can be, for example, only the first pattern feature size of the second half of the feature size formed. 通过采用本发明的上述方法可以将光刻的物理限制打破,得到更小尺寸的图形。 The physical limitations of the lithography can be broken by the above method of the present invention, to obtain a smaller size pattern.

[0044] 下面将具体描述根据本发明优选实施例的图形自对准形成方法的具体实施方式的示例。 [0044] The following embodiments will be described according to a preferred embodiment of the present invention is self-aligned pattern specific exemplary embodiment of forming method.

[0045] 实施例一 [0045] Example a

[0046] 本实施例提供的一种半导体精细特征尺寸图形的形成方法:首先在硅衬底上形成第一掩模层氮化硅,并在氮化硅上形成第二掩模层,第二掩模层为非晶碳薄膜层;采用光刻工艺形成具有第一特征尺寸的掩模图形;在掩模图形上覆盖一层氮化硅做为共形层;然后通过旋涂-凝胶法形成光刻胶作为填充层材料覆盖氮化硅共形层,并尽量的平坦;采用化学机械研磨的方法对填充层及氮化硅共形层进行研磨,探测到掩模层顶部时终止研磨;采用氧气灰化工艺去处掩模层和光刻胶填充层;利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成具有小于第一特征尺寸的第二特征尺寸的掩模图形形成浅沟槽。 The method of forming [0046] A semiconductor present a fine feature size pattern according to an embodiment of: firstly forming a first mask layer of silicon nitride on a silicon substrate, and forming a second mask layer on the silicon nitride, the second the mask layer is an amorphous carbon film layer; a mask pattern having a first feature size is formed using a photolithography process; covered with silicon nitride as a conformal layer on the mask pattern; followed by a spin coating - gel forming a photoresist layer as a filling material covering the conformal layer of silicon nitride, and flat as possible; chemical mechanical polishing method for a silicon nitride layer and the filling layer conformal polishing, polishing terminated upon detection of the top mask layer; ideas ashing process using oxygen and a photoresist mask layer filling layer; a conformal layer of silicon nitride as an etch mask for etching the substrate, forming a mask having a second size smaller than the first feature size of feature forming shallow trench pattern.

[0047] 本实施例中,掩模图形的宽度为30纳米,图形之间的间距为50纳米,氮化硅共形层覆盖在掩模图形顶部厚度与掩模图形侧壁厚度相等,均为15纳米,掩模图形侧壁之间填充层的厚度为20纳米;利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成浅沟槽,则衬底上图形的宽度为15纳米,图形与图形之间的间距为20纳米,最终形成具有小于第一特征尺寸的第二特征尺寸的掩模图形形成浅沟槽。 [0047] In this embodiment, the width of the mask pattern is 30 nm, the spacing between the pattern of 50 nm, a silicon nitride layer overlying the conformal mask pattern is equal to the thickness of the top of the sidewall thickness of the mask pattern, are 15 nm, the thickness of the filled layer between the mask pattern side wall 20 nanometers; conformal layer using the silicon nitride as an etch mask for etching the substrate, forming a shallow trench, the width of the substrate pattern is 15 nm, the distance between the pattern and the pattern of 20 nm, forming a second mask pattern having a characteristic dimension smaller than the first feature size of the shallow trench is formed.

[0048] 实施例二 [0048] Second Embodiment

[0049] 本实施例提供的一种半导体精细特征尺寸图形的形成方法:首先在硅衬底上形成第一掩模层二氧化娃栅介质层,形成多晶娃栅,并在多晶娃栅上形成第二掩模层,第二掩模层为非晶碳薄膜层;采用光刻工艺形成具有第一特征尺寸的掩模图形;在掩模图形上覆盖一层氮化硅做为共形层;然后通过旋涂-凝胶法形成光刻胶作为填充层材料覆盖氮化硅共形层,并尽量的平坦;采用化学机械研磨的方法对填充层及氮化硅共形层进行研磨,探测到掩模层顶部时终止研磨;采用氧气灰化工艺去处掩模层和光刻胶填充层;利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成具有小于第一特征尺寸的第二特征尺寸的掩模图形形成浅沟槽。 [0049] A method for forming a semiconductor fine feature size pattern provided in the present embodiment: firstly formed on a silicon substrate a first mask layer baby dioxide gate dielectric layer, to form a polycrystalline gate baby, and baby gate poly forming a second mask layer on the second mask layer is an amorphous carbon film layer; a mask pattern having a first feature size is formed using a photolithography process; covered with silicon nitride as a conformal mask pattern layer; - then by spin coating a photoresist layer as a filler material covering the conformal layer of silicon nitride, and try to form a flat-gel method; a method for chemical mechanical polishing of a silicon nitride layer and the filling is polished conformal layer, polishing terminated upon detection of a top mask layer; ideas ashing process using oxygen and a photoresist mask layer filling layer; a conformal layer of silicon nitride as an etch mask for etching the substrate to form less than a first the second mask pattern feature size characteristic dimension forming a shallow trench.

[0050] 此外,需要说明的是,除非特别说明或者指出,否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。 [0050] Further, it is noted that, unless otherwise stated or indicated otherwise, that the terms "first", "second", "third" and the like describe only used to distinguish the various components in the specification, elements, steps etc., rather than used to indicate the logical relationship between the various components, elements, steps or sequentially relationship.

[0051] 上述说明示出并描述了本发明的若干优选实施例,但如前所述,应当理解本发明并非局限于本文所披露的形式,不应看作是对其他实施例的排除,而可用于各种其他组合、修改和环境,并能够在本文所述发明构想范围内,通过上述教导或相关领域的技术或知识进行改动。 [0051] The above description of the embodiments shown and described several preferred embodiments of the present invention, as previously discussed, it should be understood that the invention is not limited to the form disclosed herein should not be considered as excluding other embodiments, the It may be used in various other combinations, modifications, and environments, and can be contemplated within the scope of the invention described herein, or make changes to the above teachings in skill or knowledge of the relevant art. 而本领域人员所进行的改动和变化不脱离本发明的精神和范围,则都应在本发明所附权利要求的保护范围内。 The modifications and variations carried out by the skilled person without departing from the spirit and scope of the invention shall fall within the scope of the appended claims of the invention.

Claims (10)

1.一种半导体精细特征尺寸图形的形成方法,其特征在于,包括: 步骤SOl:在半导体衬底上形成掩模层; 步骤S02:对衬底上的掩模层进行光刻并刻蚀,以形成具有第一特征尺寸的掩模图形; 步骤S03:在第一图形上沉积一层氮化硅作为共形层,覆盖暴露出来的衬底表面以及掩模图形的侧墙; 步骤S04:在所述氮化硅共形层的基础上沉积填充层; 步骤S05:通过化学机械研磨对填充层及氮化硅共形层进行平坦化,直至暴露出掩模层的顶部; 步骤S06:选择性的去除掩模层以及填充层,仅留下半导体衬底以及氮化硅共形层; 步骤S07:利用氮化硅共形层作为刻蚀掩模对衬底进行刻蚀,形成具有小于第一特征尺寸的第二特征尺寸的掩模图形。 1. A method for forming a semiconductor fine feature size pattern, characterized by comprising: a step SOl: forming a mask layer on a semiconductor substrate; Step S02 is: mask layer on the substrate is subjected to photolithography and etching, to form a mask pattern having a first feature size; step S03: depositing a layer of silicon nitride as a conformal layer overlying the substrate surface of the spacer and the mask pattern is exposed in a first pattern; step S04: in the base layer of silicon nitride is deposited to fill the conformal layer; step S05: by chemical mechanical polishing of the filling layer and the conformal layer of silicon nitride is planarized until the top of the mask layer is exposed; step S06: selective removing the mask layer and a filling layer, leaving only the semiconductor substrate and a silicon nitride conformal layer; step S07: using the silicon nitride conformal layer as an etch mask for etching the substrate to form less than a first the second mask pattern feature size characteristic dimension.
2.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤SOl中,所述掩模层的材料包括氮化娃、多晶娃、二氧化娃其中的一种。 2. The method of forming a fine feature size pattern of a semiconductor according to claim 1, wherein said step SOl, the material of the mask layer comprises a baby nitride, polycrystalline baby, baby dioxide which species.
3.根据权利要求2所述的半导体精细特征尺寸图形的形成方法,其特征在于,在所述掩膜层的基础上形成非晶碳薄膜层,且所述非晶碳薄膜层的厚度为半导体衬底厚度的1.5〜2倍。 3. The method of forming a fine feature size pattern of a semiconductor according to claim 2, wherein forming an amorphous carbon thin film layer on the basis of the mask layer, and the thickness of the amorphous carbon thin film layer is a semiconductor 1.5~2 times the thickness of the substrate.
4.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S03中,所述掩模图形侧壁上的氮化硅的厚度和掩模图形顶部的氮化硅厚度比大于90%。 4. The method of forming a fine feature size pattern of a semiconductor according to claim 1, wherein, in the step S03, and the thickness of the nitride mask on top of the silicon nitride sidewall mask pattern pattern Si thickness ratio of greater than 90%.
5.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S03中,通过原子层沉积工艺沉积所述氮化硅共形层,其厚度为第一特征尺寸的50 %〜150%。 5. The method of forming a fine feature size pattern of a semiconductor according to claim 1, wherein, in the step S03, the conformal layer of silicon nitride by atomic layer deposition process, wherein a thickness of a first dimension 50% ~ 150%.
6.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S04中,所述填充层为光刻胶、ODL、SOC其中的一种或几种的组合。 6. The method for forming a semiconductor fine feature size pattern as claimed in claim wherein, in said step S04, the photoresist layer is filled, ODL, or a combination of several of which SOC.
7.根据权利要求6所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述填充层通过旋涂-凝胶工艺形成。 7. The method for forming a fine feature size pattern of a semiconductor according to claim 6, characterized in that the filling layer is formed by spin-coating - gel formed.
8.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S05中,首先对掩模图形进行终点探测。 8. A method of forming a fine feature size pattern of a semiconductor according to claim 1, wherein, in the step S05, first, a mask pattern for endpoint detection.
9.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S06中,通过灰化工艺选择性的去除掩模层以及填充层。 9. A method of forming a fine feature size pattern of a semiconductor according to claim 1, characterized in that, in S06, by selective ashing process for removing the mask layer and the filling layer step.
10.根据权利要求1所述的半导体精细特征尺寸图形的形成方法,其特征在于,所述步骤S07中,第二特征尺寸为第一特征尺寸的一半。 10. A method of forming a fine feature size pattern of a semiconductor according to claim 1, wherein said step S07, the second half of the first feature size of feature size.
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