CN103944382B - Eliminate the current-mode control method in Buck code converter electric current dead band - Google Patents

Abstract

The present invention relates to field of power management and IC design field, on the basis of realizing retaining the Buck type intrinsic advantage of topology, eliminate its electric current dead band, and then making the performance of integrated circuit be increased dramatically, the present invention adopts the technical scheme that, eliminates the current-mode control method in Buck code converter electric current dead band, on the basis of Buck code converter, increasing a switching tube at output node, be referred to as time switch Q2, original switch is referred to as master switch Q1；The effect of Q2 is by outfan short circuit in the input voltage time range less than output voltage, so that continuous current mode change, particularly as follows: circuit AC input connects the rectifier bridge being made up of four diodes, a partial-pressure structure being made up of two resistant series in parallel after rectifier bridge.Present invention is mainly applied to power management and IC design.

Description

Current mode control method for eliminating current dead zone of Buck converter

Technical Field

The invention relates to the field of power management and the field of integrated circuit design, in particular to the research of a power factor correction circuit and the design modeling of a controller thereof. And more particularly, to a current mode control apparatus for eliminating a current dead zone of a Buck converter.

Technical Field

Currently, the power supply industry sets a set of standards for energy and environmental considerations. For example: the IEC91000-3-2 standard is used to limit harmonic currents; the european union guidelines (CoC) specify the average efficiency of an external power supply at 25%, 50%, 75%, and 100% full load conditions, respectively. Power Factor Converters (PFCs) are beneficial for improving the overall performance of switching power supply circuits. Therefore, it is necessary to apply power factor correction techniques to current correction in alternating current/direct current (AC/DC) converters.

Currently, Boost (Boost) type PFCs are the most popular and most widely used technologies, but maintaining relatively high efficiency over the entire load range remains a challenge. On the one hand, Boost converters are typically 1% to 3% less efficient at low input voltages than at high input voltages, and the reduction in efficiency results in an increase in input current, which increases the losses of the switches and diodes. On the other hand, the high output voltage of the Boost type converter not only causes an increase in the switching tube loss of itself, but also causes an increase in the switching loss of the subsequent-stage direct current (DC/DC) converter and an increase in electromagnetic interference.

For Buck-Boost (Buck-Boost) topologies, i.e., flyback, SEPIC, and C' uk converters, although they can be used as Buck-type converters, in particular SEPIC converters can achieve higher power factor and reduce output voltage, the voltage stress of the switches is greatly increased. In addition to this, the structural complication leads to a reduction in efficiency and an increase in cost.

In contrast, Buck (Buck) type converters have many attractive advantages. First, a Buck topology can be used to achieve high efficiency over the entire input voltage range. In addition, the Buck converter switch has low voltage stress. However, since the Buck topology has zero current in the time when the input voltage is lower than the output voltage, the topology cannot always obtain a high power factor as a PFC converter. In addition, this current dead zone can also increase total harmonic crosstalk (THD).

Conventional Buck-type topologies have been used rarely in AC-DC converters, despite the many advantages they do, due to the fact that the switching tubes are non-conducting under conditions where the input voltage is less than the output voltage. Moreover, the number of the corresponding control chips is one corner of the iceberg compared with the number of Boost type topology control chips. Therefore, the Buck converter and the research on the control chip thereof with high practicability have high values.

Disclosure of Invention

In order to overcome the defects of the prior art, the current dead zone is eliminated on the basis of keeping the inherent advantages of the Buck topology, and the performance of the whole circuit is greatly improved. Therefore, the invention adopts the technical scheme that a current mode control method for eliminating the current dead zone of the Buck-type converter is characterized in that on the basis of the Buck-type converter, a switch tube is added at an output node and is called as a secondary switch Q2, and an original switch is called as a main switch Q1; q2 functions to short circuit the output terminal in the time range when the input voltage is lower than the output voltage, so that the inductor current continuously changes, specifically: the alternating current input end of the circuit is connected with a rectifier bridge consisting of four diodes, and a voltage division structure consisting of two resistors connected in series is connected behind the rectifier bridge in parallel. The AC input power passes through the rectifier bridge and is connected in parallel with a filter capacitor. The positive output end of the rectifier bridge is connected to the cathode of a diode, the negative output end of the rectifier bridge is connected with a switch Q1 through a current detection resistor, the other end of the Q1 is connected with the anode of the diode and one end of a step-down inductor, and the switch Q2 and an output capacitor are connected between the other end of the step-down inductor and the cathode of the diode in parallel. The output load is connected with a differential voltage division structure in parallel: two resistors are connected in parallel at the output end after being connected in series, the middle node of the two resistors is connected to the base electrode of a P-type triode, the high-level end of the series resistor is connected to the emitting electrode of the triode after passing through one resistor, the collecting electrode of the triode is connected to the ground after passing through one resistor, and the node between the collecting electrode and the resistor is used as a feedback signal of output voltage.

1) When the input voltage is lower than the output voltage, the converter is equivalent to a conventional Buck-Boost type circuit, and then Q1 and Q2 are synchronously switched on and off;

a) when both switches are on simultaneously, the supply voltage V_inThe inductor is charged, and the inductor current is linearly increased;

b) when the two switches are simultaneously switched off, the inductor discharges to the load, and the current of the inductor is linearly reduced;

2) when the input voltage is higher than the output voltage, the converter is equivalent to a conventional Buck-type circuit, when Q2 is off;

a) when Q1 is conducted, the inductance is changed from V_in-V_oCharging, the inductive current linearly increasing under the action of this voltage;

b) when Q1 is turned off, the inductor discharges into the load and the inductor current decreases linearly.

For input voltage V_inThe voltage is divided by a series resistor to obtain MULT, and the output voltage is divided by the same proportion as the input voltage to obtain FB; MULT and FB as the positive input signal and the negative input signal of the comparator Comp1, respectively, are compared to obtain V_pWhen V is_in>V_oWhen, V_pIs at a high level; when V is_in<V_oWhen, V_pIs low level; v thus obtained_pFor determining the closed and open states of the two switches;

obtaining a voltage feedback signal INV from the output voltage through a differential voltage dividing structure, connecting INV to the inverting input terminal of the error amplifier EA, and obtaining a reference voltage V_refConnected to the non-inverting input of the error amplifier, error of both signalsThe difference signal is amplified by the error amplifier and then is used as an input signal of the multiplier; the other input signal of the multiplier is MULT; the output of the multiplier is used as the reference signal of the current comparator Comp2, the other input signal of the current comparator is the CS current detection signal, and the CS current detection signal is taken from the node between the current detection resistor and Q1; the current comparator outputs to the set end of the RS trigger to control the peak current of each period of Q1; one end of the coupling inductor of the step-down inductor is grounded, and the other end of the coupling inductor is connected to the negative input terminal of the comparator Comp3 through a resistor, the positive input terminal of the comparator is connected to ground through a capacitor, and the output terminal is connected to the reset terminal of the RS flip-flop. When the voltage across the inductor reverses, control turns on the external Q1. Thereby operating the circuit in a current critical mode;

the output of the RS trigger and the inverted output of the comparator Comp1 pass through an AND gate and then control a secondary switch Q2, so that the circuit works in a current critical mode; guarantee V_in>V_oWhen the circuit is in use, Q2 is disconnected, and Q1 is controlled by the chip to act; v_in<V_oQ1 and Q2 are simultaneously activated by the chip control.

The invention has the technical characteristics and effects that:

the invention has the key point that the output end is short-circuited by using the secondary switch in the dead zone part of the Buck converter, so that the switching voltage cannot be reversed, and a current dead zone cannot be generated. This stage is equivalent to a conventional Buck-Boost type converter. In addition, the control chip adopts double closed-loop control, and the circuit performance is improved compared with a voltage control mode. The corrected input current waveform is shown in fig. 4, and it can be seen that the input current waveform is corrected, and the signal envelope is a sine wave with the same frequency and phase as the input voltage. Therefore, the power factor of the improved Buck converter adopting the invention is greatly improved.

Drawings

FIG. 1: the invention discloses a Buck type converter circuit structure schematic diagram;

FIG. 2: a working phase schematic diagram;

FIG. 3: a schematic diagram of the inside of the control chip;

FIG. 4: the invention discloses a Buck type converter input voltage and current oscillogram;

FIG. 5: the circuit is compared with the power factor of the traditional Buck type converter;

FIG. 6: the converter corrects the input current waveform.

Detailed Description

The invention applies a composite structure for eliminating the dead zone of a Buck type circuit, namely, the circuit is converted into a Buck-Boost structure through an additional switch in the current dead zone time. This new architecture, while making the circuit more complex, greatly improves the performance of the Buck topology by introducing dead-time currents. The circuit disclosed by the invention aims to eliminate the current dead zone on the basis of keeping the inherent advantages of the Buck topology, so that the performance of the whole circuit is greatly improved.

The circuit described in the invention is based on the traditional Buck type converter, and a switching tube is added at an output node, which is called as a secondary switch Q2, and the original switch is called as a main switch Q1. The Q2 functions to short circuit the output terminal in the time range in which the input voltage is lower than the output voltage, thereby causing the inductor current to vary continuously, as shown in fig. 1. The concrete structure is as follows: the alternating current input end of the circuit is connected with a rectifier bridge consisting of four diodes, and a voltage division structure consisting of two resistors connected in series is connected behind the rectifier bridge in parallel. The AC input power is connected in parallel with a filter capacitor after passing through the rectifier bridge. The positive output end of the rectifier bridge is connected to the cathode of a diode, the negative output end of the rectifier bridge is connected with a switch Q1 through a current detection resistor, the other end of the Q1 is connected with the anode of the diode and one end of a step-down inductor, and the switch Q2 and an output capacitor are connected between the other end of the step-down inductor and the cathode of the diode in parallel. The output load is connected with a differential voltage division structure in parallel: two resistors are connected in parallel at the output end after being connected in series, the middle node of the two resistors is connected to the base electrode of a P-type triode, the high-level end of the series resistor is connected to the emitting electrode of the triode after passing through one resistor, the collecting electrode of the triode is connected to the ground after passing through one resistor, and the node between the collecting electrode and the resistor is used as a feedback signal of output voltage.

The converter is equivalent to a conventional buck-boost converter in the current dead time range. Therefore, by supplementing the inductor current in the dead time, the defect that the input current of the conventional Buck converter is zero outside the conduction angle can be overcome.

The circuit of the invention works as follows, as shown in fig. 2:

1) when the input voltage is lower than the output voltage, the converter is equivalent to a conventional Buck-Boost type circuit, and then Q1 and Q2 are synchronously switched on and off;

a) when both switches are on simultaneously, the supply voltage V_inCharging the inductor, the inductor current increases linearly, as shown by the path indicated by the bold line in fig. 2 (a);

b) when both switches are open at the same time, the inductor discharges into the load and the inductor current decreases linearly, as indicated by the thick line in fig. 2 (b).

2) When the input voltage is higher than the output voltage, the converter is equivalent to a conventional Buck type circuit, and Q2 is switched off, and Q1 is determined by a current comparator and a zero current detection unit in a chip.

a) When Q1 is conducted, the inductance is changed from V_in-V_oCharging, the inductor current linearly increases under the action of this voltage, as shown by the path indicated by the bold line in fig. 2 (c);

b) when Q1 is turned off, the inductor discharges into the load and the inductor current decreases linearly, as indicated by the thick line in fig. 2 (d).

Based on the above analysis, the control chip can realize the above functions by adding a voltage comparator on the basis of the basic PFC control chip, and the structure is as shown in fig. 3, and the principle is as follows:

input voltage V_inThe voltage is divided by the series resistors to obtain MULT, and the output voltage is divided by the same proportion as the input voltage to obtain FB. MULT and FB are respectively the positive input signal and the negative input signal of the comparator Comp1, and these two level signals are compared to obtain V_pWhen V is_in>V_oWhen, V_pIs at a high level; when V is_in<V_oWhen, V_pIs low. V thus obtained_pFor determining the closed and open state of both switches.

The output voltage is subjected to a differential voltage division structure to obtain a voltage feedback signal INV, the INV is connected to the inverting input end of the error amplifier EA, and the reference voltage V_refThe error amplifier is connected to the non-inverting input end of the error amplifier, and the error signal of the two signals is amplified by the error amplifier to be used as an input signal of the multiplier. The other input signal to the multiplier is MULT and therefore the envelope of the waveform of the output of the multiplier is a sine wave. The output of the multiplier is used as the reference signal of the current comparator Comp2, and the other input signal of the current comparator is the CS current detection signal. The CS current sense signal is taken from the node between the current sense resistor and Q1. The current comparator outputs to the set terminal of the RS flip-flop, which controls the peak current of each period of Q1. One end of the coupling inductor of the step-down inductor is grounded, and the other end of the coupling inductor is connected to the negative input terminal of the comparator Comp3 through a resistor, the positive input terminal of the comparator is connected to ground through a capacitor, and the output terminal is connected to the reset terminal of the RS flip-flop. When the voltage across the inductor reverses, control turns on the external Q1. Thereby causing the circuit to operate in a current critical mode.

The output of the RS flip-flop and the inverted output of the comparator Comp1 pass through an and gate and then control the secondary switch Q2, so that the circuit operates in the current critical mode. Guarantee V_in>V_oWhen the circuit is in use, Q2 is disconnected, and Q1 is controlled by the chip to act; v_in<V_oQ1 and Q2 are simultaneously activated by the chip control. The chip structure is shown in fig. 3.

The invention has obvious effect on improving the power factor of the Buck converter and can be flexibly applied to various output voltage occasions.

Take a Buck converter with an input of 220V (50 Hz) and an output of 80V as an example.

The input voltage and current waveforms of the conventional Buck converter are first analyzed. Average current i of input current in one switching period_iThe average current in BCM mode is:

$i_i=\frac{1}{2}{i}_{\mathrm{pk}}=\frac{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_0}{L}\&CenterDot;t_{\mathrm{on}}\&CenterDot;D;$

wherein, V_inIs an effective value of the input voltage, V_oTo output a DC voltage i_pkFor input current peak, t_onD is the duty cycle for the on time.

Let the input power be p_iOutput power of p_oThen, then

$P_i={\&Integral;}_{t_1}^{0.005}\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)}\&CenterDot;\frac{(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o)\&CenterDot;V_{\mathrm{in}}(100\mathrm{\&pi;}\&CenterDot;t)\&CenterDot;t_{\mathrm{on}}}{\mathrm{\&pi;}\&CenterDot;L}\mathrm{dt};$

Wherein, t₁And t₂As shown in fig. 4, the output voltage and the input voltage are equal to each other. The following can be obtained:

$t_1=\frac{1}{100\mathrm{\&pi;}}\arcsin \frac{V_o}{V_{\mathrm{in}}};t_2=0.01-t_1;$

effective value i of input current_rmsComprises the following steps:

$i_{\mathrm{rms}}=\sqrt{\frac{1}{\mathrm{\&pi;}}{\&Integral;}_{{\mathrm{\&omega;t}}_1{i_i}^{2}d\left(\mathrm{\&omega;t}\right)}^{{\mathrm{\&omega;t}}_2}}=\sqrt{\frac{2}{\mathrm{\&pi;}}{\&Integral;}_{100{\mathrm{\&pi;t}}_1}^{0.005}{(\frac{(V_{\mathrm{in}}\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o)\&CenterDot;t_{\mathrm{on}}}{2\&CenterDot;L}\&CenterDot;\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)})}^2\mathrm{dt}}$

according to the above formula, the power factor PF can be expressed as:

$\mathrm{PF}=\frac{p_i}{V_{\mathrm{in}}\&CenterDot;i_{\mathrm{rms}}}.$

according to the design indexes, the power factor SIMPLIS simulation result of the Buck-type converter is as follows:

PF=0.83

the input voltage and current waveforms of the Buck converter of the present invention are analyzed. The average current in BCM mode and in DCM mode are:

$i_{\mathrm{in}}=\left\{\begin{array}{c}{D}_{\mathrm{BUCK}}\&CenterDot;\frac{i_{\mathrm{pk},\mathrm{BUCK}}}{2},t_1<t<t_2\\ D_{\mathrm{BUCK}-\mathrm{BOOST}}\&CenterDot;\frac{i_{\mathrm{pk},\mathrm{BUCK}-\mathrm{BOOST}}}{2},0<t<t_1,t_2<t<0.01\end{array}\right.;$

wherein, $D_{\mathrm{BUCK}}=\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)};D_{\mathrm{BUCK}-\mathrm{BOOST}}=\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)+V_o}$ the duty ratio of the switching signal in the dead time and the duty ratio of the switching signal in the conduction time are respectively;

$i_{\mathrm{pk},\mathrm{BUCK}}=\frac{(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o)\&CenterDot;t_{\mathrm{on}}}{L};i_{\mathrm{pk},\mathrm{BUCK}-\mathrm{BOOST}}=\frac{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)\&CenterDot;k\&CenterDot;t_{\mathrm{on}}}{L}$ the peak currents in the two modes are respectively, and k is the coefficient relation of the conduction time in the two modes. The rewrite input current expression is as follows:

$i_{\mathrm{in}}=\left\{\begin{array}{c}\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)}\&CenterDot;\frac{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o}{2\&CenterDot;L}\&CenterDot;t_{\mathrm{on}},t_1<t<t_2\\ \frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)+V_o}\&CenterDot;\frac{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)}{2\&CenterDot;L}\&CenterDot;k\&CenterDot;t_{\mathrm{on}},0<t<t_1,t_2<t<0.01\end{array}\right.;$

wherein, according to the conservation of energy, the following relationship exists:

$({\&Integral;}_0^{t_1}\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)+V_o}\&CenterDot;\frac{{(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t))}^2\&CenterDot;k\&CenterDot;t_{\mathrm{on}}}{2\&CenterDot;L}\mathrm{dt}+{\&Integral;}_{t_1}^{0.005}\frac{V_o\&CenterDot;(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o)\&CenterDot;t_{\mathrm{on}}}{2\&CenterDot;L}\mathrm{dt})\&CenterDot;\mathrm{\&eta;}=0.005P_o;$

where η is the converter efficiency so t_onThe expression of (a) is:

$t_{\mathrm{on}}=\frac{\frac{0.01P_o}{\mathrm{\&eta;}}}{k\&CenterDot;{\&Integral;}_0^{t_1}\frac{V_o}{V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)+V_o}\&CenterDot;\frac{{(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t))}^2}{L}\mathrm{dt}+{\&Integral;}_{t_1}^{0.005}\frac{V_o\&CenterDot;(V_{\mathrm{in}}\&CenterDot;\sin (100\mathrm{\&pi;}\&CenterDot;t)-V_o)\&CenterDot;V_{\mathrm{in}}}{L}\mathrm{dt}};$

the input voltage is 220V (50 Hz), the output voltage is 80V, and the output power is 70W. The circuit performance is simulated by using simple under the condition, and the results are as follows:

power factor PF =98.11%

On the basis, comparing the power factor of the circuit under other input voltages with the improved conventional Buck-type converter, as shown in FIG. 5, it can be seen that the circuit of the invention can obtain very high power factor in a wide input voltage range, and basically more than 98%. The efficiency of the power supply is approximately the same as compared to the efficiency of a conventional Buck-type circuit. The circuit obtains higher power factor under the condition of keeping the advantage that the traditional Buck type converter obtains higher efficiency under the condition of low input voltage.

It can be seen that the power factor of the Buck converter adopting the strategy is greatly improved. In addition, compared with other methods, the method for controlling the dead zone current by adopting the pulse has the characteristics of simplicity, feasibility and more stable circuit, and the waveform of the corrected input current is as shown in fig. 6.

Claims (2)

1. A current mode control method for eliminating a current dead zone of a Buck type converter is characterized in that on the basis of the Buck type converter, a switch tube called a secondary switch Q2 is added at an output node, and an original switch called a main switch Q1; the secondary switch Q2 is used to short-circuit the output terminal in the time range when the input voltage is lower than the output voltage, so that the buck inductor current continuously changes, specifically: the alternating current input end of the circuit is connected with a rectifier bridge consisting of four diodes, and a voltage division structure consisting of two resistors connected in series is connected behind the rectifier bridge in parallel; an alternating current input power supply is connected in parallel with a filter capacitor after passing through a rectifier bridge; the positive output end of the rectifier bridge is connected to the cathode of a diode, the negative output end of the rectifier bridge is connected with a main switch Q1 through a current detection resistor, the other end of the main switch Q1 is connected with the anode of the diode and one end of a step-down inductor, and a secondary switch Q2 and an output capacitor are connected between the other end of the step-down inductor and the cathode of the diode in parallel; the output load is connected with a differential voltage division structure in parallel: the two resistors are connected in parallel at the output end after being connected in series, the middle node of the two resistors is connected to the base electrode of a P-type triode, the high-level end of the series resistor is connected to the emitting electrode of the P-type triode after passing through one resistor, the collector electrode of the P-type triode is connected to the ground after passing through one resistor, and the node between the collector electrode and the resistor is used as a feedback signal of output voltage; wherein:

1) when the input voltage is lower than the output voltage, the converter is equivalent to a traditional Buck-Boost type circuit, and the main switch Q1 and the secondary switch Q2 are synchronously switched on and off;

a) when the two switches are turned on simultaneously, the input voltage V_inCharging the voltage reduction inductor, and linearly increasing the current of the voltage reduction inductor;

b) when the two switches are simultaneously switched off, the voltage reduction inductor discharges electricity to the load, and the current of the voltage reduction inductor is linearly reduced;

2) when the input voltage is higher than the output voltage, the converter is equivalent to a conventional Buck-type circuit, and the secondary switch Q2 is turned off;

a) when the main switch Q1 is turned on, the step-down inductor is turned off from V_in-V_oThe charging and voltage-reducing inductance current linearly increases under the action of the voltage, V_oTo output a direct current voltage;

b) when the main switch Q1 is turned off, the buck inductor discharges to the load and the buck inductor current decreases linearly.

2. The current mode control method for eliminating the current dead zone of the Buck-type converter as claimed in claim 1, wherein the current mode control method is applied to an input voltage V_inThe voltage is divided by a series resistor to obtain MULT, and the output voltage is divided by the same proportion as the input voltage to obtain FB; MULT and FB as the positive input signal and the negative input signal of the comparator Comp1, respectivelyComparing the signals to obtain V_pWhen V is_in＞V_oWhen, V_pIs at a high level; when V is_in＜V_oWhen, V_pIs low level; v thus obtained_pFor determining the closed and open state of two switches, V_oTo output a direct current voltage;

obtaining a voltage feedback signal INV from the output voltage through a differential voltage dividing structure, connecting INV to the inverting input end of the error amplifier, and obtaining a reference voltage V_refThe error signal of the two signals is amplified by the error amplifier and then is used as an input signal of the multiplier; the other input signal of the multiplier is MULT; the output of the multiplier is used as a reference signal of a current comparator, and the other input signal of the current comparator is a CS current detection signal which is taken from a node between a current detection resistor and a main switch Q1; the current comparator outputs to the set end of the RS trigger to control the peak current of the main switch Q1 in each period; one end of the coupling inductor of the voltage reduction inductor is grounded, the other end of the coupling inductor is connected to the negative input end of a comparator Comp3 through a resistor, the positive input end of a comparator Comp3 is connected to the ground through a capacitor, and the output end of the coupling inductor is connected to the reset end of the RS trigger; when the voltage passing through the voltage reduction inductor is reversed, the external main switch Q1 is controlled to be turned on, so that the circuit works in a current critical mode;

the output of the RS trigger and the inverted output of the comparator Comp1 pass through an AND gate and then control a secondary switch Q2, so that the circuit works in a current critical mode; guarantee V_in＞V_oWhen the switch is turned off, the secondary switch Q2 is turned off, and the main switch Q1 is controlled by the chip to act; v_in＜V_oThe main switch Q1 and the sub switch Q2 are controlled by the chip to operate simultaneously.