CN103887310B - Non-volatility memory and preparation method thereof - Google Patents
Non-volatility memory and preparation method thereof Download PDFInfo
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- CN103887310B CN103887310B CN201210555545.XA CN201210555545A CN103887310B CN 103887310 B CN103887310 B CN 103887310B CN 201210555545 A CN201210555545 A CN 201210555545A CN 103887310 B CN103887310 B CN 103887310B
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Abstract
The invention relates to a kind of non-volatility memory and preparation method thereof. This non-volatility memory comprises grid structure, doped region, electric charge storage layer and the first dielectric layer. Grid structure is disposed in substrate. In the substrate of grid structure two sides, there is depression. Grid structure comprises gate dielectric layer and grid. Gate dielectric layer is disposed in substrate, and has interface between gate dielectric layer and substrate. Gate configuration is on gate dielectric layer. Doped region is disposed in depression substrate around. Electric charge storage layer is disposed in depression, and the end face of electric charge storage layer is higher than above-mentioned interface. The first dielectric layer is disposed between electric charge storage layer and substrate and between electric charge storage layer and grid structure.
Description
Technical field
The present invention relates to a kind of non-volatility memory and preparation method thereof, particularly relate to one and can avoid secondNon-volatility memory of unit's effect (secondbiteffect) and preparation method thereof.
Background technology
Non-volatility memory is owing to having advantages of that the data depositing in also can not disappear after power-off, therefore much electrical equipmentIn product, must possess this type of memory body, the normal operating while start to maintain electric equipment products. Particularly, fast flash memory bank(flashmemory) can repeatedly carry out the operations such as depositing in, read, wipe of data owing to having, so become PCA kind of memory cell extensively adopting with electronic equipment.
Nitride fast flash memory bank (nitride-basedflashmemory) is that current common one is non-volatileMemory body. In nitride fast flash memory bank, utilize the charge-trapping being formed by oxide skin(coating)-nitride layer-oxide skin(coating)Structure (the ONO layer of knowing) can store the data of two bits. In general, the data of two bits can be stored in respectively electric charge and catchesCatch left side (being left bit) or right side (being right bit) of the nitride layer in structure.
But, in nitride fast flash memory bank, exist second bit effect, when left bit is carried out to read operationTime, can be subject to the impact of right bit, maybe, in the time that right bit is carried out to read operation, can be subject to the impact of left bit. In addition, along withMemory body size is dwindled gradually, and the length of passage (channel) also shortens thereupon, causes second bit effect more remarkable, because ofAnd operation window (operationwindow) and the element efficiency of memory body are affected.
As can be seen here, above-mentioned existing non-volatility memory and preparation method thereof is in product structure, manufacture method and makeUse, obviously still have inconvenience and defect, and be urgently further improved. In order to solve the problem of above-mentioned existence, relevantManufacturer there's no one who doesn't or isn't seeks solution painstakingly, completed by development but have no for a long time applicable design always, and generalProduct and method do not have again appropriate structure and method to address the above problem, and this is obviously asking of the relevant anxious wish solution of dealerTopic. Therefore how to found a kind of new non-volatility memory and preparation method thereof, real one of the current important research and development problem that belongs to,Also become the current industry utmost point and need improved target.
Summary of the invention
Object of the present invention is, overcomes the defect that existing non-volatility memory exists, and provides a kind of newNon-volatility memory, technical problem to be solved is to make it can avoid producing second bit effect in the time of operation, veryBe suitable for practicality.
Another object of the present invention is to, overcome the defect that existing non-volatility memory preparation method exists, and carryFor a kind of preparation method of new non-volatility memory, technical problem to be solved is it can be produced have larger behaviourMake the non-volatility memory of nargin, thereby be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions. Propose according to the present inventionA kind of non-volatility memory, this non-volatility memory comprises that grid structure, doped region, electric charge storage layer and first are situated betweenElectricity layer. Grid structure is disposed in substrate. In the substrate of grid structure two sides, there is depression. Grid structure comprise gate dielectric layer withGrid. Gate dielectric layer is disposed in substrate, and has interface between gate dielectric layer and substrate. Gate configuration is on gate dielectric layer.Doped region is disposed in depression substrate around. Electric charge storage layer is disposed in depression, and the end face of electric charge storage layer is higher than upperThe interface of stating. The first dielectric layer is disposed between electric charge storage layer and substrate and between electric charge storage layer and grid structure.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further. Aforesaid non-wavingSend out property memory body, the thickness of wherein said electric charge storage layer for example betweenExtremelyBetween.
Aforesaid non-volatility memory, wherein said depression for example has sloped sidewall.
Aforesaid non-volatility memory, the material of wherein said electric charge storage layer is for example nitride or high-kMaterial.
Aforesaid non-volatility memory, also comprises the second dielectric layer being disposed on electric charge storage layer, and the second dielectricThe end face of layer and the end face copline of grid structure.
Aforesaid non-volatility memory, also comprises the conductor layer being disposed on the second dielectric layer and grid structure.
Aforesaid non-volatility memory, has distance between wherein said doped region and interface, and depression has bottom surfaceWith at least one sidewall, and doped region is disposed in the substrate of bottom surface below and around the part of sidewall.
Aforesaid non-volatility memory, wherein said distance is for example between 0.005 μ m to 0.01 μ m.
The object of the invention to solve the technical problems also realizes by the following technical solutions. Propose according to the present inventionA preparation method for non-volatility memory, the method is first in substrate, to form grid structure. Grid structure comprises that grid are situated betweenElectricity layer and grid. Gate dielectric layer is positioned in substrate, and has interface between gate dielectric layer and substrate. Grid is positioned at gate dielectric layerOn. Then, in the substrate of grid structure two sides, form depression. Then, on substrate and grid structure, form the first dielectric layer.Then, in the substrate around depression, form doped region. Afterwards, in depression, form electric charge storage layer, and electric charge storage layerEnd face is higher than above-mentioned interface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The preparation method of aforesaid non-volatility memory, the thickness of wherein said electric charge storage layer for example betweenExtremelyBetween.
The preparation method of aforesaid non-volatility memory, wherein said depression for example has sloped sidewall.
The preparation method of aforesaid non-volatility memory, the material of wherein said electric charge storage layer be for example nitride orHigh dielectric constant material.
The preparation method of aforesaid non-volatility memory, wherein, after forming electric charge storage layer, is also included in electric chargeStore upper second dielectric layer that forms of layer.
The preparation method of aforesaid non-volatility memory, wherein, after forming the second dielectric layer, also comprises and putting downSmooth metallization processes, removes part of first dielectric layer and part the second dielectric layer, until expose grid.
The preparation method of aforesaid non-volatility memory, wherein, after carrying out flatening process, is also included in secondOn dielectric layer and grid structure, form conductor layer.
The preparation method of aforesaid non-volatility memory, has distance between wherein said doped region and interface, and recessedFall into and there is bottom surface and at least one sidewall, and doped region is formed in the substrate below bottom surface and around the part of sidewall.
The preparation method of aforesaid non-volatility memory, wherein said distance for example between 0.005 μ m to 0.01 μ m itBetween.
The present invention compared with prior art has obvious advantage and beneficial effect. By technique scheme, the present inventionNon-volatility memory and preparation method thereof at least has following advantages and beneficial effect: at non-volatility memory of the present inventionIn, be disposed at respectively relative two sides of grid structure in order to store the electric charge storage layer of electric charge, thereby increased the logical of memory bodyRoad length and avoid producing second bit effect in the process of operation, and has increased operation window.
In sum, the invention relates to a kind of non-volatility memory and preparation method thereof. This non-volatile memoryBody comprises grid structure, doped region, electric charge storage layer and the first dielectric layer. Grid structure is disposed in substrate. Grid structureIn the substrate of two sides, there is depression. Grid structure comprises gate dielectric layer and grid. Gate dielectric layer is disposed in substrate, and grid dielectricBetween layer and substrate, there is interface. Gate configuration is on gate dielectric layer. Doped region is disposed in depression substrate around. Electric charge storageDeposit layer and be disposed in depression, and the end face of electric charge storage layer is higher than above-mentioned interface. The first dielectric layer is disposed at electric charge storage layerAnd between substrate and between electric charge storage layer and grid structure. The present invention is a significant progress in technology, and has obviouslyGood effect, be really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention,And can be implemented according to the content of description, and for allow above and other object of the present invention, feature and advantage canBecome apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Brief description of the drawings
Figure 1A to Fig. 1 D is the making flow process profile of the non-volatility memory that illustrates according to the embodiment of the present invention.
10: non-volatility memory 100: substrate
102: gate dielectric layer 104: grid
106: grid structure 108: depression
110,116: dielectric layer 112: doped region
113: interface 114: electric charge storage layer
118: conductor layer D1: distance
W1: width
Detailed description of the invention
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction withAccompanying drawing and preferred embodiment, to its detailed description of the invention of non-volatility memory and preparation method thereof proposing according to the present invention,Structure, method, step, feature and effect thereof, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic, coordinate with reference to graphic better reality followingExecute in routine detailed description and can know and present. By the explanation of detailed description of the invention, should be predetermined for reaching to the present inventionThe technological means that object is taked and effect obtain one more deeply and concrete understanding, but the appended graphic reference that is only to provideWith the use of explanation, be not used for the present invention to be limited.
Figure 1A to Fig. 1 D is the making flow process profile of the non-volatility memory that illustrates according to the embodiment of the present invention. FirstFirst, refer to shown in Figure 1A, substrate 100 is provided. Substrate 100 is for example for having silicon (siliconon on silicon base or insulating barrierInsulator, SOI) substrate. Then, in substrate 100, sequentially form grid dielectric materials layer (not illustrating) and gate material layers(not illustrating). Grid dielectric materials layer is for example oxide layer, its thickness for example betweenExtremelyBetween, its formation sideRule is as being thermal oxidation method or chemical vapour deposition technique. Gate material layers is for example polysilicon layer, and its formation method is for example for changingLearn vapour deposition process. Then, by gate material layers and grid dielectric materials layer patterning, to form grid 104 and gate dielectric layer102. The width W 1 of grid 104 is for example between 0.05 μ m to 0.1 μ m. Gate dielectric layer 102 forms grid structure with grid 104106。
Then, refer to shown in Figure 1B, in the substrate 100 of grid structure 106 sides, form depression 108. The shape of depression 108One-tenth method is for example to carry out anisotropic etch process, to remove part substrate 100. In the present embodiment, depression 108 has and inclinesTiltedly sidewall, but the present invention is not limited to this. In other embodiments, depression 108 also can have vertical sidewall. Then, in substrate100 with grid structure 106 on form dielectric layer 110. Dielectric layer 110 is for example oxide layer, its thickness for example betweenExtremelyBetween, its formation method is for example thermal oxidation method or chemical vapour deposition technique.
Then, refer to shown in Fig. 1 C, in the substrate 100 around depression 108, form doped region 112. In detail, recessedFall into 108 and there is bottom surface 108a and at least one sidewall 108b, and doped region 112 is formed in the substrate 100 of bottom surface 108a belowAnd around sidewall 108b partly. The formation method of doped region 112 is for example to carry out ion implantation technology. Doped region 112 darkDegree is for example between 0.05 μ m to 0.09 μ m. Importantly, between gate dielectric layer 102 and substrate 100, there is interface 113, andBetween doped region 112 and interface 113, do not contact, between the two, there is distance B 1. Distance B 1 is for example between 0.005 μ m to 0.01Between μ m. The doped region 112 that is positioned at grid structure 106 2 sides is respectively as source area and the drain region of non-volatility memory.Then, form electric charge storage layer 114 in depression in 108, to complete the making of non-volatility memory 10 of the present embodiment, and position110 use as tunneling dielectric layer of dielectric layer between electric charge storage layer 114 and substrate 100. The top of electric charge storage layer 114Face is higher than interface 113. The material of electric charge storage layer 114 is for example nitride or high dielectric constant material, its thickness for example betweenExtremelyBetween. The formation method of electric charge storage layer 114 is for example that elder generation's deposited charge in depression 108 stores materialThe bed of material, and then carry out etch back process, to remove Partial charge storage material layer.
Afterwards, refer to shown in Fig. 1 D, forming after electric charge storage layer 114, can also be on electric charge storage layer 114 shapeBecome dielectric layer 116. Dielectric layer 116 is for example oxide layer. The formation method of dielectric layer 116 is for example first at electric charge storage layer 114Upper deposition of dielectric materials layer, then carries out flatening process, removes part dielectric layer 116 and dielectric layer 110, until expose gridThe utmost point 104. Then, on dielectric layer 116,110 and grid structure 106, form conductor layer 118. Conductor layer 118 can be used to wave non-The grid 104 of the property sent out memory body 10 is connected with the grid of adjacent non-volatility memory (not illustrating), i.e. conductor layer 118 conductsThe use of character line.
In non-volatility memory 10, be disposed at respectively grid structure 106 in order to the electric charge storage layer 114 that stores electric chargeRelative two sides, the passage length that therefore can effectively avoid memory body is too short and produce second bit in the process of operationEffect, and increased operation window.
In addition, in non-volatility memory 10, owing to thering is distance B 1 between doped region 112 and interface 113 but not mutuallyBe connected, therefore, in the time that non-volatility memory 10 is operated, electric charge effectively iunjected charge stores layer 114.
Moreover, because the end face of electric charge storage layer 114 is higher than interface 113, therefore can avoid electric charge directly through dielectricLayer 110 and iunjected charge store layer 114 top dielectric layer 116 in.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction, thoughSo the present invention discloses as above with preferred embodiment, but is not in order to limit the present invention, is anyly familiar with this professional technology peopleMember, is not departing within the scope of technical solution of the present invention, when method and the technology contents that can utilize above-mentioned announcement are made more a littleMoving or be modified to the equivalent embodiment of equivalent variations, is the content that does not depart from technical solution of the present invention in every case, according to of the present inventionAny simple modification, equivalent variations and modification that technical spirit is done above embodiment, all still belong to technical solution of the present inventionScope in.
Claims (19)
1. a non-volatility memory, is characterized in that it comprises:
Grid structure, is disposed in substrate, in the described substrate of described grid structure both sides, has depression, described grid structure bagDraw together:
Gate dielectric layer, is disposed in described substrate, between described gate dielectric layer and described substrate, has interface; And
Grid, is disposed on described gate dielectric layer;
Doped region, is disposed in the described substrate around of described depression;
Electric charge storage layer, is disposed in described depression, and the end face of described electric charge storage layer is higher than described interface; And
The first dielectric layer, is disposed between described electric charge storage layer and described substrate and described electric charge storage layer and described gridBetween structure.
2. non-volatility memory according to claim 1, is characterized in that the thickness of wherein said electric charge storage layer is situated betweenInExtremelyBetween.
3. non-volatility memory according to claim 1, is characterized in that wherein said depression has sloped sidewall.
4. non-volatility memory according to claim 1, is characterized in that the material bag of wherein said electric charge storage layerDraw together nitride.
5. non-volatility memory according to claim 1, is characterized in that the material bag of wherein said electric charge storage layerDraw together high dielectric constant material.
6. non-volatility memory according to claim 1, characterized by further comprising the second dielectric layer, described in being disposed atOn electric charge storage layer, and the end face copline of the end face of described the second dielectric layer and described grid structure.
7. non-volatility memory according to claim 6, characterized by further comprising conductor layer, is disposed at described secondOn dielectric layer and described grid structure.
8. non-volatility memory according to claim 1, it is characterized in that wherein said doped region and described interface itBetween there is distance, described depression has bottom surface and at least one sidewall, and described doped region is disposed at the institute of below, described bottom surfaceState in substrate and around the part of described sidewall.
9. non-volatility memory according to claim 8, is characterized in that wherein said distance between 0.005 μ m extremelyBetween 0.01 μ m.
10. a preparation method for non-volatility memory, is characterized in that it comprises the following steps:
In substrate, form grid structure, described grid structure comprises:
Gate dielectric layer, is positioned in described substrate, between described gate dielectric layer and described substrate, has interface; And
Grid, is positioned on described gate dielectric layer;
In the described substrate of described grid structure both sides, form depression;
On described substrate and described grid structure, form the first dielectric layer;
In the described substrate around described depression, form doped region;
In described depression, form electric charge storage layer, the end face of described electric charge storage layer is higher than described interface.
The preparation method of 11. non-volatility memories according to claim 10, is characterized in that wherein said electric charge storageDeposit layer thickness betweenExtremelyBetween.
The preparation method of 12. non-volatility memories according to claim 10, is characterized in that wherein said depression toolThere is sloped sidewall.
The preparation method of 13. non-volatility memories according to claim 10, is characterized in that wherein said electric charge storageThe material of depositing layer comprises nitride.
The preparation method of 14. non-volatility memories according to claim 10, is characterized in that wherein said electric charge storageThe material of depositing layer comprises high dielectric constant material.
The preparation method of 15. non-volatility memories according to claim 10, is characterized in that wherein described in formingAfter electric charge storage layer, be also included in and on described electric charge storage layer, form the second dielectric layer.
The preparation method of 16. non-volatility memories according to claim 15, is characterized in that wherein described in formingAfter the second dielectric layer, also comprise and carry out flatening process, remove described the first dielectric layer of part and described the second dielectric of partLayer, until expose described grid.
The preparation method of 17. non-volatility memories according to claim 16, is characterized in that wherein described in carrying outAfter flatening process, be also included on described the second dielectric layer and described grid structure and form conductor layer.
The preparation method of 18. non-volatility memories according to claim 16, is characterized in that wherein said doped regionAnd have distance between described interface, described depression has bottom surface and at least one sidewall, and described in described doped region is formed atIn the described substrate of bottom surface below and around the part of described sidewall.
The preparation method of 19. non-volatility memories according to claim 18, is characterized in that wherein said distance is situated betweenBetween 0.005 μ m to 0.01 μ m.
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| CN101197395A (en) * | 2006-12-04 | 2008-06-11 | 海力士半导体有限公司 | Semiconductor memory device and method of manufacturing the same |
| JP2010192921A (en) * | 2010-04-12 | 2010-09-02 | Renesas Technology Corp | Method of manufacturing semiconductor device, and semiconductor device |
| CN101908560A (en) * | 2009-06-08 | 2010-12-08 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102024820A (en) * | 2009-09-22 | 2011-04-20 | 旺宏电子股份有限公司 | Memory cell and manufacture method thereof and memory structure |
| CN102738209A (en) * | 2011-04-06 | 2012-10-17 | 旺宏电子股份有限公司 | Semiconductor element and preparation method thereof |
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| US7518179B2 (en) * | 2004-10-08 | 2009-04-14 | Freescale Semiconductor, Inc. | Virtual ground memory array and method therefor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197395A (en) * | 2006-12-04 | 2008-06-11 | 海力士半导体有限公司 | Semiconductor memory device and method of manufacturing the same |
| CN101908560A (en) * | 2009-06-08 | 2010-12-08 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102024820A (en) * | 2009-09-22 | 2011-04-20 | 旺宏电子股份有限公司 | Memory cell and manufacture method thereof and memory structure |
| JP2010192921A (en) * | 2010-04-12 | 2010-09-02 | Renesas Technology Corp | Method of manufacturing semiconductor device, and semiconductor device |
| CN102738209A (en) * | 2011-04-06 | 2012-10-17 | 旺宏电子股份有限公司 | Semiconductor element and preparation method thereof |
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