CN103887202A - Monitor method - Google Patents
Monitor method Download PDFInfo
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- CN103887202A CN103887202A CN201410109846.9A CN201410109846A CN103887202A CN 103887202 A CN103887202 A CN 103887202A CN 201410109846 A CN201410109846 A CN 201410109846A CN 103887202 A CN103887202 A CN 103887202A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention discloses a monitor method. The monitor method is used for monitoring performance of a SiGe structure and an STI interface in an on-line mode. According to the monitor method, leakage current of the SiGe structure and the STI interface is measured by forming an edge type PN junction and an area type PN junction which are the same in junction area, and the states of the SiGe structure and the STI interface are obtained through data comparison and analysis. Thus, the states of the SiGe structure and the STI interface can be monitored directly by monitoring the leakage current of the SiGe structure and the STI interface, then on-line products are monitored in real time, the situation that TEM slicing is carried out for searching whether the interface is normal or not after problems occur is avoided, and product yield is largely improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the monitoring method of a kind of SiGe of monitoring structure and STI interface performance.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET device is constantly reducing, and generally includes reducing of MOSFET device channel length, and the attenuate of gate oxide thickness etc. are to obtain device speed faster.But while being developed to sub-micro level along with very large scale integration technology, particularly when 90 nanometers and following technology node, reduce channel length and can bring series of problems, in order to control short-channel effect, can in raceway groove, mix the impurity with higher concentration, this can reduce the mobility of charge carrier, thereby causes device performance to decline, and simple device size reduces to be difficult to meet the development of large scale integrated circuit technology.Therefore, the broad research of stress engineering is used for improving the mobility of charge carrier, thereby reaches device speed faster, and meets the rule of Moore's Law.
The eighties in last century, academia just started to realize heterostructure research based on silicon-based substrate to the nineties, until just realize business application the beginning of this century.Wherein have two kinds of representational stress application, a kind of is the biaxial stress technology (Biaxial Technique) being proposed by IBM; Another kind is the simple stress technology (Uniaxial Technique) being proposed by Intel; Be SMT(Stress Memorization Technology) raceway groove of NMOSFET is applied to tensile stress improve the mobility of electronics, with selectivity (or embed) epitaxial growth Ge-Si (SiGe structure) applies compression to PMOSFET raceway groove and improve two kinds of processes of the mobility in hole, thereby improve the performance of device.Wherein, with reference to accompanying drawing 1, selective epitaxial growth SiGe technique forms COMS device and generally includes following steps: first carry out step S100, carry out shallow trench isolation from making, to form fleet plough groove isolation structure on substrate; Then carry out step S101, carry out trap injection, form P type trap or N-type trap; Then carry out step S102, form grid; Carry out afterwards step S103, carry out light dope injection, form and leak light-dope structure; Then carry out step S104, on gate lateral wall, make grid the first side wall; Carry out afterwards step S105, carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas; Carry out step S106, make grid the second side wall; Carry out step S107, carry out source and leak injection to form source-drain electrode; Then carry out step S108, carry out the making of the front medium of metal, through hole, metal plug and metal level.
For selectivity (or embedding) epitaxial growth SiGe technique, there is research in large quantities to find gas composition, the flow of growth technique, cavity reaction temperature, time, the meeting counter stresses such as annealing temperature, time exert an influence, and set up wired upper real-time monitoring system and monitor the stability of above-mentioned technological parameter.But, these are all the performances of Characterization of Ge-Si SiGe structure self only, and SiGe structure and SI interface and SiGe structure and STI interface performance quality, can directly affect device performance, thereby affect the operating state of whole circuit, the monitoring that existing monitoring system can not reflect, the performance at these two interfaces.Conventionally, can only on technique research and development or production line, product goes wrong time, whether problem sample to cut into slices to study interface normal if being carried out to TEM, do not have good semiconductor process line method of real-time.
For SiGe structure and SI interface, conventionally can be designed with large-area P type heavy doping SiGe structure and N-type trap PN junction, characterize interfacial characteristics by the leakage current of this PN junction of on-line measurement.But for SiGe structure and STI interface, do not have good on-line monitoring method.
Summary of the invention
The invention provides a kind of monitoring method, to realize the object of on-line monitoring SiGe structure and STI interface performance.
For overcoming the above problems, the invention provides a kind of monitoring method, for on-line monitoring SiGe structure and STI interface performance, described monitoring method comprises:
The domain of the area-type PN junction that design SiGe structure and N-type trap form;
Design multiple peripheral type PN junction parallel-connection structures, the junction area of described multiple peripheral type PN junctions is identical with the junction area of described area-type PN junction;
In device manufacturing processes, on substrate, form described peripheral type PN junction and area-type PN junction;
Leakage current the record of two kinds of PN junctions of on-line measurement;
Be normalized calculating, calculate respectively area-type PN junction normallized current IL
aPwith peripheral type PN junction normallized current IL
eP;
Calculate the difference Δ IL of normallized current, Δ IL=IL
aP-IL
eP;
Carry out IL
aP, IL
ePand the data analysis of Δ IL, judge the interface performance of SiGe structure and STI.
Optionally, carry out IL
aP, IL
ePand the data analysing method of Δ IL is: by IL
aP, IL
ePand the contrast of Δ IL and critical field, when PN junction has when abnormal, IL
aPand IL
ePsimultaneously abnormal; When SiGe structure and STI interface are when abnormal, IL
aPnormally, IL
ePiL is abnormal with Δ.
Optionally, in the process of selectivity epitaxial growth SiGe technique formation COMS device, on substrate, form two kinds of above-mentioned PN junctions, comprising:
Carry out shallow trench isolation from making, to form fleet plough groove isolation structure on substrate;
Carry out trap injection, form P type trap or N-type trap, form the N-type trap of peripheral type PN junction and area-type PN junction simultaneously;
Form grid;
Carry out light dope injection, form and leak light-dope structure;
On gate lateral wall, make grid the first side wall;
Carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas, on the N-type trap of peripheral type PN junction and area-type PN junction, form the SiGe structure of peripheral type PN junction and area-type PN junction, to form peripheral type PN junction and area-type PN junction;
Make grid the second side wall, carry out source and leak injection to form source-drain electrode, and carry out the making step of the front medium of metal, through hole, metal plug and metal level.
Optionally, described grid is polysilicon material.
Optionally, inject by the drain electrode of P type doped source the source-drain electrode that forms P type, described P type is doped to boron doping.
Optionally, described selective epitaxial growth SiGe technique comprises, carving technology is returned in the region that form SiGe structure, then selective epitaxial growth SiGe structure
Compared with prior art, in the process that detection method provided by the present invention forms at device, form peripheral type PN junction and area-type PN junction that junction area is identical simultaneously, the then leakage current of two kinds of PN junctions of Measurement and analysis, realization judges the object of the interface performance of SiGe structure and STI.Like this, can monitor the product on production line, cut into slices to study without carrying out again TEM after going wrong at product, greatly promote product yield.
Accompanying drawing explanation
Fig. 1 is the flow chart that existing selective epitaxial growth SiGe technique forms COMS device;
Fig. 2 is the flow chart of embodiment of the present invention monitoring method;
Fig. 3 is the domain of overlooking of the area-type PN junction of embodiment of the present invention monitoring method and marginality PN junction;
Fig. 4 is the cross-sectional view of part peripheral type PN junction and area-type PN junction in this enforcement monitoring method.
Embodiment
In background technology, mention, the method not the SiGe structure at line products and SI interface state not being detected in prior art, when product goes wrong on line, carries out TEM section to problem sample and studies, and has a strong impact on product yield.
For this reason, the invention provides a kind of monitoring method, for on-line monitoring SiGe structure and STI interface performance.Core concept of the present invention is, the leakage current at the interface by monitoring SiGe structure and STI is realized the state at the interface of monitoring SiGe structure and STI.The PN junction of peripheral type is except PN junction leakage current, on the SiGe structure at edge of tying and the interface of STI, also there will be leakage current, this is to be the epitaxial growth of selection type due to SiGe structure,, form SiGe structure based on Si " seed " extension, and STI material is SiO2, therefore the interface of SiGe structure and STI is not very perfect, there will be leakage current yet.Peripheral type PN junction and area-type PN junction have identical junction area, and the interface of peripheral type PN junction marginal existence larger area SiGe structure and STI, both leakage currents of contrast can obtain the leakage current at the interface of SiGe structure and STI like this, and the leakage current that can realize the interface by monitoring SiGe structure and STI is realized the object of the state at the interface of monitoring SiGe structure and STI.
Please refer to Fig. 2, it is the flow chart of embodiment of the present invention monitoring method, and described method comprises the steps:
Step S010, the domain of the area-type PN junction that design SiGe structure and N-type trap form;
Step S011, designs multiple peripheral type PN junction parallel-connection structures, and the junction area of described multiple peripheral type PN junctions is identical with the junction area of described area-type PN junction;
Step S012 forms two kinds of above-mentioned PN junctions in device manufacturing processes on substrate;
Step S013, leakage current the record of two kinds of PN junctions of on-line measurement;
Step S014, is normalized calculating, calculates respectively area-type PN junction normallized current IL
aPwith peripheral type PN junction normallized current IL
eP;
Step S015, the difference Δ IL of calculating normallized current, Δ IL=IL
aP-IL
eP;
Step S016, carries out data analysis: by IL
aP, IL
ePand the contrast of Δ IL and critical field, when PN junction has when abnormal, IL
aPand IL
ePsimultaneously abnormal; When SiGe structure and STI interface are when abnormal, IL
aPnormally, IL
ePiL is abnormal with Δ.Wherein, described critical field can be by online a large amount of IL
aP, IL
ePand Δ IL data are formulated acquisition.
To specifically tie and in CMOS fabrication processing, the present invention is described in more detail below, the preferred embodiments of the present invention are wherein represented, should the described those skilled in the art of understanding can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
First, execution step S010 and S011, the domain of the area-type PN junction that design SiGe structure and N-type trap form, and design multiple peripheral type PN junction parallel-connection structures, the area of described multiple peripheral type PN junctions and described area-type PN junction equal area.With reference to Fig. 3, wherein, 401 is area-type PN junction overlooks domain, and 402 is marginality PN junction overlooks domain.In the present embodiment, the domain 401 of described marginality PN junction can comprise all shapes of selective epitaxial growth SiGe structure in COMS technique, for example " work " font, " ten " font, " mouth " font etc.Be understandable that, shape in Fig. 3 is only for peripheral type PN junction is tied and the embodiment of CMOS manufacture craft in the present embodiment, its domain shape is not limited only to the shape in Fig. 3, can comprise all distribution of shapes of SiGe structure in actual process production, those skilled in the art can be according to core concept knot of the present invention and concrete device fabrication design peripheral type PN junction domain shape.
Then perform step S012, form two kinds of above-mentioned PN junctions in COMS device manufacturing processes on substrate, with reference to Fig. 4, Fig. 4 is the cross-sectional view of part peripheral type PN junction and area-type PN junction in this enforcement monitoring method.Described area-type PN junction has larger junction area, and described peripheral type PN junction has more and contact-making surface STI in knot edge.Wherein, utilize the process can be with reference to background technology part and accompanying drawing 1: first to carry out step S100, carry out shallow trench isolation from making, to form fleet plough groove isolation structure (STI) 403 on substrate; Then carry out step S101, carry out trap injection, form P type trap or N-type trap, in this step, form the N-type trap 405 of peripheral type PN junction and area-type PN junction simultaneously; Then carry out step S102, form grid, in the present embodiment, described grid is polysilicon material; Carry out afterwards step S103, carry out light dope injection, form and leak light-dope structure; Then carry out step S104, on gate lateral wall, make grid the first side wall; Carry out afterwards step S105, carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas, in same step, on the N-type trap of peripheral type PN junction and area-type PN junction, form the SiGe structure 404 of peripheral type PN junction and area-type PN junction, formed respectively peripheral type PN junction 402 and area-type PN junction 401; Proceed afterwards follow-up COMS processing step S106, S107 and S108, make grid the second side wall, carry out source and leak injection to form source-drain electrode, carry out the making of the front medium of metal, through hole, metal plug and metal level, in the present embodiment, inject by the drain electrode of P type doped source the source-drain electrode that forms P type, described P type is doped to boron doping.Described selective epitaxial growth SiGe technique comprises, carving technology is returned in the region that form SiGe structure, then selective epitaxial growth SiGe structure.Specific in this enforcement, carving technology is returned in the source drain region to COMS on silicon substrate and peripheral type PN junction and area-type PN junction region, then forms SiGe structure based on Si " seed " extension.
Having formed respectively after peripheral type PN junction and area-type PN junction, carry out step S013, leakage current the record data of two kinds of PN junctions of on-line measurement; For example can detect when website by the WAT after COMS metal level is made, respectively the leakage current of described area-type PN junction and peripheral type PN junction is measured.
Carry out afterwards step S014, be normalized calculating, calculate respectively area-type PN junction normallized current IL
aPwith peripheral type PN junction normallized current IL
eP; Then carry out step S015, calculate the difference Δ IL of normallized current, Δ IL=IL
aP-IL
eP.Wherein IL
aPcharacterize the state of area-type PN junction, IL
ePcharacterize the state of peripheral type PN junction, the state at SiGe structure and STI interface, Δ IL has characterized the state at SiGe structure and STI interface.
Then perform step S016, carry out data analysis: by IL
aP, IL
ePand the contrast of Δ IL and critical field, when PN junction has when abnormal, IL
aPand IL
ePsimultaneously abnormal; When SiGe structure and STI interface are when abnormal, IL
aPnormally, IL
ePiL is abnormal with Δ.Wherein, described critical field can be by online a large amount of IL
aP, IL
ePand Δ IL data are formulated acquisition.Conventionally can utilize the data of all like products to draw out parameter curve table, customize out rational scope.Can reflect like this state at the SiGe of line products structure and STI interface performance, whether without carrying out TEM, to cut into slices to study interface normal.
Certainly, above-described embodiment is only for knot with to the scheme in CMOS fabrication processing, and those skilled in the art can be according to core concept of the present invention, by monitoring method knot of the present invention with in other selective epitaxial growths SiGe technique.
In sum, monitoring method provided by the invention, by forming identical peripheral type PN junction and the area-type PN junction of junction area, measures both leakage currents, obtains the state at the interface of SiGe structure and STI by comparing and analysis.Adopt in such a way, can be directly the leakage current at interface by monitoring SiGe structure and STI monitor the state at the interface of SiGe structure and STI.Thereby realize Real-Time Monitoring to product on line, produce and carry out again TEM whether cut into slices to study interface normal without problem by the time, greatly improved product yield.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. a monitoring method, for on-line monitoring SiGe structure and STI interface performance, described monitoring method comprises:
The domain of the area-type PN junction that design SiGe structure and N-type trap form;
Design multiple peripheral type PN junction parallel-connection structures, the junction area of described multiple peripheral type PN junctions is identical with the junction area of described area-type PN junction;
In device manufacturing processes, on substrate, form described peripheral type PN junction and area-type PN junction;
Leakage current the record of two kinds of PN junctions of on-line measurement;
Be normalized calculating, calculate respectively area-type PN junction normallized current IL
aPwith peripheral type PN junction normallized current IL
eP;
Calculate the difference Δ IL of normallized current, Δ IL=IL
aP-IL
eP;
Carry out IL
aP, IL
ePand the data analysis of Δ IL, judge the interface performance of SiGe structure and STI.
2. monitoring method as claimed in claim 1, is characterized in that: carry out IL
aP, IL
ePand the data analysing method of Δ IL is: by IL
aP, IL
ePand the contrast of Δ IL and critical field, when PN junction has when abnormal, IL
aPand IL
ePsimultaneously abnormal; When SiGe structure and STI interface are when abnormal, IL
aPnormally, IL
ePiL is abnormal with Δ.
3. monitoring method as claimed in claim 1, is characterized in that: form in the process of COMS device in selective epitaxial growth SiGe technique, form two kinds of above-mentioned PN junctions on substrate.
4. monitoring method as claimed in claim 3, is characterized in that: on substrate, form the junction area of described peripheral type PN junction and the step of described area-type PN junction comprises:
Carry out shallow trench isolation from making, to form fleet plough groove isolation structure on substrate;
Carry out trap injection, form P type trap or N-type trap, form the N-type trap of peripheral type PN junction and area-type PN junction simultaneously;
Form grid;
Carry out light dope injection, form and leak light-dope structure;
On gate lateral wall, make grid the first side wall;
Carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas, on the N-type trap of peripheral type PN junction and area-type PN junction, form the SiGe structure of peripheral type PN junction and area-type PN junction, to form peripheral type PN junction and area-type PN junction;
Make grid the second side wall, carry out source and leak injection to form source-drain electrode, and carry out the making step of the front medium of metal, through hole, metal plug and metal level.
5. monitoring method as claimed in claim 4, is characterized in that: described grid is polysilicon material.
6. monitoring method as claimed in claim 4, is characterized in that: inject by the drain electrode of P type doped source the source-drain electrode that forms P type, described P type is doped to boron doping.
7. monitoring method as claimed in claim 4, is characterized in that: described selective epitaxial growth SiGe technique comprises, carving technology is returned in the region that form SiGe structure, then selective epitaxial growth SiGe structure.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943531A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for monitoring auto-doping boron concentration in germanium-silicon process on line |
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| US5486772A (en) * | 1994-06-30 | 1996-01-23 | Siliconix Incorporation | Reliability test method for semiconductor trench devices |
| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN102800594A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105604A (en) * | 1985-07-24 | 1987-02-11 | 海因茨·克鲁格 | The circuit structure that is used for testing integrated circuit components |
| US5486772A (en) * | 1994-06-30 | 1996-01-23 | Siliconix Incorporation | Reliability test method for semiconductor trench devices |
| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN102800594A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103943531A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for monitoring auto-doping boron concentration in germanium-silicon process on line |
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