CN103887172B - Full lining bottom isolates FINFET transistors - Google Patents

Full lining bottom isolates FINFET transistors Download PDF

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Publication number
CN103887172B
CN103887172B CN201310489429.7A CN201310489429A CN103887172B CN 103887172 B CN103887172 B CN 103887172B CN 201310489429 A CN201310489429 A CN 201310489429A CN 103887172 B CN103887172 B CN 103887172B
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fin
grid
semi
silicon substrate
array
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CN201310489429.7A
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CN103887172A (en
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N·劳贝特
P·卡雷
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意法半导体公司
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Priority to US13/725,528 priority patent/US8956942B2/en
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Publication of CN103887172A publication Critical patent/CN103887172A/en
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    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
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Abstract

Prevent the raceway groove in FinFET to substrate leakage by inserting insulating barrier between substrate in semi-conduction raceway groove (fin).Similarly, prevent the source/drain in FinFET to substrate leakage by inserting insulator separation regions and source/drain between regions and source/drain and substrate with substrate.Insulating barrier physically and electrically isolates conducting path and substrate, therefore prevents current leakage.If semi-conduction fin array is made up of multiple-level stack, base material can be removed, therefore produce the fin array of side's suspension on a silicon surface.Then it can preferably support fin to the gained gap fill oxide at the top of residue below fin material and isolate fin array and substrate.Gained FinFET is isolated in both area of grid and regions and source/drain for full lining bottom.

Description

Full lining bottom isolates FINFET transistors

Technical field

Present disclosure is related to the making of integrated circuit transistor, and specifically related to low leakage three-dimensional FinFET (is imitated field Answer transistor) making of device.

Background technology

In digital circuit, transistor is switch, and the switch is ideally:A) zero current is transmitted when it is turned off;B) at it High current flowing is supplied during conducting;And c) instantaneously switch between conducting and off state.Regrettably, it is being configured in collection Transistor is not preferable and often still leakage current when it is turned off during into circuit.By device or from The electric current of device leakage often exhausts the battery that power is supplied to device.For many years, by reducing critical dimension to increase switching Speed improves integrated circuit transistor performance.Continue to reduce however as the yardstick of the transistor based on silicon, maintenance includes closing The control of the various electrical characteristics of disconnected state leak becomes more and more challenging, and the performance benefit obtained from reduction device dimension Become less notable.Therefore it is general advantageously to be reduced by the alternative means including changing material and device geometries Leakage current in transistor.

Integrated circuit is usually incorporated into FET, in these FET, and current-responsive is flowed through in source electrode in the voltage applied to grid Semi-conduction raceway groove between drain electrode.Show in figure ia and conventional planar described more particularly below (2D) transistor arrangement. In order to provide the more preferably control to electric current flowing, the FinFET transistors of sometimes referred to as 3D transistors, such as Figure 1B have been developed Shown in FinFET transistors.FinFET is electronic switch part, in the electronic switch part, and traditional FET plane half is passed Guide channel road is replaced by the semi-conduction fin (fin) extended perpendicularly outward with substrate surface.In such devices, in control fin The grid of electric current flowing rolls up bag (wrap) to influence electric current stream from three surfaces rather than a surface around three sides of fin It is dynamic.The improved control realized with FinFET design produces faster performance of handoffs and the current leakage of reduction.

Intel describes the transistor of this type in the circular on May 4th, 2011, by it titled with including 3D crystal The various appellations of pipe, 3D tri-gate transistors or FinFET.(for example, see on the internet positioned at http:// News.cnet.com/8301-13924_3-20059431-64.html, entitled " How Intel ' s3D tech Redefines the transistor " article;Referring also to:Kavalieros et al. U.S. Publication NO.2009/ 0090976, it is disclosed on April 9th, 2009;Rakshit et al. United States Patent (USP) NO.8,120,073;Rios et al. the U.S. is special Sharp NO.7,973,389;Hareland et al. United States Patent (USP) NO.7,456,476;And Chau et al. United States Patent (USP) NO.7, 427,794。)

Figure 2 illustrates semi-conduction fin array.Generally, can by conformally deposited on fin array public grid come Form the array of multiple transistors.Furthermore it is possible to many to be formed by conformally depositing multiple public grids on fin array Gridistor array.The such FinFET arrays for having three grids between source electrode and drain region are referred to as three gate transistors Pipe.

Before exploitation FinFET, develop strain silicon transistor to increase the electric charge carrier in double of conduction Mobility is controlled.Compression strain is introduced into transistor material often increases charge mobility, so as to produce to applying to grid Voltage change faster handoff response.For example source electrode and drain region can be replaced by using the silicon compound of epitaxial growth In or raceway groove in itself in body silicon introduce strain.Term extension refers to controlled xtal growth technique, in the process from The new epitaxial crystal layer of superficial growth of body crystal, and maintain the same crystal structure of following body transistor.

The improvement provided in spite of three-dimensional structure and strained silicon materials, transistor is still as device dimension tapers to 1-50 Certain form of hydraulic performance decline is continued to suffer from the range of nanometer.These hydraulic performance declines are specifically included in semi-conduction raceway groove and lining Charge leakage between bottom.

The content of the invention

According to one embodiment as described herein, by insert insulating barrier between the raceway groove and substrate as fin and every Prevent the raceway groove in FinFET to substrate leakage from raceway groove and substrate.Insulating barrier physically and electrically isolates fin and substrate, because This prevents the current leakage between fin and substrate.In theory, in No leakage, device is all-pass or complete disconnected.

If fin includes two kinds of different materials, base material can be easily removed and leave top material, therefore produced The semi-conduction fin array that side is suspended on a silicon surface.Then if it is desired to can then be filled in fin material at the top of residue with oxide Following gained gap is preferably to support fin and isolate fin channel array and substrate.

Similarly, according to one embodiment as described herein, by inserting exhausted between regions and source/drain and substrate Edge layer and isolate regions and source/drain and substrate to prevent the source/drain in FinFET to substrate leakage.Insulating barrier thing Reason and electric isolution regions and source/drain and substrate, therefore prevent the current leakage between source/drain and substrate.Therefore, institute FinFET is obtained in both area of grid and regions and source/drain for full lining bottom to isolate.

Brief description of the drawings

In the accompanying drawings, identical label mark similar components.The size for the element being not necessarily drawn to scale in accompanying drawing and relative Position.

Figure 1A is prior art plane FET diagram perspective drawing.

Figure 1B is prior art FinFET diagram perspective drawing.

Fig. 2 is the saturating of the array of the semi-conduction fin of the epitaxial growth obtained from actual scanning electron microscope (SEM) image View.

Fig. 3 is the high-level process flow figure for showing the basic step when forming full isolation FinFET as described herein.

Fig. 4 is the intermediate technique stream for showing the additional detail in full isolation FinFET technique as described herein is formed Cheng Tu.

Fig. 5 A are to show dopant and to form what fin was stacked for injecting to silicon substrate according to one embodiment The process chart of series of process steps.

Fig. 5 B are the side views for the device profile that technological process shown in Fig. 5 A is formed, and there is shown with covering that composition fin is stacked Cover (blanket) layer.

Fig. 6 A are that show can be for the another processing step sequence that forms illusory plug (mandrel) and silicon nitride spacer The process chart of row.

Fig. 6 B are the side views for the device profile that technological process shown in Fig. 6 A is formed, and there is shown with the sacrifice knot of completion Structure.

Fig. 7 A illustrate process chart, and the technological process, which is illustrated, can be used for carrying out pattern using sidewall image transfer technique Change the process chart for the another series of process steps that fin is stacked.

Fig. 7 B are the side views for the device profile that technological process shown in Fig. 7 A is formed, and there is shown with the multilayer epitaxial of completion Fin array.

Fig. 8 A are process charts, and the technological process is illustrated can provide office for the extension fin array shown in Fig. 7 B The another series of process steps of portionization isolation.

Fig. 8 B are the side views for the device profile that technological process shown in Fig. 8 A is formed, wherein isolating between setting up fin.

Fig. 9 A are process charts, and the technological process, which is illustrated, can be used for etching and filling in the either end of fin array The another series of process steps of isolated groove.

Fig. 9 B are the side views for the device profile that technological process shown in Fig. 9 A is formed, wherein in fin array and adjacent domain Between lateral isolation is provided.

Figure 10 A, 11A, 12A, 13A and 14A are the technique phases for wherein isolating raceway groove and regions and source/drain with substrate Between along the FinFET profile in area of grid line A-A' cut side view.

Figure 10 B, 11B, 12B, 13B and 14B are the technique phases for wherein isolating raceway groove and regions and source/drain with substrate Between along the FinFET profile in regions and source/drain line B-B ' cut side view.

Figure 10 C, 11C, 12C, 13C and 14C are the perspective views of two transistor structure as described herein, these perspective diagrams Go out the change of area of grid (A-A ') and regions and source/drain profile (B- when forming isolated gate and source/drain structures B ') change.

Figure 10 D be show can for deposited sacrificial grid and the another series of process steps of sept technological process Figure.

Figure 11 D are process charts, and the technological process, which is illustrated, to be shown to adulterate outside for preparing the original position that is used for of fin The another series of process steps of the topsheet surface of epitaxial growth.

Figure 12 D are process charts, and the technological process, which is illustrated, can be used for removing bottom fin layer to create space again One series of process steps.

Figure 13 D are process charts, the technological process illustrate can be used for isolate to space fill oxide fin with The another series of process steps of substrate.

Figure 14 D are process charts, and the technological process, which is illustrated, can be used for replacing sacrificial gate with operable metal gates The another series of process steps of pole.

Embodiment

In the following description, some details are illustrated to provide to the thorough of the various aspects of disclosed subject content Understand.However, disclosed subject content still can be realized without these details.In some instances, not yet specifically describe The known features and semiconductor processing of embodiment including subject matter disclosed herein content are in order to avoid fuzzy present disclosure The description of other side.

Unless the context otherwise requires, through specification and appended, wording " including (comprise) " and its Change, such as " including (comprises) " and " including (comprising) " will in opening, comprising being explained in meaning, Exactly it is construed to " include but is not limited to ".

The reference of " one embodiment " or " embodiment " is meaned through specification to combine what the embodiment was described Specific features, structure or characteristic are contained at least one embodiment.Therefore, occurring phrase everywhere through specification " in one embodiment " or " in one embodiment " it is not necessarily all referring to identical aspect.Furthermore it is possible in present disclosure Specific features, structure or characteristic are combined in any appropriate manner in one or more aspect.

The reference of insulating materials or semiconductive material can be included except for illustrating presentation through specification Transistor device specific embodiment material outside various materials.Term " epitaxial silicon compounds " should not narrowly be explained The structure of epitaxial growth is for example limited to Si or SiGe, but be actually construed broadly term " epitaxial silicon compounds " covering Can be from any compound of surface of crystalline silicon epitaxial growth.

Through specification to the conventional film deposition skill for deposited silicon nitride, silica, metal or analog material The reference of art is heavy including such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), Metallo-Organic Chemical Vapor Product (MOCVD), plasma enhanced chemical vapor deposition (PECVD), plasma gas phase deposition (PVD), ald (ALD), technique as molecular beam epitaxy (MBE), plating, electroless plating etc..Example herein by reference to such technique describes tool Body embodiment.However, present disclosure and the reference to some deposition techniques should not necessarily be limited by the deposition technique of description.For example one In a little circumstances, it alternatively can complete to quote CVD description using PVD, or alternatively can realize using electroless plating Specify the description of plating.In addition, the reference to traditional films formation technology can include growth in situ film.For example implement at some In example, it can realize that control oxide grows to required thickness by making silicon face be exposed to oxygen or moisture in by hot cell Degree.

The conventional lithographic techniques for being used to pattern various films known to field of semiconductor fabrication are drawn through specification With the spin coating including being related to photoresist-exposure-development process sequence.Such photolithography sequence need spin coating on a photoresist, By the mask of patterning make the region of photoresist exposed to ultraviolet light and the photoresist that develops to fall exposure (or alternatively not Exposure) region, thus to photoresist transfer just or negative mask pattern.Photoresist mask and then can be for mask pattern is lost It is carved into the film below one or more.Generally, if subsequent etch is relatively shallow, photoresist mask is effective, because Photoresist may be consumed during etch process.Otherwise, photoresist can be for hard mask, and the hard mask can be used again To pattern the film below thicker.

Through specification to known to field of semiconductor fabrication be used for selective removal polysilicon, silicon nitride, silica, Metal, photoresist, the reference of the conventional etch techniques of polyimides or analog material include such as wet chemical etch, reaction Ion (plasma) etching (RIE), cleaning, wet blasting, pre-cleaning, shot blastinog, chemical-mechanical planarization (CMP) etc. this The technique of sample.Example herein by reference to such technique describes specific embodiment.But present disclosure and to some deposition skills The reference of art should not necessarily be limited by the deposition technique of description.In some instances, technology can be with interchangeable as two kinds.For example peel off Photoresist may need to impregnate sample in wet chemistry bath or alternatively to directly injection wet-chemical agent on sample.

Example herein by reference to the FinFET structure produced describes specific embodiment;However, present disclosure and Being cited as of details and sequence to some materials, yardstick and process step is illustrated and should not necessarily be limited by shown disclosure and draw With.

In figure, identical label mark similar features or element.The size for the feature being not necessarily drawn to scale in figure and Relative position.

Figure 1A shows the conventional planar transistor 100 built on silicon substrate 102.The part of conventional planar transistor includes Active region 104, source electrode 106, drain electrode 108, planar conductive raceway groove 110 and grid 112.Unshowned gate-dielectric such as ability Domain is electrically isolated raceway groove and grid as knowing.Active region 104 occupies the top layer of substrate, and the substrate can be adulterated with impurity To create the trap with net negative or net positive charge.When conventional planar transistor 100 is turned on, electric current passes through planar conductive raceway groove 110 flow to drain electrode 108 from source electrode 106.By applying grid voltage by the electric current stream in the control plane conduction of grid 112 It is dynamic.The electric field associated with grid voltage has connects conventional planar transistor 100 if grid voltage exceedes some threshold value Effect.If apply grid voltage be down to below threshold voltage, conventional planar transistor 100 turn off and electric current stop from The flow direction of source electrode 106 drain electrode 108.Because grid 112 is only capable of passing from side (i.e. from the top of planar conductive raceway groove 110) influence plane Guide channel road 110, so the charge leakage into silicon substrate 102 often occurs at channel/substrate knot.

Figure 1B shows the conventional FinFET 150 built on silicon substrate 102.It is similar to device shown in Figure 1A, often Advising the part of FinFET 150 includes active region 104, source electrode 152, drain electrode 154, conduction fin raceway groove 156 and wraparound gate (wrap-around)158.The active region 104 of conventional FinFET 150, which can be adulterated with impurity to create, has net bear Or the trap of net positive charge.When conventional FinFET 150 is turned on, electric current is under the control of wraparound gate 158 through too high (tall) conduction fin raceway groove 156 from the flow direction of source electrode 152 drain electrode 154.Apply the electricity of the value with more than some threshold voltage value Crimping generally rule FinFET 150.If the voltage applied is down to below threshold voltage value, conventional FinFET 150 Shut-off, and electric current stopping flows to drain electrode 154 from source electrode 152.Fin raceway groove 156 is conducted because wraparound gate 158 rings from three silhouettes, It is achieved that the improvement of the conductive properties to conducting fin raceway groove 156 is controlled.It is such improvement control make from conduction fin raceway groove 156 to Although the charge leakage of silicon substrate 102 is not eliminated, it is reduced.Because the current-carrying capacity of fin raceway groove 160 compares planar conductive The current-carrying capacity of raceway groove 110 is much bigger, so the switching characteristic of conventional FinFET 150 is also than conventional planar transistor 100 Switching characteristic be improved.

Fig. 2 shows the semi-conduction fin array 200 of epitaxial growth.Can be configured to 22nm and smaller technology node as Full lining bottom described herein isolates the fin 156 of FinFET transistors.For example the width of fin 156 can be in scope 18-22nm, fin Highly 204 in scope 25-100nm preferred scope 50-75nm.Space 208 between fin 156 can be in the width with fin In the range of identical, such as 18-22nm.

For 22nm fins, the pitch 206 of fin (i.e. from the center of a fin 156 to the center of next fin 156 away from From) by typically in scope 40-48nm and typically twice of the width of fin 156, pitch 206 is also from a space 208 Center to the center in next space 208 distance.Therefore, for 18nm fin width, preferably 36nm pitch 206, but It is that can also use the pitch in scope 30-50nm.Fin 156 with these general sizes and smaller yardstick is used for as now The various embodiments of the present invention that reference picture 3-14D is illustrated.As semiconductor technology develops, yardstick can also change with can Matched with technology.Design characteristics and available geometry can be so that width is in scope 8-20nm and has needed for for such as fin Height in scope 10-200nm.

Fig. 3 is the high level flow chart for describing the elemental motion in manufacture craft 300, and the manufacture craft is used to be designed to Prevent raceway groove to substrate leakage and source/drain to the full isolation FinFET of substrate leakage.302, side wall image is used (SIT) technique is shifted to form multilayer semi-conduction fin array.304, paired groove is formed in a silicon substrate and to this pair Trench fill insulating materials is to be electrically isolated semi-conduction fin and adjacent domain.306, formed and sacrifice grid.308, from semi-conduction The top layer of fin laterally outwardly grown epitaxial layer and be in-situ doped.310, semi-conduction fin and original position are mixed by inserting insulating barrier Diamicton is isolated with substrate.312, replaced with operable grid and sacrifice grid.

Fig. 4 is rudimentary flow of the description for the more specific manufacture craft 400 of the full isolation FinFET described in Fig. 3 Figure.402, inject and deposit to silicon substrate and cover a layer fin stacking.Cover layer include the bilayer of epitaxial growth, i.e. silicon nitride and Undoped silicate glass (USG).404, illusory mandrel structure is formed by patterned nitride and usg film.406, Illusory plug is used for performing sidewall image transfer (SIT) technique to create semi-conduction fin array, then removes plug.408, use Insulating materials is filled in the space between semi-conduction fin to provide isolation between localization fin.410, etch isolated groove and to Isolated groove fills insulation oxide.412, formed in area of grid and sacrifice polysilicon gate and offset spacer, and 414, isotropically grow doping (ISD) epitaxial layer in situ from the top layer of each fin in regions and source/drain.416, Double-deck bottom of epitaxial growth is removed in both area of grid and regions and source/drain, so as to create space.418, to sky Gap fill insulant, such as oxide.420, remove and replaced with operable metal gates and sacrifice polysilicon gate.

Referring to Fig. 5 A-14D, every group of figure is by being presented more comprehensively series of process steps and when completing the sequence of steps The corresponding side view of generation more specifically shows one of processing step from Fig. 4.

The more specific illustrated steps 402 of Fig. 5 A and 5B, according to one embodiment, inject and sink to silicon substrate in this step Product is covered layer fin and stacked.Fig. 5 A show to include the series of process steps of step 502,504,506,508,510 and 512, can held These steps of row cover cap layer stack 514 to be formed shown in Fig. 5 B.Cover cap layer stack 514 includes silicon substrate 516, covers outer respectively Epitaxial growth semi-conduction bottom 518 (such as SiGe (SiGe) or another epitaxial silicon compounds), cover epitaxial growth semi-conduction Top layer 520 (such as silicon or epitaxial silicon compounds), cover silicon nitride cap layer 522 and undoped with amorphous silicate glass (USG) first and second cover sacrifice layer 524 and 526.

502, silicon substrate can receive trap infusion with respectively according to the device of making whether be designed to N-P-N or P-N-P transistors and become to be adulterated with p-type or n-type atom.

504, it can deposit or grow pad oxide layer.506, extension pre-cleaning step can be performed to prepare The surface for epitaxial crystal growth of silicon substrate.Generally, extension pre-cleaning step uses wet chemical process (such as hydrofluoric acid (HF)) come remove all surface oxide (including native oxide and 504 deposition pad oxide layers).

In 508, growth extension semi-conduction bottom 518.Semi-conduction bottom 518 can be made up of SiGe, wherein Ge content Wish about 35%, and thickness wishes about 30nm.The Ge content of semi-conduction bottom 518 can be with scope from about 20% to about 60%.The thickness of semi-conduction bottom 518 can be in the range of about in 20nm-60nm.In addition, 508, by from SiGe semi-conduction The semi-conduction top layer 520 of the epitaxial crystal growth formation epitaxial growth of the top surface of bottom 518.Semi-conduction top layer 520 can be by Silicon or SiGe are made, with the thickness in the range of about 25nm-50nm.

510, extension semi-conduction top layer 520 can be capped with silicon nitride cap layer 522 is covered.Can be with cvd nitride Hard mask of the silicon cap layer 522 for use as the thickness with about 40nm., can be for example using conventional method (such as this area 512 Method commonly used to deposit polycrystalline silicon) cover layer 524 and 526 to deposit the first and second USG sacrifices respectively.First USG is sacrificial Domestic animal covers layer 524 and wishes to have in the range of about the thickness in 20nm-40nm.2nd USG, which sacrifices, covers the hope of layer 526 with model Enclose the thickness in about 80nm-120nm.First and second USG sacrifice cover layer can be with substantially the same, or they can be such as The difference in density or in the change of one or more other film character, this can in subsequent processing steps pin Different etch-rates are produced to two usg films.

The more specific illustrated steps 404 of Fig. 6 A and 6B, form sacrifice plug to be supported on unconventional side wall figure in this step Sidewall spacer as being used as mask arrangement in transfer (SIT) technique.SIT techniques can be for patterning narrow and/or near spacing Structure is particularly useful.Fig. 6 A show to include the series of process steps of step 602,604 and 606, can perform these steps with shape Into sacrifice (illusory) plug 614 (showing three) in Fig. 6 B.Each plug 614 is the paired sidewall spacer 628 of support Patterning undoped with amorphous silicate glass (USG) structure.In SIT techniques, side wall will be shifted to the width of multilayer fin The width of sept 628 rather than using mask to pattern fin.The width of gained multilayer fin is wished in an example embodiment Hope in the range of about in 3-15nm.In addition, plug width 630 determines in the exemplary embodiment to wish in the range of about in 10-50nm Spacing between fin.Similarly, the uniformity of sidewall spacer 628 and plug 614 determines fin in fin array and fin spacing respectively Uniformity.

602, conventional lithographic and etch process can be used pattern undoped with amorphous silicate glass (USG) Sacrifice layer 526 is covered to form plug 614.Because conventional lithographic is known to semiconductor processes art personnel, so Do not express in figure, but it will be sketched.Conventional lithographic needs spin coating on a photoresist, makes photoresist by the mask of patterning Part is exposed to the unexposed portion of ultraviolet light and the photoresist that develops to fall, thus to photoresist transfer mask pattern.Photoresist Mask and then can be for pattern is etched into the layer below one or more.Generally, if subsequent etch is relatively shallow, Photoresist mask can be then used, because photoresist may be consumed during etch process.Such photoetching can be used Glue mask and the 2nd USG sacrifice layers are patterned to the first selective wet etching of USG sacrifice layers or RIE chemical agents 526.It is alternatively possible to use the timed-etch for being wherein subjected to the first USG sacrifice layers 524 of part consumption.

604, conventional deposition technique depositing conformal silicon nitride layer (not shown) on USG structures 526 can be used.

606, it can perform and cover (maskless) wet method or dry etching to remove the uniform thickness of nitride layer, because This forms paired sidewall spacer 628.In such technique, plug 614 can be used to be used as etching stopping layer or can To be timed to etch process.It is temporary transient because the first USG covers sacrifice layer 524 and plug 614, it is possible to can connect By the non-optimal etching selectivity for causing part to consume these layers.According to the etch process used, sidewall spacer 628 can be from The top surface of plug 614 slightly or significantly tilts (slope away).

The more specific illustrated steps 406 of Fig. 7 A and 7B, in this step by cover cap layer stack 514 shift sidewall spacer 628 area of coverage (image) carrys out patterned multilayer fin array.Fig. 7 A show to include the technique step of step 702,704,706 and 708 Rapid sequence, can perform these steps to form the multilayer fin array 714 (showing six) in Fig. 7 B.According to one embodiment, Each multilayer fin 716 includes the extension SiGe bottom 718 of patterning, figure 7 illustrates for by the nitridation of the patterning remained The epitaxial silicon top layer 720 for the patterning that silicon cap 722 is covered.

702, after sidewall spacer 628 is formed, can by using to silicon nitride sidewall spacers 628 highly Selective wet etching or dry etching are to etch USG so as to removing illusory plug 614.For removing plug 614 Then etchant also will often remove the first USG sacrifice layers 524, except it is in addition to protected below sidewall spacer 628.

704, SIT techniques can be performed, following layer (524,522,520 and 518) are being etched in the process Residue below 10nm sidewall spacer 628 is used in the exemplary embodiment as hard mask during full stacking.Turn in example wall image When moving completion, the gained multilayer fin 716 vertically extended from silicon substrate 516 as shown in fig.7b will have and sidewall spacer 628 area of coverage approx identical width and uniformity.Therefore, warp-wise fin shifts the image of sidewall spacer.

706, in fin-shaped after, can use Conventional wet etch agent (such as hot phosphoric acid or respectively to body silicon serve as a contrast Bottom 516 and the selective another etchant of epitaxial silicon bottom and top layer 718 and 720) cover the surplus of multilayer fin 716 to remove Remaining sidewall spacer 628.

708, the first USG sacrifice layers 524 can be for example removed using the chemical agent based on HF is used as residual USG caps Layer (not shown) remaines in the part above of multilayer fin 716, therefore leaves the multilayer fin 716 including silicon nitride cap 722.

The more specific illustrated steps 408 of Fig. 8 A and 8B, in this step can between multilayer fin 716 deposition of insulative material with Form the multilayer fin array 814 partly isolated.Fig. 8 A show the technique for including step 802,804,806,808,810 and 812 Sequence of steps, can perform these steps to form the multilayer fin array 814 (showing six fins) partly isolated in Fig. 8 B. According to one embodiment, multilayer fin 716 isolates packing material 816 between the fin localized and tetraethyl orthosilicate (TEOS) is derivative Oxide skin(coating) or TEOS818 separation.

802, packing material 816, such as oxide can be locally isolated to the space filling between multilayer fin 716.

804, chemical-mechanical planarization (CMP) technique stopped on nitride cap 722 then can be used to come flat Change many fin arrays of filling.

806, it can use to the selective wet chemical etch agent at least in part of following epitaxial silicon top layer 720 Make a return journey silicon nitride cap layers 722.

808, it can use to the selective etchant of silicon (such as wet chemical etching based on HF) come the part that is recessed Isolate packing material 816.The final thickness for being locally isolated packing material 816 of depression is wished so that what is be recessed is locally isolated filling The top surface of material 816 intersects at the point in epitaxial Germanium SiClx bottom 718 with multilayer fin 716.

810, thin TEOS layers 818 can be conformally deposited on many fin arrays 814 (such as less than about 10nm is thick). TEOS layers 818 will act as gate-dielectric.

812, the packing material 816 of depression can be replaced with deposited pad nitride layer 820 and in multilayer fin battle array The elevation-over extension of row 814.Pad nitride layer 820 can be used as hard mask to form isolated groove.

The more specific illustrated steps 410 of Fig. 9 A and 9B, form isolation trench on the either side of many fin arrays 814 in this step Groove is to isolate multilayer fin array 914 and adjacent domain.Fig. 9 A show to include the work of step 902,904,906,908,910 and 912 Skill sequence of steps, can perform the fin array 914 that these steps are laterally insulated to be formed shown in Fig. 9 B.

902, pad nitride layer 820 can be patterned using conventional lithographic techniques as described above, with Just the region of many fin arrays 814 and exposure beyond the end of many fin arrays 814 is covered.

904, pad nitride then can be used during the etch process for being locally isolated packing material 816 and silicon is removed Nitride layer 820 is as hard mask to create deep trench in silicon substrate 516.It is desirably each for the etch process that creates isolated groove Anisotropy plasma etching.

906, insulator can be filled to deep isolated groove.Insulator may, for example, be silica, such as it is high in length and breadth Than technique (HARPTM) packing material 916.It can use from Santa Clara, California Applied The proprietary technique performed in available specialized chemical vapor deposition (CVD) equipment of Materials, Inc. is such to deposit HARPTMPacking material 916.

908, the CMP stopped on pad nitride layer 920 can be used to planarize HARPTMPacking material 916。

910, HF can be used to impregnate come the HARP that is recessedTMPacking material 916, then in 912 nitride removal step Suddenly (such as hot phosphoric acid wet etching).In the fin array 914 that gained example is laterally insulated from, as shown in fig. 9b, HARPTMFill out Fill the side of tying of two silicon epitaxial layers 718 and 720 of the height of material 916 below the height of fin but in fin.

The more specific illustrated steps 412 of Figure 10 A, 10B and 10C, form sacrifice grid and sept in this step.Figure 10 D Show to include the series of process steps of step 1002,1004 and 1006, these steps can be performed to be formed in area of grid It is covered in the sacrifice grid 1018 (Figure 10 A) above the array 914 for six fins being laterally insulated from.Gained is shown in fig 1 oc The perspective view of FinFET arrays 1014 (showing only two fins).

1002, sacrificing grid 1018 can conformally be deposited on the fin array 914 being laterally insulated from, and and fin Substantially orthogonal to ground alignment.Three sides of the grid 1018 therefore with each multilayer fin are sacrificed to abut.Sacrificing grid 1018 can basis For example it is made up for the technology that forms conventional planar transistor grid of polysilicon.Sacrificing grid 1018 is.1004, Ke Yichen Product covers silicon nitride hardmask layer 1020.Sacrifice grid 1018 and silicon nitride hardmask layer 1020 be only formed in area of grid, It is not formed in regions and source/drain.This can be realized by deposition mas deposition materials.Or film can be covered and is deposited on On both grid and regions and source/drain, then it is selectively removed (Figure 10 B) from source electrode and drain region so that sacrificial Both domestic animal grid 1018 and silicon nitride hardmask layer 1020 are only remained in area of grid (Figure 10 A).

Figure 10 B therefore substantially Fig. 9 B reproductions.Figure 10 A are the edges as shown in the perspective view 1014 presented in Figure 10 C The side view of FinFET arrays of the line of cut A-A ' in area of grid.Figure 10 B are the perspective views 1014 as presented in Figure 10 C Shown in FinFET arrays along line of cut B-B ' in regions and source/drain side view.Conformal along A-A ' formation Before grid, Figure 10 B are the identical structures 914 occurred in figures 9 b and 9.

1006, another Common deposition and patterning (photoetching and etching) can be used to circulate in and sacrifice appointing for grid structure Offset spacer is formed on one.Sept for example can be made up of silicon nitride.However, sept occurs in fig 1 oc, come from A-A ' sectional drawing and sectional drawing from B-B ' do not intersect with sept, therefore they are not come across shown in Figure 10 A or 10B In side view.

The more specific illustrated steps 414 of Figure 11 A, 11B and 11C, are epitaxially grown original from semi-conduction top layer 520 in this step Position doping (ISD) layer.Figure 11 D show to include the series of process steps of step 1102,1104 and 1106, can perform these steps To form the fin array 1112 (Figure 11 B) of doping in regions and source/drain.The fin array 114 of doping is shown in Figure 11 C Perspective view.

1102, N2H2 gases can be used to complete the first pre-cleaning.

1104, second pre-cleaning similar to the pre-cleaning being known in the art as before nickle silicide is formed can be completed SiCoNi.Pre-cleaning step 1102 and 1104 removes native oxide, impurity etc. to allow epitaxial crystal growth not from silicon face Occurred with hindering by surface contaminant.

1106, it outwards can be epitaxially grown crystalline silicon to be formed from the epitaxial silicon top layer 720 of the patterning of multilayer fin Doping (ISD) structure 1108 in situ of facet.Can be by introducing impurity (such as boron or phosphorus) during epitaxial growth come real Existing doping in situ.If maintaining epitaxial growth, the ISD for the facet extended from the top layer of fin through fully long time interval Structure 1108 can grow the epitaxial layer contacted with the oxide 816 formed with being recessed together.

The more specific illustrated steps 416 of Figure 12 A, 12B and 12C, remove the bottom of conduction fin raceway groove with top in this step Space is created between portion's semiconductive material and substrate.Figure 12 D show to include step 1202 and 1204 series of process steps, can be with These steps are performed to form area of grid space 1210 (Figure 12 A) and regions and source/drain space 1212 (Figure 12 B).In figure The perspective view 1214 to be formed after space is shown in 12C.

1202, another SiCoNi pre-cleanings can be performed to contribute to the more effective film in subsequent step to remove.

1204, can example as used in the dipping in hydrochloric acid solution from both area of grid and regions and source/drain In fin extension bottom 718 is removed to create area of grid space 1210 and regions and source/drain space 1212.Extension top layer 720 keep being suspended in above substrate, but anchor to grid structure (i.e. along fin) in vertical direction.

In alternative process flow, the epitaxial growth of the ISD structures 1108 of facet shown in Figure 11 B can betide to be formed After area of grid space 1210 and regions and source/drain space 1212.

The more specific illustrated steps 418 of Figure 13 A, 13B and 13C, in this step can be to area of grid space 1210 and source Pole/fill oxide of drain region space 1212 is with physically and electrically insulated conductive fin raceway groove and substrate.Figure 13 C show to include step 1302nd, 1304,1306 and 1308 series of process steps, can perform these steps to be formed in area of grid (Figure 13 A) The substrate isolation fin channel array 1310 of the extension of substrate isolation fin raceway groove 1312 into regions and source/drain (Figure 13 B).In figure Show that full lining bottom isolates the perspective view 1310 of fin raceway groove in 13C.

1302, the superficial growth titanium dioxide in both grid and regions and source/drain from silicon substrate 516 can be passed through Silicon fills area of grid space 1210 and regions and source/drain space 1212.Then in regions and source/drain, Ke Yisheng Long or deposition additional oxide to slightly gate electrodes silicon nitride spacer and hard mask elevation-over height.

1304, conventional annealing technique can be performed in the ISD structures 1108 of the facet in regions and source/drain to expand Dissipate dopant.

1306, the conventional CMP of polishing stop layer can be for example may be used as using wherein silicon nitride hardmask layer 1020 Technique polishes oxide.

1308, plasma etch process (can be directed downwardly towards) by using anisotropy and remove silicon nitride from grid Hard mask 1020 and do not remove silicon nitride sidewall spacers, be then Conventional wet chemical cleanup step.

The more specific illustrated steps 420 of Figure 14 A, 14B and 14C, are replaced with operable grid sacrifice grid in this step.This The technique of sample is generally referred to by those skilled in the art as replacing metal gates (RMG) technique.Figure 14 D show to include step 1402,1404, 1406th, 1408 and 1410 series of process steps 420, can perform these steps to form operable grid in area of grid Structure 1412 (Figure 14 A).The perspective view 1414 of operable grid structure 1412 is shown in Figure 14 C.

1402, for example it can be come using the wet chemical etchants for selectively corroding silicon nitride and silica silicon Remove and sacrifice polysilicon gate.Or can be used in same process step two parts (two-part) dry method etch technology with Remove polysilicon gate and gate-dielectric (1404).

1406, can be etched back as shown in Figure 14 B oxide 1318 in regions and source/drain to extension top layer 720 height overlapped.

Conformally deposition has greater than about 4.0 Gao Jie on 1408, extension top layer 720 that can be in area of grid The high k gate-dielectrics 1418 of electric constant (k).

1410, operable metal gates 1420 can be deposited in area of grid and also in regions and source/drain It is used as the metal contact layer (i.e. extension top layer 720) for going to isolation fin.To sacrifice grid 1018 it is similar, operable metal gates with The three sides adjoining of each multilayer fin so that the potential applied to grid can be from each aspect effect in three directions in fin The electric current of flowing.

Various embodiments described above can be combined to provide more embodiments.It is quoting in this manual and/or All United States Patent (USP)s for being enumerated in application data form, U.S. Patent Application Publication, U.S. Patent application, foreign patent, foreign country Patent application and non-patent disclose and are fully incorporated in this by reference.Can be such as in order to various patents, application and openly Concept and must as modification embodiment aspect to provide more embodiments.

Although it will be understood that describing the specific embodiment of present disclosure for exemplary purposes herein, can carry out It is various modification and without departing from the spirit and scope of present disclosure.Thus, present disclosure is except by appended claims It is unrestricted outside limitation.

These and other change can be carried out to embodiment according to description described in detail above.In general, in appended right It is required that in, it should not explain that the term used makes claim be limited to disclosed specific embodiment in the specification and in the claims, But the equivalents that these terms include being possible to embodiment and such claim has the right to have should be explained Complete scope.Thus, claim is not limited by the disclosure.

Claims (20)

1. a kind of method for forming FinFET transistors on a silicon substrate, methods described includes:
Dopant is injected to the silicon substrate;
The raised multilayer fin array vertically extended from the silicon substrate is formed, the raised multilayer fin at least includes bottom half and passed Lead material and top semiconductive material;
Deposition of insulative material is to provide isolation between local fin between the fin;
Insulated trench is formed to be electrically isolated the FinFET transistor AND gates adjacent domain;
Form the sacrifice for being covered in above the raised multilayer fin array and being aligned with the raised multilayer fin ary Quadrature Grid, three sides of the sacrifice grid and each multilayer fin are abutted, the portion being located at below the sacrifice grid of each multilayer fin It is allocated as conduction fin channel operation;
The doped epitaxial in situ layer contacted with the top semiconductive material is formed on the opposite side of the sacrifice grid;
The bottom semiconductive material is removed with the top semiconductive material and the silicon substrate from the conduction fin raceway groove Between form space, the space provides the physical separation between the conduction fin raceway groove and the silicon substrate;
To the space fill oxide so that the conduction fin raceway groove is electrically insulated with the silicon substrate;And
The sacrifice grid is replaced with operable grid.
Side wall image is used when forming the raised multilayer fin array 2. according to the method described in claim 1, being additionally included in Shifting process patterns the array.
3. method according to claim 2, in addition to formation sacrifice plug and are used as the one of the sidewall image transfer technique Part.
4. method according to claim 3, wherein the sacrifice plug includes amorphous silicon material.
5. according to the method described in claim 1, wherein the sacrificial gate pole includes polysilicon and the operable grid bag Include metal.
6. method according to claim 5, is additionally included in and is sunk between the operable grid replacement sacrificial gate crisis Additional metal is accumulated to form source contact and drain contact.
7. according to the method described in claim 1, wherein the operable grid is included by with the dielectric constant more than 4.0 The dielectric layer that material is made.
8. according to the method described in claim 1, wherein the bottom semiconductive material is the SiGe of epitaxial growth, and institute State the silicon that top semiconductive material is epitaxial growth.
9. a kind of full isolation FinFET transistors on a silicon substrate, the transistor includes:
Fin channel array is conducted, is suspended on the silicon substrate and is spaced apart by insulating barrier with the silicon substrate;
Doped epitaxial layer in situ, is contacted with the part of the conduction fin channel array, and the doped epitaxial layer in situ is suspended in institute State on silicon substrate and be spaced apart by insulating barrier with the silicon substrate;
Conformal gate, is covered in above the conduction fin channel array, the conformal gate is operable to respond in application Electric current flowing in the voltage control conduction fin raceway groove;And
Paired insulated trench, is abreast aligned with the conduction fin raceway groove.
10. FinFET transistors according to claim 9, wherein the conformal gate is included with the dielectric more than 4.0 The dielectric layer of constant and the body grid material including metal.
11. FinFET transistors according to claim 9, the trap infusion being additionally included in the silicon substrate and bag injection One or more infusion in thing.
12. FinFET transistors according to claim 9, wherein the conduction fin channel array includes the silicon of epitaxial growth Material.
13. FinFET transistors according to claim 9, wherein the insulating barrier is oxide.
14. FinFET transistors according to claim 9, wherein the doped epitaxial layer in situ and the conduction fin raceway groove The contact of the part beyond the conformal gate of array.
15. a kind of method for forming the FinFET transistors isolated with silicon substrate, methods described includes:
Form semi-conduction fin array;
Insulated trench is formed to be electrically isolated the FinFET transistor AND gates adjacent domain;
The conformal gate being covered in above the semi-conduction fin array is formed, the conformal gate is operable as in response to application Electric current in voltage, control conductive fin raceway groove;
The doped epitaxial layer with the semi-conduction fin array contact is formed beyond the conformal gate;And
The semi-conduction fin array and doped epitaxial layer are isolated with the silicon substrate with insulating barrier.
16. method according to claim 15, wherein the semi-conduction fin array includes top epitaxial layer and bottom extension Layer.
17. method according to claim 16, wherein isolating the semi-conduction fin array needs to be replaced with the insulating barrier The bottom epitaxial layer.
18. method according to claim 15, wherein the insulating barrier is silica.
19. method according to claim 15, wherein the conformal gate is also included with the dielectric constant more than 4.0 Dielectric layer and metal level.
20. a kind of electric isolution transistor formed on a silicon substrate, the transistor includes:
One or more semi-conduction fin raceway groove;
Doped epitaxial layer, is contacted with the semi-conduction fin raceway groove;
Conformal metallic grid, is covered in above one or more of semi-conduction fin raceway grooves, and the grid can be used to ring The electric current flowing in the semi-conduction fin raceway groove should be controlled in the voltage of application;
For the device for isolating the semi-conduction fin raceway groove with adjacent domain;And
For by the semi-conduction fin raceway groove and the doped epitaxial layer isolate with the silicon substrate so as to prevent to the silicon lining The device of charge leakage in bottom.
CN201310489429.7A 2012-12-21 2013-10-12 Full lining bottom isolates FINFET transistors CN103887172B (en)

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