CN103871463B - Phase change memory array stacked structure and operating method thereof - Google Patents

Phase change memory array stacked structure and operating method thereof Download PDF

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Publication number
CN103871463B
CN103871463B CN201410115086.2A CN201410115086A CN103871463B CN 103871463 B CN103871463 B CN 103871463B CN 201410115086 A CN201410115086 A CN 201410115086A CN 103871463 B CN103871463 B CN 103871463B
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phase change
described
change memory
block
stacked structure
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CN201410115086.2A
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Chinese (zh)
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CN103871463A (en
Inventor
李喜
陈后鹏
宋志棠
蔡道林
王倩
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中国科学院上海微系统与信息技术研究所
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Abstract

The invention provides a phase change memory array stacked structure and an operating method thereof. The phase change memory array stacked structure at least comprises multiple phase change memory blocks, a global bit line, local bit lines, block bit lines, first strobe gates and second strobe gates, wherein each phase change memory block comprises at least four columns of phase change resistors; the phase change resistors in each column are respectively correspondingly connected with a block bit line; at least two block bit lines are respectively connected with a second strobe gate; at least two second strobe gates are connected to the same local bit line; at least two local bit lines are connected to the global bit line through a first strobe gate. According to the phase change memory array stacked structure, all the block bit lines are connected together in a unified mode through the global bit line, and the maximum load of the global bit line is only determined by the lengths of the block bit lines in the memory blocks, so that parasitic capacitance is greatly reduced. Therefore, large signal delay and high power consumption generated in a high-capacity phase change memory are avoided.

Description

Phase change memory array stacked structure and its operational approach

Technical field

The present invention relates to a kind of technical field of semiconductors, more particularly to a kind of phase change memory array stacked structure and its Operational approach.

Background technology

Phase transition storage(Phase Change Memory, PCM, PCRAM)Generally referred to as it is based on certain chalcogenide compound The random access memory of thin film.It is a kind of new nonvolatile memory, is considered most possibly to substitute in the near future Flash memory(Flash)Become main flow nonvolatile memory.This is because its operating voltage is low, and reading speed is fast, can with bit manipulation, Write wiping speed and be significantly faster than flash memory, and fatigue properties are more excellent, wiping is write in the circulation being capable of more than one hundred million times, and manufacturing process is simple And compatible with present ripe CMOS technology such that it is able to be easy to for its memory element to be contracted to less size.

Single phase-change memory cell is typically made up of phase change resistor and gating unit.Described phase change resistor is by phase change memory Material cell is constituted.Wherein, the operation to single described phase change resistor includes:

Write/erase operates:Mainly electric pulse is inputted by gating unit, thus producing Joule heat to make phase-change storage material In amorphous state(Material is in high-impedance state)With crystalline state(Material is in low resistive state)Between occur reversible transition and realize writing of data Enter/wipe;

Read operation:Mainly pass through gating unit input current, then the state by measuring resistance realizes data Read.

Phase change memory array and peripheral control electricity are generally comprised by the phase transition storage that several phase-change memory cells form Road.Phase change memory array is made up of several phase-change memory cells, is suitable to data storage;Peripheral control circuits are suitable to drive phase transformation Storage array works, and peripheral circuit here mainly includes reading circuit, also has some companies to incite somebody to action in the design of phase transition storage Specially devise the erasable circuit of memory block, and gate specific phase-change memory cell and operated.

In jumbo phase transition storage, also ratio is larger for phase change memory array, there is larger parasitic capacitance.So, Drive the phase transition storage operation of larger capacity, not only can produce larger signal lag, and also bring along bigger Power consumption.In traditional method for designing, in order to provide memory read/write speed faster, by the phase in large-capacity phase change memorizer If becoming storage array to be divided into less memory block BLOCK of dry capacity, need design periphery accordingly for each memory block BLOCK Circuit.So, because each storage array can have the peripheral circuit of itself in large-capacity phase change memorizer, correspondingly, these Peripheral circuit just occupies substantial amounts of chip area.Make phase change memory chip area excessive, cost.

Therefore, it is necessary to be optimized to phase change memory array structure, thus realizing prolonging not increasing memory signals When while lift the ratio of storage array occupied area in memory to greatest extent, thus reducing chip cost.

Content of the invention

The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of phase change memory array stacking Structure and its operational approach, for solving in prior art the ratio of lifting storage array occupied area in memory, thus Reduce the problem of chip cost.

For achieving the above object and other related purposes, the present invention provides a kind of phase change memory array stacked structure, institute State phase change memory array stacked structure at least to include:

Some phase change memory blocks, global bit line, this ground bit lines, block bit line, the first storbing gate and the second storbing gate;

Wherein, every piece of described phase change memory block includes at least four row phase change resistors, and phase change resistor described in each column is respectively It is correspondingly connected to a block bit line, described piece of bit line connects second storbing gate respectively, at least two second storbing gates connect To same basic ground bit lines, at least two described ground bit lines are connected to described overall situation position by described first storbing gate Line.

Preferably, described phase change memory array stacked structure also includes block wordline, described phase change memory array stacking Structure also includes at least two row phase change resistors, and described phase change resistor of often going is connected respectively to a block wordline.

Preferably, one end of described phase change resistor is connected by each column and connects to corresponding second storbing gate, and the other end is pressed Often row is connected and connects to corresponding wordline.

Preferably, described phase change memory array stacked structure includes at least two row phase change memory blocks, each column phase change memory Corresponding this ground bit lines connecting of every piece of phase change memory block in block are commonly connected to same first storbing gate.

Preferably, described phase change memory array stacked structure also includes the first discharge cell and the second discharge cell, institute State the connection of block bit line and the ground connection that the first discharge cell each phase change resistor corresponding is located, be suitable to correspond in described phase change memory block Electric discharge when not being strobed of block bit line, every one second storbing gate of described second discharge cell correspondence connects and is grounded, and is suitable to Discharge when described ground bit lines are not strobed.

Preferably, one end of described each piece of bit line connects described second storbing gate, and the other end connects the second discharge cell, Described second discharge cell is a nmos pass transistor, and its drain electrode is connected with described piece of bit line, its source ground.

Preferably, one end of described each phase change resistor connects described piece of bit line, and it is single that the other end connects described first electric discharge Unit, described first discharge cell is a nmos pass transistor, and its drain electrode is connected with described phase change resistor, its source ground.

Technical scheme additionally provides a kind of operational approach of phase change memory array stacked structure, including:

Phase change memory array stacked structure as above is provided;

There is provided the second gating gate signal to corresponding described second storbing gate of the phase change memory block being strobed;

There is provided block selected signal to the phase change memory block being strobed;

The institute that first gating gate signal is connected to the phase change memory block being strobed is provided under the control of block selected signal State the first storbing gate;

Block wordline selected signal is provided under the control of block selected signal, controls and need selected block wordline to choose.

Preferably, described first gating signal only gates the first storbing gate described in, and described second gating signal only gates Second storbing gate described in one;Described piece of wordline selected signal only gates one piece of wordline.

As described above, the phase change memory array stacked structure of the present invention and its operational approach, have the advantages that:

In the phase change memory array stacked structure of technical scheme offer and its operational approach, selected piece of word The phase change resistor of line and selected piece of bit line infall is selected, and connects to global bit line, and not selected bit line then passes through Second level discharge cell and first order discharge cell are connected to the ground, thus completing the decoding process of memory element, simultaneously any In the moment, most only one of which memory element are selected, and not selected memory element place bit line is all connected to ground, And then achieve the protection to unselected cells.

Brief description

Fig. 1 to Fig. 2 be shown as in embodiments of the invention provide phase change memory array stacked structure schematic diagram.

Component label instructions

BLOCK phase change memory block

GBL global bit line

This ground bit lines of LBL

BBL block bit line

SLBL first storbing gate

SBBL second storbing gate

BWL block wordline

DBBL first discharge cell

DLBL second discharge cell

Specific embodiment

Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from Carry out various modifications and changes under the spirit of the present invention.

Refer to Fig. 1 to Fig. 2.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, only shows the assembly relevant with the present invention rather than then according to package count during actual enforcement in schema Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its Assembly layout kenel is likely to increasingly complex.

Described phase change memory array stacked structure at least includes:

Some phase change memory block BLOCK are (including but not limited to:BLOCK_0 ... ..., BLOCK_q), global bit line GBL, this Ground bit lines LBL are (including but not limited to:LBL0... ..., LBLp), block bit line BBL(Including but not limited to:BBL00、BBL01... ..., BBL0(n-1)、BBL0n), the first storbing gate SLBL (including but not limited to:SLBL0... ..., SLBLp)With the second storbing gate SBBL (including but not limited to:SBBL00、SBBL01);

Wherein, every piece of described phase change memory block BLOCK includes at least four row phase change resistors, each column phase change resistor connect to Same bit line BBL, at least two described phase change resistors of row pass through connected block bit line BBL and are commonly connected to same second gating Door SBBL, at least two second storbing gates SBBL are connected to ground bit lines LBL, and this ground bit lines LBL described at least two leads to Cross the first storbing gate SLBL described in connect to described global bit line GBL.

In addition, combining Fig. 2 reference, the described phase change memory array stacked structure that the present embodiment provides also includes:Block word Line BWL(Including but not limited to:BWL00~BWL0m), the first discharge cell DBBL(Including but not limited to:DBBL00~DBBL01)With Second discharge cell DLBL(Including but not limited to:DLBL0~DLBLp).

One end of described each column phase change resistor is connected by each column and connects to block bit line BBL, and one end of block bit line BBL connects Second storbing gate SBBL, the other end connects the second discharge cell DLBL, and described second discharge cell is a nmos pass transistor, its leakage Pole is connected with described piece of wordline BBL, its source ground.

One end that described phase change resistor is not connected to block bit line BBL is also associated with one first discharge cell DBBL, and described One discharge cell ground connection.In the present embodiment, described first discharge cell DBBL is a nmos pass transistor, described nmos pass transistor Source ground.And often the phase change resistor gone is connected with the drain electrode of described first discharge cell DBBL, then by described nmos pass transistor Grid connect to corresponding piece of wordline BWL of every row.Described first discharge cell DBBL can be in described phase change resistor place block When bit line is not gated on, discharged, to protect the phase change resistor being not gated on.

And, the phase change memory block in the described phase change memory array stacked structure that the present embodiment provides includes at least two Row, corresponding this ground bit lines LBL of the phase change memory block BLOCK in each column is connected to one first storbing gate SLBL.

In addition, the present embodiment also provides a kind of operational approach of above-mentioned phase change memory array stacked structure, including:

Second gating gate signal is provided, controls and need selected this ground bit lines LBL to connect to global bit line GBL;Enter one Step ground, not selected ground bit lines LBL are connected to the ground by second level discharge cell DLBL.

Block selected signal is provided, controls and need selected phase change memory block BLOCK activation;

First gating gate signal is provided under the control of block selected signal, controls and need selected block bit line BBL to connect To this ground bit lines LBL;Further, not selected piece of bit line BBL is connected to the ground by first order discharge cell DBBL.

Block wordline selected signal is provided under the control of block selected signal, controls and need selected block wordline BWL to choose.

Wherein, described first gating signal only gates the first storbing gate SLBL described in, and described second gating signal is only selected Second storbing gate SBBL described in logical one;Described piece of wordline selected signal only gates one piece of wordline BWL.

In the present embodiment, described second gating gate signal can be by second level bit line decoder(Not shown)Produce, described Block selected signal can be by first order bit line decoder(Not shown)Produce, described first gating gate signal can be translated by first order bit line Code device(Not shown)Produce, described piece of wordline selected signal can be by block word-line decoder(Not shown)Produce.Wherein, the first level Line decoder and block word-line decoder are controlled by block selected signal respectively.In other embodiments, described second storbing gate letter Number, block selected signal, first gating gate signal or/and block wordline selected signal can also by other those skilled in the art institute The technical approach of solution provides.

The phase transition storage stacked structure that the present embodiment provides passes through global bit line GBL and connects unified for all pieces of bit line BBL Be connected together, during the selected execution read-write operation of any one memory element in array, the maximum load of global bit line only by The block bitline length of single BLOCK determines, thus greatly reducing the generation of parasitic capacitance, thus avoiding jumbo phase The larger signal lag that can produce in transition storage and larger power consumption.

And by controlling the first storbing gate and the in the operational approach of phase transition storage stacked structure that provides of the present embodiment Two storbing gates, with selected one piece of wordline BWL, choose one piece of bit line BBL so that selected block wordline BWL and block bit line simultaneously The phase change resistor of BBL infall is selected, and connects to global bit line GBL, and not selected piece of bit line BBL is then put by second Electric unit DLBL and the first discharge cell DBBL is connected to the ground, thus completing the decoding process of memory element, simultaneously when any Carve, most only one of which memory element are selected, and not selected memory element place bit line is all connected to ground, enters And achieve the protection to unselected cells.

In the phase transition storage stacked structure of the present embodiment offer and its operational approach, many by designing multistage transmission goalkeeper Individual phase change memory block BLOCK is stacked, and in each operation, most only one of which phase change memory block BLOCK are selected, entirely Parasitic capacitance on office bit line GBL is to be determined by selected that phase change memory block BLOCK.Therefore the present embodiment provides Although to be connected to total Number of Storage Units in global bit line GBL larger in phase transition storage stacked structure and its operational approach, Namely the capacity of whole phase transition storage is larger, and the capacity of phase change memory block BLOCK is consistent with traditional design, but always The quantity of whole phase transition storage peripheral circuit is decreased on body, thus decreasing chip area.

In sum, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.

Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as All equivalent modifications becoming or change, must be covered by the claim of the present invention.

Claims (8)

1. a kind of phase change memory array stacked structure is it is characterised in that described phase change memory array stacked structure at least wraps Include:
Some phase change memory blocks, global bit line, this ground bit lines, block bit line, the first storbing gate and the second storbing gate;
Wherein, every piece of described phase change memory block includes at least four row phase change resistors, and described in each column, phase change resistor corresponds to respectively Connect to a block bit line, described piece of bit line connects second storbing gate respectively, and at least two second storbing gates are connected to One basic ground bit lines, at least two described ground bit lines are connected to described global bit line by described first storbing gate;
Described phase change memory array stacked structure includes at least two row phase change memory blocks, every piece of phase in each column phase change memory block Become corresponding this ground bit lines connecting of memory block and be commonly connected to same first storbing gate.
2. phase change memory array stacked structure according to claim 1 it is characterised in that:Described phase change memory array Stacked structure also includes block wordline, and described phase change memory array stacked structure also includes at least two row phase change resistors, often row institute State phase change resistor to be connected respectively to a block wordline.
3. phase change memory array stacked structure according to claim 2 it is characterised in that:One end of described phase change resistor It is connected by each column and connects to corresponding second storbing gate, the other end is connected and is connected to corresponding wordline by often row.
4. phase change memory array stacked structure according to claim 1 it is characterised in that:Described phase change memory array Stacked structure also includes the first discharge cell and the second discharge cell, and described first discharge cell corresponds to each phase change resistor and is located Block bit line connect and be grounded, be suitable to when described corresponding piece of bit line of phase change memory block is not strobed electric discharge, described second Every one second storbing gate of discharge cell correspondence connects and is grounded, and is suitable to the electric discharge when described ground bit lines are not strobed.
5. phase change memory array stacked structure according to claim 4 it is characterised in that:The one of described each piece of bit line End connects described second storbing gate, and the other end connects the second discharge cell, and described second discharge cell is a nmos pass transistor, its Drain electrode is connected with described piece of bit line, its source ground.
6. phase change memory array stacked structure according to claim 5 it is characterised in that:Described each phase change resistor One end connects described piece of bit line, and the other end connects described first discharge cell, and described first discharge cell is a nmos pass transistor, Its drain electrode is connected with described phase change resistor, its source ground.
7. a kind of operational approach of phase change memory array stacked structure is it is characterised in that include:
Phase change memory array stacked structure any one of claim 1 to 6 is provided;
There is provided the second gating gate signal to corresponding described second storbing gate of the phase change memory block being strobed;
There is provided block selected signal to the phase change memory block being strobed;
There is provided under the control of block selected signal that the first gating gate signal is connected to the phase change memory block being strobed described the One storbing gate;
Block wordline selected signal is provided under the control of block selected signal, controls and need selected block wordline to choose.
8. phase change memory array stacked structure according to claim 7 operational approach it is characterised in that:
Described first gating signal only gates the first storbing gate described in, and described second gating signal only gates the second choosing described in Open gate;Described piece of wordline selected signal only gates one piece of wordline.
CN201410115086.2A 2014-03-26 2014-03-26 Phase change memory array stacked structure and operating method thereof CN103871463B (en)

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