CN103870426A - High-performance and intermediate-frequency digitizer - Google Patents
High-performance and intermediate-frequency digitizer Download PDFInfo
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- CN103870426A CN103870426A CN201310691838.5A CN201310691838A CN103870426A CN 103870426 A CN103870426 A CN 103870426A CN 201310691838 A CN201310691838 A CN 201310691838A CN 103870426 A CN103870426 A CN 103870426A
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Abstract
The invention discloses a high-performance and intermediate-frequency digitizer. The high-performance and intermediate-frequency digitizer comprises an FPGA (Field Programmable Gate Array), wherein the FPGA is respectively connected with an ADC (Analog-Digital Conversion) data acquisition module and a clock distribution module; the ADC data acquisition module is connected with the clock distribution module; the FPGA is respectively connected with a DSP (Digital Signal Processor), an SPI (Serial Peripheral Interface) and an RS232 (Recommend Standard 232) serial port; the DSP is connected with a 100M Ethernet and the RS232 serial port; an external memory interface is also connected between connecting points of the FPGA and the DSP and is connected with a NORFlash, a synchronous dynamic random access memory or the NANDFlash. The high-performance and intermediate-frequency digitizer disclosed by the invention has the advantages that the ADC data acquisition module is arranged for sampling data, and the data are transmitted to the FPGA to be further recognized and sorted, then are transmitted to the SPI and the DSP for being subjected to narrowband concurrent task processing and wideband concurrent task processing, and are compressed by the DSP, so that the storage depth of data is improved; the data are replayed by utilizing powerful data processing capability of the DSP, and simultaneously interact with the Ethernet to realize wideband task processing, so that the data loading time is reduced, the signal processing capability is improved and the convenient and fast effects are achieved.
Description
Technical field
The present invention relates to a kind of digitizer, be specifically related to the if digitization instrument that a kind of network and SPI mix.
Background technology
Digitizer is the device that the continuous analog amount of image and figure is converted to discrete digital quantity, is a kind of purposes graphic input device very widely in professional application field, is made up of electromagnetic induction plate, vernier and corresponding electronic circuit.When user on electromagnetic induction plate moving cursor to assigned address, and when the intersection point of spider is aimed to digitized, press button, digitizer is arranged in one group of orderly information by the position coordinate value of now corresponding order symbol and this point, is then sent to principal computer by interface (multiplex serial line interface).
Present digitizer can not be supported the concurrent task in hyperchannel broadband and arrowband, and the function that the firmware being used in conjunction with is realized is few, and signal handling capacity simulated performance is strong, data upload overlong time, can not be applied easily and fast.
Summary of the invention
For addressing the above problem, the invention provides a kind of high-performance intermediate frequency digitizer that can improve signal handling capacity raising simulated performance.
Object of the present invention reaches by the following technical programs:
Comprise FPGA, described FPGA is connected with adc data acquisition module and clock distribution module, described adc data acquisition module is connected with clock distribution module, and FPGA is also connected with DSP, SPI mouth and RS232 serial ports, and described DSP is connected with 100M Ethernet and RS232 serial ports.Between FPGA and the tie point of DSP, be also connected with external memory interface.Described external memory interface and NOR Flash or synchronous DRAM or NAND Flash are connected.
Described adc data acquisition module is connected with controllable amplifier.
Described adc data acquisition module is 2, and adc data acquisition module is 2ch 14bit, being connected of each adc data acquisition module and 2 controllable amplifiers.Adc data acquisition module is binary channels, 14bit, the high performance chips of 80Msa.
DSP is also connected with audio interface.
Described adc data acquisition module is connected with controllable amplifier, and adc data acquisition module is connected with 2 controllable amplifiers.
DSP is TMS320C6713.FPGA is EP3C80 or EP3C120.
The present invention compared with prior art, there is following advantage and beneficial effect:
The present invention arranges adc data acquisition module data is sampled, be sent to again FPGA and realize further identification and the sorting to data, be transferred to the concurrent task processing that SPI interface and DSP place carry out arrowband and broadband, by DSP, data are compressed, improve the storage depth of data, and utilize the powerful deal with data ability of DSP to carry out playback to data, while and Ethernet are mutual, realize the task processing in broadband, reduced the data upload time, improved signal handling capacity, convenient and swift.
Brief description of the drawings
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment 1
As shown in Figure 1, comprise FPGA, described FPGA is connected with adc data acquisition module and clock distribution module, and described adc data acquisition module is connected with clock distribution module, FPGA is also connected with DSP, SPI mouth and RS232 serial ports, and described DSP is connected with 100M Ethernet and RS232 serial ports.Adc data acquisition module is sampled to data, be sent to again FPGA and realize further identification and the sorting to data, be transferred to the concurrent task processing that SPI interface and DSP place carry out arrowband and broadband, by DSP, data are compressed, improve the storage depth of data, and utilize the powerful deal with data ability of DSP to carry out playback to data, while and Ethernet are mutual, realize the task processing in broadband, reduced the data upload time, improved signal handling capacity, convenient and swift.In the present embodiment, FPGA adopts ALTERA FPGA, EP3C80 or EP3C120.DSP adopts TIDSP, is TMS320C6713.
Between FPGA and the tie point of DSP, be also connected with external memory interface.Described external memory interface and NOR Flash and/or synchronous DRAM and/or NAND Flash are connected.External memory interface is that the function admirable of EMIF has very large convenience and dirigibility with outside synchronous DRAM (SDRAM), asynchronous device while connection, and according to the difference of DSP, EMIF bus is 32 or 16.
Described adc data acquisition module is connected with controllable amplifier.
Described adc data acquisition module is 2, and adc data acquisition module is 2ch 14bit, being connected of each adc data acquisition module and 2 controllable amplifiers.Adc data acquisition module is binary channels, 14bit, the high performance chips of 80Msa.
DSP is also connected with audio interface.Can connect audio frequency apparatus, output sound signal.
Described adc data acquisition module is connected with controllable amplifier, and adc data acquisition module is connected with 2 controllable amplifiers.The gain adjustment of controllable amplifier support+13dB～-18dB.
The present invention includes adc data acquisition module, digital signal processor and SPI, 100M network interface, realize if signal sampling and processing, further, can need to match firmware with objects such as realization detect, catches according to application.
Claims (8)
1. high-performance intermediate frequency digitizer, it is characterized in that: comprise FPGA, described FPGA is connected with adc data acquisition module and clock distribution module, described adc data acquisition module is connected with clock distribution module, FPGA is also connected with DSP, SPI mouth and RS232 serial ports, and described DSP is connected with 100M Ethernet and RS232 serial ports.
2. high-performance intermediate frequency digitizer according to claim 1, is characterized in that: between FPGA and the tie point of DSP, be also connected with external memory interface.
3. high-performance intermediate frequency digitizer according to claim 3, is characterized in that: described external memory interface and NOR Flash or synchronous DRAM or NAND Flash are connected.
4. high-performance intermediate frequency digitizer according to claim 1, is characterized in that: adc data acquisition module is connected with controllable amplifier.
5. high-performance intermediate frequency digitizer according to claim 1, is characterized in that: described adc data acquisition module is 2, and adc data acquisition module is 2ch 14bit.
6. high-performance intermediate frequency digitizer according to claim 1, is characterized in that: clock distribution module is also connected with outside main system clock input.
7. according to the high-performance intermediate frequency digitizer described in claim 1-6 any one, it is characterized in that: DSP is also connected with audio interface.
8. according to the high-performance intermediate frequency digitizer described in claim 1-6 any one, it is characterized in that: described adc data acquisition module is connected with controllable amplifier, adc data acquisition module is connected with 2 controllable amplifiers.
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| CN201310691838.5A CN103870426A (en) | 2013-12-17 | 2013-12-17 | High-performance and intermediate-frequency digitizer |
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| CN201310691838.5A CN103870426A (en) | 2013-12-17 | 2013-12-17 | High-performance and intermediate-frequency digitizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110109853A (en) * | 2019-04-04 | 2019-08-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing (DAP) device and method |
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| CN101110154A (en) * | 2007-08-10 | 2008-01-23 | 北京理工大学 | Dual-channel DSPEED-ADC_D2G high-speed data acquisition board |
| CN101150316A (en) * | 2007-09-14 | 2008-03-26 | 电子科技大学 | A multi-channel clock synchronization method and system |
| CN201247466Y (en) * | 2008-08-26 | 2009-05-27 | 天津理工大学 | High speed real-time data collection system |
| CN202396015U (en) * | 2011-12-12 | 2012-08-22 | 江苏新恒基重工有限公司 | Pipeline local heating device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6938177B1 (en) * | 2001-12-19 | 2005-08-30 | Sentient Sensors Llc | Multi-chip module smart controller |
| CN101110154A (en) * | 2007-08-10 | 2008-01-23 | 北京理工大学 | Dual-channel DSPEED-ADC_D2G high-speed data acquisition board |
| CN101150316A (en) * | 2007-09-14 | 2008-03-26 | 电子科技大学 | A multi-channel clock synchronization method and system |
| CN201247466Y (en) * | 2008-08-26 | 2009-05-27 | 天津理工大学 | High speed real-time data collection system |
| CN202396015U (en) * | 2011-12-12 | 2012-08-22 | 江苏新恒基重工有限公司 | Pipeline local heating device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110109853A (en) * | 2019-04-04 | 2019-08-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing (DAP) device and method |
| CN110109853B (en) * | 2019-04-04 | 2021-04-16 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing device and method |
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