CN103858170A - Contact structure and method for variable impedance memory element - Google Patents
Contact structure and method for variable impedance memory element Download PDFInfo
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- CN103858170A CN103858170A CN201280023443.1A CN201280023443A CN103858170A CN 103858170 A CN103858170 A CN 103858170A CN 201280023443 A CN201280023443 A CN 201280023443A CN 103858170 A CN103858170 A CN 103858170A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Abstract
A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.
Description
Technical field
Present disclosure relates generally to the equipment of the memory element with variableimpedance, relates more specifically to the contact structures for such memory element.
Background
Element (being sometimes referred to as programmable metallization unit (PMC)) and other resistor-types RAM(RRAM of traditional conductive bridge random access memory (CBRAM) type) memory element of type can comprise the accumulation layer that can programme between two or more resistance states.The memory element of this routine can comprise " effectively " electrode being formed by metal (such as silver), and this metal can be oxidized and carry out ionic conduction by solid electrolyte.
The blanket coating of such metal (as silver) is because meeting produces defect, and is difficult to process (, carrying out patterning with lithography step).It is especially difficult when such processing procedure is carried out during backend process (BEOL) part of manufacturing process.The BEOL part of technique is carried out after can forming in substrate at active parts and then being covered by one or more interlayer dielectric layers.
In addition, traditionally, may suffer thermal instability and/or facilitate the variation in the performance between memory component in the large interface region between active electrode and solid electrolyte.
Brief Description Of Drawings
Fig. 1 is according to the sectional view of the memory element with etching stopping layer of embodiment.
Fig. 2 is according to the sectional view of the memory element with hard etching mask of embodiment.
Fig. 3 is according to the sectional view of the memory element with etching stopping layer of another embodiment.
Fig. 4 is according to the sectional view of the memory element with hard etching mask of another embodiment.
Fig. 5 A to Fig. 5 E makes a series of views of the method for memory element as shown in Figure 1 according to the demonstration of embodiment.
Fig. 6 A to Fig. 6 H makes a series of sectional views of the method for memory element as shown in Figure 2 according to the demonstration of embodiment.
Fig. 7 A to Fig. 7 D-1 makes a series of views of the method for memory element as shown in Figure 3 according to the demonstration of embodiment.
Fig. 8 A to Fig. 8 F makes a series of sectional views of the method for memory element as shown in Figure 4 according to the demonstration of an embodiment.
Describe in detail
Embodiment disclosed herein has shown a kind of method and corresponding structure of memory element of the contact area that can reduce accumulation layer and electrode.Such memory element can provide so little region contact and need to not cover patterning and the etching step on the electrode layer of deposition at blanket, thereby prevents the defect occurring in traditional method.And compared with classic method, such area that reduces contacts the memory element response that can provide more consistent.
With reference to Fig. 1,, and represent by general reference numeral 100 with shown in sectional view according to the memory element of an embodiment.Memory element 100 can comprise the first electrode part 102, be formed on the second electrode part 116, accumulation layer 120 and top electrodes 122 on etching stopping layer (ESL) 106.The first and second electrode parts (102 and 116) can form bottom electrode, and this bottom electrode and accumulation layer 120 have little contact area.
The first electrode part 102 can be formed on lower insulator 104.Etching stopping layer (ESL) 106 can be formed in lower isolator 104.Shown in specific embodiment in, the first electrode part 102 can be extended by the opening in ESL106.But in another embodiment, ESL can be formed in the part of top surface of the first electrode part, and has opening, this opening exposes the top surface of the first electrode part.
The second electrode part 116 can be formed in the opening 110 of upper portion insulating body 108, and contacts with the top surface of the first electrode part 102 and ESL106.Upper portion insulating body 108 can be formed on the top of lower isolator 104 and the first electrode part 102.Upper portion insulating body 104 can comprise an insulation course or form multiple insulation courses of dielectric stack.In very specific embodiment, upper portion insulating body 108 can be formed by silicon nitride and/or silicon oxynitride.
ESL106 can be any material that the etch process that forms opening on upper portion insulating body 108 is stopped of being applicable to.,, for the upper portion insulating body 108 above ESL106, the etch process that forms opening 108 is high selectivity.
The second electrode part 116 can comprise one or more conducting films, and these conducting films can provide the conductive material of required resistance to form by any suitable element size for given.In certain embodiments, the second electrode part 116 wherein forms anode all or part of of CBRAM type element, and the second electrode part 116 can comprise one or more elements, and these one or more elements are oxidable and at the interior ionic conduction of accumulation layer 120.In very specific embodiment, the second electrode lay 116 can comprise any in silver or copper.
It should be noted that ESL106 can assist in ensuring that opening 110 keeps desirable low flat shape characteristic.If there is no such layer, the bottom of opening 110 can extend to lower isolator 104 and/or the first electrode part 102, thereby in bottom surface, produces undesirable step.If there is no ESL106, the conforma layer of the second electrode part 116 may have discontinuous due to the undesirable shape characteristic in opening 110.
The second electrode part 116 therein forms in other all or part of embodiment of cathode electrode of CBRAM, the second electrode part 116 can be by the conductive material of one or more 'inertia's (for example, with respect to accumulation layer 120, substantially do not there is the material of electrochemical activity) form.In very specific embodiment, conductive contact layer 112 can comprise any in tantalum or tantalum nitride.
Still with reference to Fig. 1, insulating regions 118 can be formed in opening 110, between the second electrode part 116 forming on opening 110 sides.Insulating regions 118 can comprise any suitable insulant (comprising space).In specific embodiment, insulating regions 118 can comprise any in silicon nitride or monox, comprises by tetraethyl orthosilicate (TEOS) and decomposes the monox generating.
In very specific embodiment, accumulation layer 120 can comprise ion conductor, for example solid electrolyte.Conductive filament can form in accumulation layer 120, and can be eliminated by applying electric field.In very specific embodiment, accumulation layer 120 can comprise any in chalcogenide or solid electrolyte.
Fig. 2 has shown the memory element 200 according to another embodiment.Memory element 200 can comprise the part-structure as Fig. 1.Similar item refers to by identical Reference numeral, but the first digit of Reference numeral is " 2 ", rather than " 1 ".
Fig. 2 can be different from Fig. 1, and difference is, the first electrode part 202 can comprise the first component 202-0 and the second component 202-1 that are formed in lower isolator 204.In certain embodiments, first component 202-0 can be by the part of the first interconnection layer of the one or more conductive layers formation of patterning.Similarly, second component 202-1 can be a part that is formed on the second interconnection layer on described the first interconnection layer by the one or more conductive layers of patterning.Although the first and second parts (202-0 and 202-1) can be formed by any suitable (one or more) conductive material, in a specific embodiment, first component 202-0 and/or Part II 202-1 can comprise copper.
In other embodiments, the first electrode part 202 can be formed by the process of similar " dual damascene ".Such process can form the opening corresponding with first component 202-0 on lower insulator, and then forms the opening corresponding with second component 202-1 on lower insulator.Then, one or more conductive materials can be filled two openings.In this case, the first and second parts (202-0/1) can be the integration sections of identical electrode structure.
Fig. 2 can also be different from Fig. 1, that is, upper portion insulating body 208 can comprise bottom layer 208-0, interlayer insulating film 208-1 and top layer 208-2.In one embodiment, bottom layer 208-0 can be the ESL for etching step.In a particular embodiment, in the time that opening 210 has formed, bottom layer 208-0 can play in etching the effect of etch stop by interlayer insulating film 208-1.That is to say, initial etching operation can etching pass through interlayer insulating film 208-1 also till bottom layer 208-0.The part of the bottom 208-0 that expose at the bottom place of etching openings can be removed with exposed bottom contact 202 and complete opening 210.
In one embodiment, layer 208-2 in top can be the etching mask of " firmly ".That is to say, top layer 208-2 can be formed with opening and use as etching mask, replaces the mask based on resist, or analog.Compare hard etching mask 208-2, for interlayer insulating film 208-1, form opening 210(and wherein comprise electrode part 216) etching step be high selectivity.
Fig. 2 is be different from Fig. 1 further: top electrodes 222 can comprise the first conductive layer 222-0 and the second conductive layer 222-1.
Although it should be noted that the embodiment that Fig. 2 shows has comprised ESL and hard etching mask, may only include hard etching mask in alternate embodiment and does not comprise ESL simultaneously.
Fig. 3 illustrates the memory element 300 according to another embodiment.Memory element 300 can comprise the part-structure as Fig. 1.Similar item refers to by identical Reference numeral, but the first digit of Reference numeral is " 3 ", rather than " 1 ".
Fig. 3 is different from Fig. 1 to be: the second electrode part 316 can comprise oxide layer 324.Oxide layer 324 can increase the resistance of the second electrode part 316.In addition, in certain embodiments, the second electrode part 316 is anodes, and formation oxide layer 324 can further reduce the area of the contact interface (being solid electrolyte) between anode and accumulation layer.
Fig. 4 has shown the memory element 400 according to another embodiment.Memory cell 400 can comprise the part-structure as Fig. 2.Similar item refers to by identical Reference numeral, but the first digit of Reference numeral is " 4 ", rather than " 2 ".
Fig. 4 is different from Fig. 2 to be: the second electrode part 416 not exclusively covers the bottom of opening 410.In addition, in an illustrated embodiment, the second electrode part 416 can have " sidewall " shape, little at the thickness of Thickness Ratio opening 410 bottoms at opening 410 tops.
Describing according to after the structure of the various memory elements of embodiment, will the method that form such structure be described.
Fig. 5 A to Fig. 5 E illustrates the method for the memory element 100 shown in Fig. 1 according to the formation of specific embodiment.
Fig. 5 A has shown the memory element 100 forming in upper portion insulating body 108 after opening 110, and this memory element 100 has the first electrode part 102 having exposed.In one embodiment, etching mask (not shown) can be formed on having on the top surface corresponding to the opening of opening 110 of upper insulator 108.Then can carry out etching step, this etching step uses ESL106.ESL106 can protect lower isolator 104 to exempt from etching.What in such embodiments, ESL106 and the first electrode part 102 can be from the basal surfaces of opening 110 is all or part of.
Fig. 5 B has shown above the top surface of top insulator 104 and at the interior formation conductive contact layer 112 of opening 110.As shown in the figure, conductive contact layer 112 does not fill up opening 110, and therefore, space 113 can be present between the part of contact layer 112 of the relative both sides of opening 110.Conductive contact layer 112 can have width (being shown as W).
As described above and in conjunction with Fig. 1, in certain embodiments, conductive contact layer 112 can form active electrode, comprises the oxidable elements in one or more accumulation layers forming subsequently.
Fig. 5 C has shown the formation of packed layer 114.Packed layer 114 can be formed at space 113 with interior and conductive contact layer 112 tops.Packed layer 114 can comprise one or more insulation courses.As described above, in certain embodiments, only filling opening 113 leave space partly of packed layer 114.Or, can not adopt packed layer 114 and leave space (, space 113).
Fig. 5 D-0 has shown the top surface removal conductive contact layer 112 from upper portion insulating body 108.Consequently, can form the region contact structures 116 of reduction.In such contact structures 116, the top surface of conductive contact layer 112 is exposed.Such top surface part can represent the proportional surface area of width (being designated as A) to conductive contact layer 112.In the embodiment shown, the process operation of Fig. 5 D-0 can be at the interior formation insulating regions 118 of opening 110.
In certain embodiments, removing conductive contact layer 112 can comprise the planarisation step of the top surface planarization of upper portion insulating body 108.Planarisation step can comprise chemically mechanical polishing (CMP), etching or their combination.
Fig. 5 D-1 has shown the vertical view of Fig. 5 D-0 structure.The area of the contact structures 116 that as shown in the figure, area reduces can significantly be less than the area of opening 110.Although the contact structures 116 that the area that Fig. 5 D-1 shows reduces have loop configuration and have solid bottom, also can comprise different shapes according to the shape of opening 110 in alternate embodiment.
Fig. 5 E has shown the formation of accumulation layer 120 and top electrodes 122.As described above, in a particular embodiment, accumulation layer 120 can comprise ion conductor 120, comes in responsive materials or by the ionic conduction of material by response electric field change, ion conductor 120 can be realized the static of electrical specification (for example, resistance and/or electric capacity) and/or change dynamically.Accumulation layer 120 can comprise one or more layers, and can comprise in certain embodiments solid electrolyte.In very specific embodiment, accumulation layer 120 can comprise chalcogenide and/or metal oxide, and conductive part wherein can form by electrochemical reaction.
In one embodiment, accumulation layer 120 and top electrodes 122 can form by depositing one or more layers.Then, patternable ion stores and (one or more) top electrode layer.In alternate embodiment, accumulation layer 120 can separately be carried out patterning by top electrodes 122.
Fig. 6 A to Fig. 6 H illustrates the method for the memory element 200 shown in Fig. 2 according to the formation of a specific embodiment.
Fig. 6 A has shown above the second electrod assembly 202-1 and has formed upper portion insulating body 208.Upper portion insulating body 208 can comprise ESL208-0, interlayer insulating film 208-1 and hard etching mask layer 208-2.As mentioned above, the material of layer 208-0/1/2 can be selected according to the etching step that generates opening in interlayer insulating film 208-1.
Fig. 6 B has shown in order to create hard etch mask 208-2 and in hard etching mask layer, has formed mask open 210'.In illustrated embodiment, can be by form etching mask 211 on the top surface of etching stopping layer, then etching openings 210', forms mask open 210'.Should be understood that and then can remove etching mask 211.
Fig. 6 C shown carry out etching openings 210 through interlayer insulating film 208-1 hard etch mask 208-2 ".ESL208-0 can be used as the end points of such etching step.That is, compare ESL208-0, for middle layer 208-1, the etching that creates opening 210 through interlayer insulating film 208-1 is high selectivity.
Fig. 6 D has shown by ESL208-0 and has formed an opening, thereby formed the opening 210 that electrod assembly 202-1 is exposed.
Fig. 6 E has shown the formation of the conductive contact layer 212 as described in Fig. 5 B.Conductive contact layer 212 can be formed on the top surface of hard etching mask 208-2 and on the side of opening 210, contacts with the second electrod assembly 202-1 with interlayer insulating film 208-1, ESL208-0.
Fig. 6 F has shown the formation of packed layer 214.Packed layer 214 can be formed in space 213 and conductive contact layer 212 tops.Packed layer 214 can comprise one or more insulation courses.In the situation of Fig. 5 C, in alternate embodiment, form packed layer 214 and can set up space, or may not use packed layer 214.
Fig. 6 G has shown from the top surface of upper portion insulating body 208 (, the top surface 208-2 of hard etch mask) and has removed conductive contact layer 212.Consequently, can form and reduce area contact structures 216.As at Fig. 5 A in the embodiment of 5E, surface area (being shown A) can be relevant to the width of conductive contact layer 213, and be less than the represented area of opening 210.
In certain embodiments, remove conductive contact layer 212 and can comprise planarisation step, like above-mentioned Fig. 5 A is to step or the equivalent steps described in 5E, and can form insulating regions 218.
Fig. 6 H has shown the formation of ion conductor 220 and top electrodes 222.Form or equivalent form that ion conductor 220 can take above-mentioned Fig. 1 to describe.
Fig. 7 A to Fig. 7 D-1 illustrates the method for the memory element 300 shown in Fig. 3 according to the formation of a specific embodiment.Suppose to carry out the processing as shown in Fig. 5 A or equivalent, to produce opening 310 on upper portion insulating body 308.
Fig. 7 A has shown above top insulator 304 top surfaces and the interior formation conductive contact layer 312 of opening 310.Such action comprises as shown at Fig. 5 B or the processing of equivalence.But, different from Fig. 5 B, suppose that conductive contact layer 312 is formed by oxidable material.
Fig. 7 B has shown the part of conductive contact layer 312 has been oxidized to form oxidized portion 324.This oxidation step can further reduce the width (W) of conductive contact layer 312.
Fig. 7 C has shown the formation of packed layer 314.Such action can comprise as Fig. 5 C describe or equivalence processing.
Fig. 7 D-0 and 7D-1 can comprise the action of mentioning as in Fig. 5 D-0 and 5D-1.But as shown in Fig. 7 D-1, contact area " A " can be proportional with the width of layer " W ", less than the thickness of oxidized portion.
Fig. 8 A to Fig. 8 F illustrates the method for the memory element 400 shown in Fig. 4 according to the formation of a specific embodiment.
With reference to Fig. 8 A, suppose through shown in Fig. 6 A to 6D or after the processing of equivalence, on upper portion insulating body 408, form opening 410.Upper portion insulating body 408 can comprise that bottom layer 408-0, top layer 408-2 or both have both at the same time, and 408-0 is as ESL for this bottom layer, and this top layer 408-2 is as hard etching mask 408-2.
Fig. 8 B has shown above the top surface of upper portion insulating body 408 and the interior formation conductive contact layer 412 of opening 410.Such action has comprised as shown at Fig. 5 B or the processing of equivalence.
Fig. 8 C has shown by anisotropic etching conductive contact layer to form the second electrode part 416 of " sidewall " type.
Fig. 8 D has shown the formation of packed layer 414.Packed layer 414 can be formed in space 413, and can comprise processing as described or equivalent in Fig. 5 C.
Fig. 8 E has shown planarisation step, this step can complanation to remove the part of upper portion insulating body 408 and to expose the top of the second electrode part 416.Such action can comprise as shown at Fig. 5 D-0 or the processing of equivalence.
Fig. 8 F has shown the formation of the accumulation layer 420 that contacts the second electrode part 416, and the formation of the top electrodes 422 of accumulation layer 420 tops.Such action can comprise as shown at Fig. 5 E or the processing of equivalence.
According to the memory construction described in embodiment with method may be included in or for the memory element (the memory storage of basis function storage is only provided) of an independent storage.In alternate embodiment, such memory device can be embedded in larger integrated circuit (IC)-components.In specific embodiment, can in " rear end " of manufacturing process, form such memory construction, for example, after forming in Semiconductor substrate or analog, active device (, transistor) forms again.
Can from above-described embodiment, understand, active electrode can be formed at accumulation layer with a little contact area, simultaneously without effectively sheltering and etching on material blanket coating.And contact area can for example, for example, be controlled according to thickness of electrode (, Fig. 5 D-0,6E, the W in 7C) rather than the patterning step (lithography step) of deposition.
But should be appreciated that in the above description of exemplary embodiment, various features are grouped together in single embodiment, figure or description sometimes, and object is to help to understand the one or more creationary aspect in various aspects of the present invention.But method of the present disclosure can not be interpreted as reflecting that invention required for protection need to be than the intention of the more feature of clearly recording in each claim.On the contrary, as the following claims reflect, creative aspect is the feature fewer than all features of arbitrary single above-mentioned disclosed embodiment.Therefore, appended claims is clearly incorporated in this detailed description at this, and wherein each claim oneself itself is as independent embodiment of the present invention.
Should also be understood that embodiments of the invention also can implement in the time lacking not concrete disclosed element and/or step., character of innovation of the present invention can be got rid of key element.
Claims (26)
1. a memory element, comprising:
Opening, it is formed at least one insulation course, and insulation course is formed on etching stopping layer, and described opening is at its bottom-exposed the first electrode part and described etching stopping layer;
The second electrode part forms at least one side surface of described opening, and above the top surface of described at least one insulation course, does not form, and the second electrode part divides contact the first electrode part; And
At least one accumulation layer, is formed on the top surface of at least one insulation course and divides and contact with the second electrode part, and described at least one accumulation layer can be reversibly able to programme between at least two impedance states.
2. memory element according to claim 1, is characterized in that:
Described etching stopping layer is selected from following group: silicon nitride and silicon oxynitride; And
A described insulation course is to be formed by the material that is different from etching stopping layer.
3. memory element according to claim 1, is characterized in that:
The second electrode comprises annular section.
4. memory element according to claim 1, is characterized in that:
The second electrode part divides and comprises the conductive material that is selected from following group: tantalum, tantalum nitride.
5. memory element according to claim 1, is characterized in that:
The first electrode part divides and comprises copper.
6. memory element according to claim 1, is characterized in that:
Described at least one accumulation layer comprises solid electrolyte; And
The second electrode part divides and comprise at least one metal that can be oxidized in solid electrolyte.
7. memory element according to claim 1, is characterized in that:
Described at least one accumulation layer is selected from following group: chalcogenide and metal oxide.
8. according to the memory element of claim 1, it is characterized in that, further comprise:
Fill insulator, in opening, form, and between part on the relative both sides that are formed on described opening of the second electrode.
9. a memory element, comprising:
Opening, it forms within least one hard etching mask and at least one insulation course, and described opening is in its bottom-exposed the first electrode part;
The second electrode part forms at least one side surface of described opening, and above the top surface of described hard etching mask, does not form, and the second electrode part divides contact the first electrode part; And
At least one accumulation layer, is formed on the top surface of hard etching mask and divides and contact with the second electrode part, and described at least one accumulation layer can be reversibly able to programme between at least two impedance states.
10. memory element according to claim 9, is characterized in that:
The second electrode comprises annular section.
11. memory elements according to claim 9, is characterized in that:
Described at least one accumulation layer comprises solid electrolyte; And
The second electrode part divides and comprise at least one metal that can be oxidized in solid electrolyte.
12. memory elements according to claim 9, is characterized in that:
Described at least one accumulation layer is selected from following group: chalcogenide and metal oxide.
13. memory elements according to claim 9, is characterized in that, further comprise:
Fill insulator, in opening, form, and between part on the relative both sides that are formed on described opening of the second electrode.
14. memory elements according to claim 9, is characterized in that, further comprise:
Etching stopping layer, is formed at described at least one insulation course below, and divides and contact with the first electrode part.
15. 1 kinds of methods, comprising:
Etching arrives etching stopping layer through at least one insulation course, and to form the opening that exposes the first electrode part, than etching stopping layer, described etching step has high selectivity for described at least one insulation course;
Depositing conducting layer conformally at least side surface of opening keeps space simultaneously in opening;
Planarization is to remove the part of the conductive contact layer forming on the top surface of described at least one insulation course; And
In at least one accumulation layer contacting through the contact layer of formation above the contact layer of planarization and process planarization, described accumulation layer is reversibly able to programme between at least two impedance states.
16. according to the method for claim 15, it is characterized in that:
Etching comprises through the step of described at least one insulation course
On insulation course, form hard etching mask layer,
In described hard etching mask layer, form opening to produce hard etching mask, and
Use described hard etching mask to carry out etching through insulation course.
17. memory elements according to claim 15, is characterized in that:
Described at least one accumulation layer comprises solid electrolyte; And
The second electrode part divides and is included in oxidable at least one metal in solid electrolyte.
18. according to the method for claim 15, it is characterized in that:
Described planarisation step exposes the top section of conductive contact layer, presents the contact area directly related with the thickness of described contact layer.
19. according to the method for claim 15, it is characterized in that:
Described planarisation step comprises chemically mechanical polishing (CMP).
20. according to the method for claim 15, it is characterized in that, further comprises:
Conformally deposit described conductive contact layer in described opening after, in the space in described opening, deposit at least one insulation filling layer.
21. according to the method for claim 15, it is characterized in that, further comprises:
After conformally depositing described conductive contact layer, be oxidized at least a portion of described conductive contact layer.
22. 1 kinds of methods, comprising:
Use hard mask layers etching through at least one insulation course, to form the opening that the first electrode part is exposed;
Depositing conducting layer conformally at least side surface of opening, to form space in opening;
Planarization is to remove the part of the conductive contact layer forming on the top surface of described at least one insulation course; And
On the contact layer of described planarization, form at least one accumulation layer contacting with the contact layer of described planarization, described accumulation layer is reversibly able to programme between at least two impedance states.
23. according to the method for claim 22, it is characterized in that, further comprises:
Below described at least one insulation course, form etching stopping layer, wherein
Etching comprises through the step of described at least one insulation course: have the etching of high selectivity for described at least one insulation course than etching stopping layer.
24. memory elements according to claim 22, is characterized in that:
Described at least one accumulation layer comprises solid electrolyte; And
Described the second electrode part divides and is included in oxidable at least one metal in solid electrolyte.
25. according to the method for claim 24, it is characterized in that, further comprises:
Conformally deposit described conductive contact layer in opening after, in the space in opening, deposit at least one insulation filling layer.
26. according to the method for claim 24, it is characterized in that, further comprises:
After conformally depositing described conductive contact layer, be oxidized at least a portion of described conductive contact layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/470,286 | 2012-05-12 | ||
| US13/470,286 US8816314B2 (en) | 2011-05-13 | 2012-05-12 | Contact structure and method for variable impedance memory element |
| PCT/US2012/044050 WO2012167286A1 (en) | 2011-05-13 | 2012-06-25 | Contact structure and method for variable impedance memory element |
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| Publication Number | Publication Date |
|---|---|
| CN103858170A true CN103858170A (en) | 2014-06-11 |
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| CN201280023443.1A Pending CN103858170A (en) | 2012-05-12 | 2012-06-25 | Contact structure and method for variable impedance memory element |
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| KR (1) | KR20140145529A (en) |
| CN (1) | CN103858170A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1650419A (en) * | 2002-04-30 | 2005-08-03 | 独立行政法人科学技术振兴机构 | Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device |
| US20050243597A1 (en) * | 2004-04-29 | 2005-11-03 | Zettacore, Inc. | Systems, tools and methods for production of molecular memory |
| US20060211231A1 (en) * | 2005-03-15 | 2006-09-21 | Elpida Memory, Inc. | Memory device and manufacturing method thereof |
| CN101859871A (en) * | 2009-04-02 | 2010-10-13 | 索尼公司 | Memory element and manufacture method thereof and semiconductor storage |
-
2012
- 2012-06-25 CN CN201280023443.1A patent/CN103858170A/en active Pending
- 2012-06-25 KR KR1020137033102A patent/KR20140145529A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1650419A (en) * | 2002-04-30 | 2005-08-03 | 独立行政法人科学技术振兴机构 | Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device |
| US20050243597A1 (en) * | 2004-04-29 | 2005-11-03 | Zettacore, Inc. | Systems, tools and methods for production of molecular memory |
| US20060211231A1 (en) * | 2005-03-15 | 2006-09-21 | Elpida Memory, Inc. | Memory device and manufacturing method thereof |
| CN101859871A (en) * | 2009-04-02 | 2010-10-13 | 索尼公司 | Memory element and manufacture method thereof and semiconductor storage |
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| KR20140145529A (en) | 2014-12-23 |
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