CN103839878B - The forming method of semiconductor structure - Google Patents

The forming method of semiconductor structure Download PDF

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Publication number
CN103839878B
CN103839878B CN201210492711.6A CN201210492711A CN103839878B CN 103839878 B CN103839878 B CN 103839878B CN 201210492711 A CN201210492711 A CN 201210492711A CN 103839878 B CN103839878 B CN 103839878B
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layer
opening
surface
metal
medium
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CN201210492711.6A
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CN103839878A (en
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洪中山
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中芯国际集成电路制造(上海)有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors

Abstract

A kind of forming method of semiconductor structure, including:The Semiconductor substrate with the first conductive layer and the second conductive layer is provided, semiconductor substrate surface has first medium layer;There is the 3rd opening and the 4th opening in first medium layer surface formation mask layer, mask layer, the 3rd opening is corresponding with the position of the first conductive layer, and the 4th opening is corresponding with the position of the second conductive layer;Using mask layer as mask, etch first medium layer, the first opening for exposing the first conductive layer and the second opening for exposing the second conductive layer are formed, the second opening includes the first son opening being mutually communicated and the second son opening, and the opening size of the second son opening is more than the opening size of the first son opening;The first metal layer is formed in the first opening and the second opening;The first metal layer surface in the first opening forms second dielectric layer;Afterwards, the full second metal layer of filling in the first opening and the second opening.The forming method of the semiconductor structure is simple, and the semiconductor structure performance of formation is stable.

Description

The forming method of semiconductor structure

Technical field

The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor structure.

Background technology

In existing integrated circuit technology, damascene structure(Damascene)And metal-insulator-metal(MIM) The metal capacitor of structure is the common structure in current integrated circuit.

Wherein, because the metal capacitor of metal-insulator-metal structure has, resistance value is low, parasitic capacitance (Parasitic Capacitance)Small advantage, and there is no depletion layer induced voltage(Induced Voltage)Skew Problem, thus the metal-insulator-metal structure capacitor be able to analog circuit, radio circuit or mixed signal electricity It is widely used in road.

Fig. 1 is refer to, is the cross-section structure of the metal capacitor with metal-insulator-metal structure of prior art Schematic diagram, including:Conductive layer 101 in Semiconductor substrate 100;Positioned at the Semiconductor substrate 100 and the table of conductive layer 101 Have in the first medium layer 102 in face, first medium layer 102 and expose conductive layer 101 and part semiconductor substrate 100 Opening(It is not shown);Positioned at the side wall of the opening and the first metal layer 103 of lower surface and the table of the first metal layer 103 The second dielectric layer 104 in face;Positioned at the surface of second dielectric layer 104 and the second metal layer 105 of the full opening of filling.Its In, the material of the second metal layer 105 is copper, because copper has low-resistance characteristic, the metal capacitor is had more Good characteristic.

In addition, being improved constantly with the integrated level of integrated circuit, the characteristic size of semiconductor devices constantly reduces, and copper is with it Low-resistance characteristic becomes the mainstay material of metal interconnection structure;In order to overcome the problem of copper product is difficult to be etched, big horse Scholar's leather structure turns into the primary structure for making copper metal interconnection.

However, in existing integrated circuit fabrication process, formed the metal-insulator-metal structure capacitance and The process integration of damascene structure is relatively low, and technological process is excessively complicated.

The related data in more Damascus and metal-insulator-metal structure capacitance and forming method thereof refer to Publication No. US2007/0057305 U.S. patent documents.

The content of the invention

The problem of present invention is solved is to provide a kind of forming method of semiconductor structure, and simplification forms metal-insulator-gold The technique for belonging to structure capacitance and damascene structure.

To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including:Semiconductor lining is provided There is the first conductive layer and the second conductive layer, the table of first conductive layer and the second conductive layer in bottom, the Semiconductor substrate Face and the surface of Semiconductor substrate are flushed, and the surface of the Semiconductor substrate, the first conductive layer and the second conductive layer has first Dielectric layer;There is the 3rd opening and the 4th opening in first medium layer surface formation mask layer, the mask layer, it is described 3rd opening exposes first medium layer surface corresponding with the position of the first conductive layer, and the 4th opening exposes and second The corresponding conductive layer of first medium layer surface second in position of conductive layer;Using the mask layer as mask, etch described first and be situated between Matter layer, forms the first opening for exposing the first conductive layer and the second opening for exposing the second conductive layer, second opening It is open including exposing the first son opening of the second conductive layer and the second son of bottom and the described first son opening insertion, institute The opening size for stating the second son opening is more than the opening size of the described first son opening;It is open in the described first opening and second Side wall and lower surface and first medium layer surface formation the first metal layer;Side wall and bottom in the described first opening The first metal layer surface forms second dielectric layer;After the second dielectric layer is formed, in the described first opening and the second opening The interior second metal layer for forming filling full first opening and the second opening;Remove the second gold medal higher than first medium layer surface Belong to layer, second dielectric layer, the first metal layer and mask layer.

Optionally, the formation process of first opening and the second opening is:Opened in the mask layer surface and the 4th The side wall of mouth and section bottom surface form photoresist layer, and the photoresist layer exposes the correspondence position of the second conductive layer;With The photoresist layer is mask, and the 3rd opening and the 4th open bottom are etched using anisotropic dry etch process First medium layer, formed it is corresponding with the first conductive layer position the 5th be open, and with the second conductive layer position the corresponding 6th Opening;The photoresist layer is removed, and using the mask layer as mask, is etched using anisotropic dry etch process described The bottom of 4th opening, the 5th opening and the 6th opening is untill Semiconductor substrate is exposed, and it is conductive that formation exposes first First opening of layer, and expose the second opening of the second conductive layer.

Optionally, the photoresist layer also covers the side wall of the 3rd opening and the first medium layer surface of section bottom.

Optionally, the mask layer includes the first sub- mask layer, the material of the first sub- mask layer is titanium nitride, titanium, One or more combinations in tantalum nitride and tantalum.

Optionally, the mask layer also includes the second sub- mask layer, and the second sub- mask layer is covered positioned at first son Between film layer and first medium layer, or positioned at the described first sub- mask layer surface, the material of the second sub- mask layer is oxidation One or more combinations in silicon, fire sand and silicon nitride.

Optionally, also include:The second medium layer surface has the 3rd metal level, and the material of the 3rd metal level is Ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese.

Optionally, the second dielectric layer and the formation process of the 3rd metal level are:Covered on the first metal layer surface Lid second medium film;In the second medium film surface the 3rd metallic film of formation;The first son for removing the second opening is opened The 3rd metallic film and second medium film of the side wall and lower surface of mouth and the second son opening.

Optionally, the 3rd metal level also covers the first metal layer surface of first medium layer surface, and second opens Intraoral the first metal layer surface.

Optionally, the second dielectric layer and the formation process of the 3rd metal level are:Covered on the first metal layer surface Lid second medium film;Remove the first son opening of the second opening and the side wall of the second son opening and the second medium of lower surface Film, forms second dielectric layer;The 3rd metal level is covered in the second dielectric layer and the first metal layer surface.

Optionally, the material of the second metal layer is copper.

Optionally, the formation process of the second metal layer is chemical vapor deposition method, physical gas-phase deposition, electricity Depositing process or physical gas-phase deposition and electroplating technology are combined.

Optionally, the material of the first metal layer is ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese.

Optionally, the material of the second dielectric layer is high K dielectric material.

Optionally, the high K dielectric material includes:HfO2、ZrO2、HfSiNO、Al2O3Or SbO.

Optionally, the material of the first medium layer is silica, silicon nitride or low-K dielectric material.

Optionally, there is etching barrier layer between the Semiconductor substrate and first medium layer, the etching barrier layer Material is silica, silicon nitride or low-K dielectric material, and the etching barrier layer is different from the material of first medium layer.

Optionally, the material of first conductive layer and the second conductive layer is copper, tungsten or aluminium.

Compared with prior art, technical scheme has advantages below:

In first medium layer surface formation mask layer, the mask layer define it is follow-up needed for the first opening for being formed and the The position of two openings and opening shape;Using the mask layer, the first medium layer described in mask etching is conductive up to exposing first Untill layer and the second conductive layer, it is open in the first conductive layer surface formation first, for forming capacitance structure, in the second conductive layer Surface forms second and is open, for forming damascene structure;Wherein, second opening includes exposing the second conductive layer First son opening and bottom and the second son of the described first son opening insertion are open, the opening size of the second son opening More than the opening size of the described first son opening;First opening and the second opening use same mask layer, in same etching Formed in technique, processing step and process time can be saved, and it is cost-effective.

In addition, after the first opening and the second opening is formed, the side wall and lower surface of the first opening and the second opening The first metal layer is formed simultaneously;And formed on the first metal layer surface of the first opening after second dielectric layer, while described Form the full second metal layer of filling in first opening and the second opening, and remove second metal layer higher than first medium layer, the Second medium layer, the first metal layer and mask layer;Due to the first metal layer and the second gold medal in the described first opening and the second opening Category layer is formed simultaneously, can further simplify technique;Moreover, second metal layer, second medium higher than first medium layer surface Layer, the first metal layer and mask layer are removed simultaneously, are reduced the number of times of the removal technique, can be avoided because repeatedly removing work Skill and cause the damage to first medium layer surface and other device surfaces for being formed at semiconductor substrate surface, make what is formed The pattern of semiconductor devices is good, and performance is stable.

Brief description of the drawings

Fig. 1 is the cross-sectional view of the metal capacitor with metal-insulator-metal structure of prior art;

Fig. 2 to Fig. 5 is cuing open for the process of existing formation metal-insulator-metal structure capacitance and damascene structure Face structural representation;

Fig. 6 to Figure 13 is the cross-sectional view of the forming method of the semiconductor structure described in embodiments of the invention.

Embodiment

The technological process for making the metal-insulator-metal structure capacitance and damascene structure is not easy of integration, makes The manufacturing process of integrated circuit is excessively complicated.

The present inventor has found by research, due to for forming the metal-insulator-metal structure capacitance It is different with the opening shape of damascene structure, therefore its formation process is also different;Moreover, as shown in figure 1, the metal-absolutely Edge layer-metal structure capacitor is made up of the first metal layer 103, second dielectric layer 104 and second metal layer 105.And existing skill The damascene structure of art is only made up of metal;Due to the structure and damascene of the metal-insulator-metal structure capacitance Remove from office structure different, therefore, in existing integrated circuit technology, the metal-insulator-metal structure capacitance and damascene Leather structure is formed respectively using respective technological process, makes the manufacturing process of integrated circuit complicated;Specifically, Fig. 2 to Fig. 5 is existing There is the cross-sectional view for the process to form metal-insulator-metal structure capacitance and damascene structure, including:

Refer to Fig. 2, there is provided the Semiconductor substrate 200 with the first conductive layer 201 and the second conductive layer 202, described The surface of one conductive layer 201 and the second conductive layer 202 is flushed with the surface of Semiconductor substrate 200, first conductive layer 201, Two conductive layers 202 and the surface of Semiconductor substrate 200 have first medium layer 203, and the dielectric layer 203, which has, to be exposed first and lead First opening 204 of electric layer 201 and part semiconductor substrate 200.

Fig. 3 is refer to, on the first medium 203 surface of layer and the first opening 204(As shown in Figure 2)Side wall and bottom Portion surface forms the first metal layer 205, the second dielectric layer 206 on the surface of the first metal layer 205 and the table of second dielectric layer 206 The second metal layer 207 in face, and full first opening 204 of the filling of the second metal layer 207;Using first time chemical machinery Glossing removes the first metal layer 205, second dielectric layer 206 and the second metal layer higher than 203 surface of first medium layer 207, form capacitance structure.

Fig. 4 is refer to, after first time CMP process, exposure is formed in first medium layer 203 Go out the second opening 208 of the second conductive layer 202, second opening 208 includes the first son opening for exposing the second conductive layer (It is not shown), and bottom and the second son opening of the first son opening insertion(It is not shown), it is described second son opening size it is big In the size of the described first son opening.

Fig. 5 is refer to, the full metal material of filling in the described second opening 208, and chemically-mechanicapolish polished using second Technique removes the metal material higher than 203 surface of first medium layer, forms damascene structure 209.

During above-mentioned formation metal-insulator-metal structure capacitance and damascene structure 209, formed After complete capacitance structure, damascene structure is re-formed, its complex technical process;Moreover, in the first opening 204(Such as Fig. 2 institutes Show), it is necessary to carry out chemical machine for the first time after interior formation the first metal layer 205, second dielectric layer 206 and second metal layer 207 Tool glossing, and, it is necessary to carry out second of CMP process after filling metal materials in the second opening 208, And CMP process easily causes the depression of first medium layer 203 twice, or in second of CMP process In, damage is caused to established capacitance structure surface;Make formed device topography and performance bad.

Further studied by the present inventor, in first medium layer surface formation mask layer, the mask layer is sudden and violent Expose the first medium layer surface of the first conductive layer and the second conductive layer correspondence position;Using the mask layer described in mask etching First medium layer is open untill the first conductive layer and the second conductive layer is exposed in the first conductive layer surface formation first, It is open in the second conductive layer surface formation second;It is described second opening include expose the second conductive layer first son opening, with And bottom and the second son of the described first son opening insertion are open, the opening size of the second son opening is more than the described first son The opening size of opening, can be used in forming damascene structure, and first opening can be used in forming capacitance structure;Institute State the first opening and the second opening uses same mask layer, formed in same etching technics, processing step and work can be saved The skill time, and it is cost-effective.

In addition, after the first opening and the second opening is formed, the side wall and lower surface of the first opening and the second opening, And first medium layer surface covering the first metal layer;And first opening the first metal layer surface formed second dielectric layer it Afterwards, while forming the full second metal layer of filling in the described first opening and the second opening, and remove higher than first medium layer Second metal layer;, can because the first metal layer and second metal layer in the described first opening and the second opening are formed simultaneously Further simplify technique;Moreover, higher than the second metal layer of first medium layer surface, second dielectric layer, the first metal layer and covering Film layer can be removed simultaneously, so as to reduce the number of times of chemically mechanical polishing;And then, technique is reduced to first medium layer table Face and the damage for other devices for being formed at semiconductor substrate surface, make the pattern of formed semiconductor devices good, and property Can be stable.

To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.

Fig. 6 to Figure 13 is the cross-sectional view of the forming method of the semiconductor structure described in embodiments of the invention.

Fig. 6 be refer to there is provided Semiconductor substrate 300, there is the first conductive layer 301 and the in the Semiconductor substrate 300 Two conductive layers 302, the surface of the conductive layer 302 of the first conductive layer 301 and second and the surface of Semiconductor substrate 300 are flushed, The surface of the Semiconductor substrate 300, the first conductive layer 301 and the second conductive layer 302 has first medium layer 303.

The Semiconductor substrate 300 is used to provide workbench for subsequent technique;The Semiconductor substrate 300 serves as a contrast for silicon Bottom, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator(SOI)Substrate, germanium on insulator(GOI)Substrate, glass substrate or III- V compounds of group substrates(Such as silicon nitride or GaAs).Or, the Semiconductor substrate 300 includes:Substrate, and formed If having the device layer or dielectric layer that dried layer is overlapped in the substrate surface, the substrate includes above-mentioned various types of substrates, and The device layer or dielectric layer are formed by preamble technique, and the conductive layer 302 of the first conductive layer 301 and second is located at the device of top layer In part layer or dielectric layer, and surface and the device layer or dielectric layer of the conductive layer 302 of first conductive layer 301 and second Surface is flushed.

The material of the conductive layer 302 of first conductive layer 301 and second is copper, tungsten or aluminium;First conductive layer 301 is used The electrode of the capacitance structure subsequently formed in electrical connection, second conductive layer 302 is used for Damascus with being subsequently formed Structure is electrically connected;The formation process of the conductive layer 302 of first conductive layer 301 and second is:The shape in the Semiconductor substrate Into two openings;In side wall and lower surface the formation stop-layer of described two openings, the material of the stop-layer is titanium, tantalum, One or more combinations in titanium nitride and tantalum nitride;In the metal of the full described two openings of the stopping layer surface formation filling Material;Metal material and stop-layer higher than the surface of Semiconductor substrate 300 is removed using CMP process, in institute State in two openings and form the first conductive layer 301 and the second conductive layer 302.Wherein, by the metal material filled with it is described The material of stop-layer is different, therefore stop position of the stop-layer for defining CMP process, and by certain The polishing of crossing of degree exposes the surface of Semiconductor substrate 300.

The material of the first medium layer 303 is silica, silicon nitride, low-K dielectric material or ultralow K(Ultra Low- k)Capacitance structure and damascene structure are formed in subsequent technique in material, the first medium layer 303;In the present embodiment In, have between the Semiconductor substrate 300, the first conductive layer 301 and the second conductive layer 302 and first medium layer 304 Etching barrier layer 320, the material of the etching barrier layer 320 is silica, silicon nitride or low-K dielectric material, and the etching Barrier layer 320 is different from the material of first medium layer 303;The etching barrier layer 320 is used for follow-up using etching work When skill forms the opening for forming capacitance structure and damascene structure, the stop position of etching technics is defined, and in etching After stopping, by certain over etching technique to expose the first conductive layer 301 or the second conductive layer 302, so that described carve Etching technique is easier control.

Fig. 7 is refer to, mask layer 304 is formed on 303 surface of first medium layer, has the in the mask layer 304 Three openings 305 and the 4th opening 306, the 3rd opening 305 expose corresponding with the position of the first conductive layer 301 first and are situated between 303 surface of matter layer, the 4th opening 306 exposes 303 surface of first medium layer corresponding with the position of the second conductive layer 302 Second conductive layer 302.

The mask layer 304 is used to, when subsequent etching is used to be formed the opening of capacitance structure and damascene structure, make For mask, so as to make the opening for being subsequently used for being formed capacitance structure and damascene structure be formed simultaneously, and then being capable of letter Change processing step and process time.In the present embodiment, because the surface of the first conductive layer 301 is subsequently formed capacitance structure, The surface of second conductive layer 302 is subsequently formed damascene structure, therefore through the 3rd opening 305 of the mask layer 304 Position and the surfacial pattern for the capacitance structure being subsequently formed are defined, the 4th opening 306 defines the Damascus being subsequently formed The position of structure and surfacial pattern.

The formation process of the mask layer 304 is:Mask film is formed on 303 surface of first medium layer;Described Mask film surface the first photoresist layer of formation(It is not shown), first photoresist layer define the 3rd opening 305 and the 4th The correspondence position of opening 306;Using first photoresist layer as mask, the mask film is etched until exposing first medium Untill 303 surface of layer, the 3rd opening 305 and the 4th opening 306 are formed.

In the present embodiment, the material of the mask layer 304 is one or more groups in titanium nitride, titanium, tantalum nitride and tantalum Close;In another embodiment, the mask layer 304 includes the first sub- mask layer and the second sub- mask layer, the first sub- mask The material of layer is one or more combinations in titanium nitride, titanium, tantalum nitride and tantalum, and the material of the second sub- mask layer is oxidation One or more combinations in silicon, fire sand and silicon nitride;The second sub- mask layer be located at the described first sub- mask layer and Between first medium layer 303, or positioned at the described first sub- mask layer surface;When the described second sub- mask layer is located at the described first son During mask layer surface, the second sub- mask layer is used to, when exposure forms the first photoresist layer, be used as anti-reflecting layer;When described When second sub- mask is between the first sub- mask layer and first medium layer 303, the second sub- mask layer is used for as etching Etching stop layer when the 3rd opening 305 and the 4th opening 306 is formed, and first medium layer is exposed by certain over etching 303 surfaces.

Fig. 8 is refer to, in the surface of mask layer 304 and the 4th opening 306(As shown in Figure 7)Side wall and part Lower surface the second photoresist layer 307 of formation, second photoresist layer 307 exposes corresponding with the position of the second conductive layer 302 First medium layer 303 surface;Be mask with second photoresist layer 307, etch first medium layer 303, formed with Corresponding 5th opening 308 in the position of first conductive layer 301, and the 6th opening 309 corresponding with the position of the second conductive layer 302.

Second photoresist layer 307 defines first in the second opening being subsequently formed in the 4th 306 bottoms of opening The position of son opening and opening shape;Second due to being subsequently formed is open for forming damascene structure, and the big horse Scholar's leather structure includes contact bore portion and electric connection layer part, therefore second opening is needed by twice etching technique, with The first different son opening of size is formed, and is open with the second son of the first son opening insertion, and the second son opening Size is more than the described first son opening;And in the present embodiment, in order to simplify processing step, second opening forms electricity with being used for The first opening for holding structure is formed simultaneously, therefore first opening is formed also by twice etching technique.

Second photoresist layer 307 is formed by the exposure technology after spin coating proceeding and spin coating proceeding, exposes The section bottom surface of four openings 306, and the 3rd opening 305;Second photoresist layer 307 defines what is subsequently formed The size of first son opening in second opening, and the first son opening is used to be formed in damascene structure in subsequent technique Contact hole.

It is described 5th opening 308 and the 6th opening 309 formation process be:It is mask with second photoresist layer 307, Using anisotropic dry etch process etching the 3rd opening 305(As shown in Figure 7)With the 4th opening 306(Such as Fig. 7 institutes Show)The first medium layer 303 of bottom, forms the opening 309 of the 5th opening 308 and the 6th;The bottom of 6th opening 309 Distance to etching barrier layer 320 is not more than the depth of the second son opening in follow-up required the second opening formed, so as to protect Demonstrate,prove and be subsequently formed the etching technics of the second opening while the second son opening of depth needed for being formed, can open the first son Mouth exposes the surface of etching barrier layer 303;In addition, the 5th opening 308 is a part for the first opening subsequently formed, Because the described 5th opening 308 and the 6th opening 309 are formed in same etching technics, therefore its depth is identical;And then, rear After continuous removal second photoresist layer 307,309 bottoms of the 6th opening are etched again, to expose the second conductive layer When 302, the bottom of the 5th opening 308 can be etched simultaneously, to form the first opening for exposing the first conductive layer 301.

In the present embodiment, second photoresist layer 307 completely reveals the 3rd opening 305, makes what is subsequently formed The side wall of first opening is vertical with the surface of Semiconductor substrate 300;Because the side wall of the described first opening and the area of bottom are determined Overlapping area in the capacitance structure subsequently formed between two layers electrode, and the overlapping area determined and subsequently formed The capacitance of capacitance structure;Therefore, the electric capacity that the sidewall shape of first opening can be according to needed for the capacitor formed Value and specifically adjust, with increase or reduce follow-up institute's formation and first be open in the first metal layer and second metal layer between Overlapping area, makes produced capacitance meet process requirements.

In other embodiments, second photoresist layer(It is not shown)Also cover side wall and the part of the 3rd opening 305 303 surface of first medium layer of bottom, so that the 5th opening formed(It is not shown)Size be less than the described 3rd opening 305 size;Subsequently removing second photoresist layer, and perform etching again technique expose the first conductive layer 301 it Afterwards, the first opening formed is open by the 3rd son for exposing the first conductive layer 301(It is not shown), and with the described 3rd son 4th son opening of opening insertion(It is not shown)Constitute, and chi of the size more than the described 3rd son opening of the 4th son opening It is very little;Thus, it is possible to the sidewall area of the first opening subsequently formed be added, to increase the capacitance structure subsequently formed Capacitance.

Fig. 9 is refer to, second photoresist layer 307 is removed(As shown in Figure 8), and be mask with the mask layer 304, 4th opening 306 is etched using anisotropic dry etch process simultaneously(As shown in Figure 7), the 5th opening 308(As schemed Shown in 8)With the 6th opening 309(As shown in Figure 8)Bottom first medium layer 303, until exposing Semiconductor substrate 300 and being Only, the first opening 310 for exposing the first conductive layer 301 is formed, and exposes the second opening 311 of the second conductive layer 302.

It is described second opening 311 include expose the second conductive layer 302 first son opening 311a and bottom with it is described Second son opening 311b of the first son opening 311a insertions, the opening size of the second son opening 311b is more than the described first son Opening 311a opening size;The second opening 3111 formed is used to form damascene structure in subsequent technique.

Wherein, the first son opening 311a is formed by etching 309 bottoms of the 6th opening, the second son opening 311b is formed by etching 306 bottoms of the 4th opening;And the size of the 6th opening 309 is less than the described 4th opening 306 size, therefore, it is possible to form first son opening 311a of the opening size less than the second son opening 311b;First son is opened Mouth 311a is used for the contact hole formed in damascene structure in subsequent technique, and the second son opening 311b is used for rear The conductive layer formed in continuous technique in damascene structure.

In the present embodiment, after the second photoresist layer 307 are removed, before dry etch process, the mask layer 304 is sudden and violent Expose the 5th opening 308 corresponding with the position of the first conductive layer 301, and opened with the position of the second conductive layer 302 the corresponding 4th Mouth 306, and the bottom of the 4th opening 306 and the described 6th 309 insertions of opening, and the size of the 6th opening 309 is small In the size of the described 4th opening 306;Therefore, the anisotropic dry method after the second photoresist layer 307 of the removal is carved In etching technique, the bottom of the opening 308 of the 4th opening the 306, the 5th and the 6th opening 309 is etched simultaneously;Due to described Five openings 308 are identical with the depth of the 6th opening 309, therefore, when etching the 6th opening 309 to exposing the second conductive layer When 302, the 5th opening 308 can be also etched to the first conductive layer 301 is exposed, so that the first opening 310 and second Opening 311 is formed simultaneously, can simplify processing step, and save process time and cost.

Moreover, the bottom of the 6th opening 309 is not more than the second son opening to the distance of etching barrier layer 320 311b depth, when etching the bottom of the 4th opening 306 with the form required depth second sub- opening 311b, Neng Goubao The first son opening 311a that card etching 309 bottoms of the 6th opening are formed can completely reveal etching barrier layer 320;And The material of the etching barrier layer 320 is different from the material of first medium layer 303, when etching first medium layer 303, institute State etching barrier layer 320 has etching selection ratio relative to first medium layer 303, and therefore, the etching technics is described Stop at etching barrier layer 320;And after the first opening 310 and the second opening 312 is formed, remove first opening 310 With the etching barrier layer 320 of the second 312 bottoms of opening, and material due to the etching barrier layer 320 and first medium layer 303 Material it is different, therefore remove the technique of the etching barrier layer 320 and will not damage the opening of the first opening 310 and second 312 pattern.

In addition, forming the first opening 310 and the second opening 310 simultaneously, making subsequently can be simultaneously in the described first opening 310 With filling metal in the second opening 311 and carrying out CMP process, to form damascene structure and capacitance structure, enter One step simplifies technique;And processing step can not only be saved by filling metal simultaneously and polishing, additionally it is possible to reduce chemically mechanical polishing The number of times of technique, to reduce glossing to the damage of the semiconductor device surface formed, makes formed semiconductor devices Performance it is stable.

In other embodiments, second photoresist layer(It is not shown)Also cover side wall and the part of the 3rd opening 305 303 surface of first medium layer of bottom, so that the 5th opening formed(It is not shown)Size be less than the described 3rd opening 305 size;So that after second photoresist layer is removed, when etching the 5th opening 308, the 3rd opening Bottom is also etched simultaneously, can form the 3rd son opening for exposing the first conductive layer 301(It is not shown), and with described 4th son opening of three son opening insertions(It is not shown)Constitute, and the size of the 4th son opening is more than the described 3rd son opening Size;So as to the sidewall area increase of first opening, by increasing capacitance it is possible to increase be subsequently formed in first in the described first opening Overlapping area between metal level and second metal layer, increases the capacitance of the capacitance structure subsequently formed with this.

Figure 10 is refer to, is situated between in the described first opening 310 and the side wall and lower surface of the second opening 311 and first 303 surface of matter layer form the first metal layer 312.

The material of the first metal layer 312 is ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese;The first metal layer 312 formation process is chemical vapor deposition method or physical gas-phase deposition;First in the described first opening 310 Metal level 312 is used for as one layer of electrode in the capacitance structure formed, is applied in partially by first conductive layer 301 Pressure;The first metal layer 312 in the described second opening 311 is used for when subsequently using electroplating technology formation second metal layer As conductive layer to grow copper product;In addition, the first metal layer 312 positioned at 303 surface of first medium layer can also be It is subsequently formed after second metal layer, when carrying out CMP process, is used as polishing stop layer.

Figure 11 is refer to, forming second in the side wall of the described first opening 310 and the surface of the first metal layer 312 of bottom is situated between Matter layer 313 and the 3rd metal level 314 on the surface of second dielectric layer 313.

The material of the second dielectric layer 313 is high K dielectric material;The high K dielectric material includes:HfO2、ZrO2、 HfSiNO、Al2O3Or SbO;The material of 3rd metal level 314 is ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese;Described Second medium layer 313 is used to be used as the dielectric layer between two layers of electrode in the capacitance structure subsequently formed;Due to described second Dielectric layer 313 can not be conductive, it is therefore desirable to forms the 3rd metal level 314, for subsequently using electroplating technology described When forming second metal layer in the first opening 310, conductive layer is used as.

In the present embodiment, the formation process of the metal level 314 of second dielectric layer 313 and the 3rd is:Described first The surface of metal level 312 covers second medium film;In the second medium film surface the 3rd metallic film of formation;Described The 3rd metal film surfaces formation photoresist layer in one opening 310 and 303 surface of part first medium layer;With the photoetching Glue-line is mask, etches the 3rd metallic film and second medium film.After the etching technics, first son is opened The son openings of mouth 311a and second 311b side wall and the 3rd metallic film and second medium film of lower surface are removed, subsequently Second metal layer can be formed on the surface of the first metal layer 312 in the second opening 311, to form damascene structure.

In other embodiments, the 3rd metal level(It is not shown)The first metal also on covering first medium layer 303 The surface of the first metal layer 312 in 312 surface of layer, and the second opening 311;The metal level of second dielectric layer 313 and the 3rd Formation process be:Second medium film is covered on the surface of the first metal layer 312;Described first opening 310 in and Second medium film surface formation photoresist layer on part first medium layer 303;Using the photoresist layer as mask, etching the First son opening of two openings 311 and the side wall of the second son opening and the second medium film of lower surface, form second medium Layer;The 3rd metal level is covered in the second dielectric layer and the first metal layer surface.

Figure 12 is refer to, after the metal level 314 of second dielectric layer 313 and the 3rd is formed, in the described first opening 310 (As shown in figure 11)With the second opening 311(As shown in figure 11)It is interior to form the full opening 311 of first opening 310 and second of filling Second metal layer 315.

In the present embodiment, the material of the second metal layer 315 is copper;The second gold medal in the described first opening 310 Belong to layer 315 as another layer of electrode in the capacitance structure formed, the second metal layer 315 in the second opening 311 is used In formation damascene structure;Therefore, one layer of electrode of the capacitance structure formed and the material of damascene structure are copper; And the resistance of copper is relatively low, during using copper as the electrode of capacitance structure, the energy consumption of capacitance structure can be reduced, capacitance structure is improved Performance;Accordingly, due to the low resistance characteristic of copper, when the characteristic size of semiconductor devices constantly reduces, using copper as material Damascene structure disclosure satisfy that the process requirements being electrically interconnected in device.

Because the material of the second metal layer 315 is copper, therefore the formation process of the second metal layer 315 is plating Technique, can form the preferable second metal layer 315 of quality;And the metal level 314 of the first metal layer 312 and the 3rd is used for In the electroplating technology for forming second metal layer 315, as conductive layer to grow copper product.

In other embodiments, the formation process of the second metal layer 315 can also be chemical vapor deposition method, thing Physical vapor deposition technique or physical gas-phase deposition and electroplating technology are combined;Wherein, when the second metal layer 315 When formation process is chemical vapor deposition method or physical gas-phase deposition, the 3rd metal level 314 can not be formed, and Directly the second metal layer 315 is formed in the first opening 310 and the second opening 311.

It refer to Figure 13, remove the second metal layer 315 higher than 303 surface of first medium layer, second dielectric layer 313, the One metal level 312 and mask layer 304(As shown in figure 12).

Due in the present embodiment, second metal layer 315 is formed simultaneously in the opening 312 of the first opening 305 and second(Such as Shown in Figure 11), therefore only need that using a CMP process second higher than 303 surface of first medium layer can be removed Metal level 315, the 3rd metal level 314, second dielectric layer 313, the first metal layer 312 and mask layer 304;So as to, it is to avoid in order to Form capacitance structure and damascene structure respectively and CMP process is employed many times, chemical machinery throwing can be reduced The number of times of light technique;And the number of times for reducing CMP process can not only save process costs, additionally it is possible to reduce chemistry Mechanical polishing process makes the performance of formed semiconductor devices more steady for the damage of the semiconductor device surface formed It is fixed.

Second metal layer 315 and the first metal layer 312 in the described first opening 310 are used as the capacitive junctions formed Two layers of electrode of structure, and the second dielectric layer 313 is used to isolate two layers of electrode, constitutes the electricity of metal-insulator-metal Hold structure;And be formed at the 3rd metal level 314 between second dielectric layer 313 and second metal layer 315 and formed for conductive material, Therefore the performance of formed capacitance structure is not interfered with.

Second metal layer 315 in the described second opening 311 is used to be used as damascene structure;Wherein, described One son opening 311a in second metal layer 315 as damascene structure contact hole, and it is described second son opening 311b in Second metal layer 315 as damascene structure interconnection layers.

In the present embodiment, the first opening 310 for forming capacitance structure, and for forming the second of damascene structure Opening 311 is mask with mask layer 304, is formed while etching, can save processing step and process costs;Further, since institute State the first opening 310 and the second opening 311 is formed simultaneously, can be open shape in 311 in the described first opening 310 and second simultaneously Into the first metal layer 312;And formed in the first opening 310 after second dielectric layer 313, while in the described second opening 311 Second metal layer 315 is formed with the first opening 310;Moreover, being that can remove to be higher than only with a CMP process Second metal layer 315, second dielectric layer 313, the first metal layer 312 and the mask layer 304 on 303 surface of first medium layer;Therefore, The number of times of chemically mechanical polishing reduces, it is to avoid because multiple chemical mechanical polishing process is to the semiconductor device surface that is formed Damage, improves the stability of formed semiconductor devices.

In summary, in first medium layer surface formation mask layer, the mask layer define it is follow-up needed for formed the The position and opening shape of one opening and the second opening;Using the mask layer described in mask etching first medium layer until exposure Untill going out the first conductive layer and the second conductive layer, it is open in the first conductive layer surface formation first, for forming capacitance structure, in Second conductive layer surface formation second is open, for forming damascene structure;Wherein, second opening includes exposing the First son opening of two conductive layers and bottom and the second son of the described first son opening insertion are open, the second son opening Opening size be more than described first son opening opening size;First opening and the second opening use same mask layer, Formed in same etching technics, processing step and process time can be saved, and it is cost-effective.

In addition, after the first opening and the second opening is formed, the side wall and lower surface of the first opening and the second opening The first metal layer is covered simultaneously;And formed on the first metal layer surface of the first opening after second dielectric layer, while described Form the full second metal layer of filling in first opening and the second opening, and remove second metal layer higher than first medium layer, the Second medium layer, the first metal layer and mask layer;Due to the first metal layer and the second gold medal in the described first opening and the second opening Category layer is formed simultaneously, can further simplify technique;Moreover, second metal layer, second medium higher than first medium layer surface Layer, the first metal layer and mask layer are removed simultaneously, are reduced the number of times of the removal technique, can be avoided because repeatedly removing work Skill and cause the damage to first medium layer surface and other device surfaces for being formed at semiconductor substrate surface, make what is formed The pattern of semiconductor devices is good, and performance is stable.

Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention Any simple modification, equivalent variation and modification for being made to above example of technical spirit, belong to technical solution of the present invention Protection domain.

Claims (16)

1. a kind of forming method of semiconductor structure, it is characterised in that including:
There is provided has the first conductive layer and the second conductive layer, first conductive layer in Semiconductor substrate, the Semiconductor substrate Flushed with the surface of the second conductive layer and the surface of Semiconductor substrate, the Semiconductor substrate, the first conductive layer and second are conductive The surface of layer has first medium layer;
In first medium layer surface formation mask layer, there is the 3rd opening and the 4th opening in the mask layer, described the Three openings expose first medium layer surface corresponding with the position of the first conductive layer, and the 4th opening exposes to be led with second The corresponding conductive layer of first medium layer surface second in position of electric layer;
Photoresist layer, the photoresist are formed in the mask layer surface and the 4th side wall being open and section bottom surface Layer exposes the correspondence position of the second conductive layer;
Using the photoresist layer as mask, using anisotropic dry etch process etching the 3rd opening and the 4th opening The first medium layer of bottom, forms the 5th opening corresponding with the first conductive layer position, and corresponding with the second conductive layer position The 6th opening;
The photoresist layer is removed, and using the mask layer as mask, is etched using anisotropic dry etch process described The bottom of 4th opening, the 5th opening and the 6th opening is untill Semiconductor substrate is exposed, and it is conductive that formation exposes first First opening of layer, and the second opening of the second conductive layer is exposed, second opening includes exposing the second conductive layer First son opening and bottom and the second son of the described first son opening insertion are open, the opening size of the second son opening More than the opening size of the described first son opening, described first is open for forming capacitance structure, and described second is open for shape Into damascene structure;
In the side wall and lower surface and first medium layer surface the first metal of formation of the described first opening and the second opening Layer;
Second dielectric layer is formed in the side wall of the described first opening and the first metal layer surface of bottom;
After the second dielectric layer is formed, formed in the described first opening and the second opening full first opening of filling and The second metal layer of second opening;
Remove second metal layer, second dielectric layer, the first metal layer and the mask layer higher than first medium layer surface.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the photoresist layer also covers the 3rd and opened The side wall of mouth and the first medium layer surface of section bottom.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the mask layer includes the first sub- mask Layer, the material of the first sub- mask layer is one or more combinations in titanium nitride, titanium, tantalum nitride and tantalum.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that the mask layer is also covered including the second son Film layer, the second sub- mask layer is located between the described first sub- mask layer and first medium layer, or covered positioned at first son Film surface, the material of the second sub- mask layer is one or more combinations in silica, fire sand and silicon nitride.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include:The second dielectric layer table Face has the 3rd metal level, and the material of the 3rd metal level is ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the second dielectric layer and the 3rd metal Layer formation process be:Second medium film is covered on the first metal layer surface;In the second medium film surface shape Into the 3rd metallic film;Remove the first son opening of the second opening and the side wall of the second son opening and the 3rd metal of lower surface Film and second medium film.
7. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the 3rd metal level also covers first The first metal layer surface in the first metal layer surface of dielectric layer surface, and the second opening.
8. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the second dielectric layer and the 3rd metal Layer formation process be:Second medium film is covered on the first metal layer surface;Remove the first son opening of the second opening With the side wall and the second medium film of lower surface of the second son opening, second dielectric layer is formed;In the second dielectric layer and The first metal layer surface covers the 3rd metal level.
9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the second metal layer is Copper.
10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the formation work of the second metal layer Skill is chemical vapor deposition method, physical gas-phase deposition, electroplating technology or physical gas-phase deposition and electroplating technology phase With reference to.
11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the first metal layer is Ruthenium, titanium, titanium, tantalum nitride, tantalum or cupromanganese.
12. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the second dielectric layer is High K dielectric material.
13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that the high K dielectric material includes: HfO2、ZrO2、HfSiNO、Al2O3Or SbO.
14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the first medium layer is Silica, silicon nitride or low-K dielectric material.
15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the Semiconductor substrate and first is situated between There is etching barrier layer, the material of the etching barrier layer is silica, silicon nitride or low-K dielectric material, and institute between matter layer State etching barrier layer different from the material of first medium layer.
16. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first conductive layer and second is led The material of electric layer is copper, tungsten or aluminium.
CN201210492711.6A 2012-11-27 2012-11-27 The forming method of semiconductor structure CN103839878B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329234B1 (en) * 2000-07-24 2001-12-11 Taiwan Semiconductor Manufactuirng Company Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow
US6399495B1 (en) * 2000-11-06 2002-06-04 Ling-Hsu Tseng Copper interconnections for metal-insulator-metal capacitor in mixed mode signal process
TW200536041A (en) * 2004-04-20 2005-11-01 Powerchip Semiconductor Corp Method of manufacturing a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329234B1 (en) * 2000-07-24 2001-12-11 Taiwan Semiconductor Manufactuirng Company Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow
US6399495B1 (en) * 2000-11-06 2002-06-04 Ling-Hsu Tseng Copper interconnections for metal-insulator-metal capacitor in mixed mode signal process
TW200536041A (en) * 2004-04-20 2005-11-01 Powerchip Semiconductor Corp Method of manufacturing a semiconductor device

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