CN103839863A - Device for producing compound semiconductor and wafer retainer - Google Patents

Device for producing compound semiconductor and wafer retainer Download PDF

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Publication number
CN103839863A
CN103839863A CN201310589003.9A CN201310589003A CN103839863A CN 103839863 A CN103839863 A CN 103839863A CN 201310589003 A CN201310589003 A CN 201310589003A CN 103839863 A CN103839863 A CN 103839863A
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China
Prior art keywords
wafer
loading
compound semiconductor
loading surface
wafer holder
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Granted
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CN201310589003.9A
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Chinese (zh)
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CN103839863B (en
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安原秀树
吉村和孝
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Toyoda Gosei Co Ltd
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Toyoda Gosei Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4584—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally the substrate being rotated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel

Abstract

Variations in composition in epitaxial growth of a compound semiconductor are suppressed. A wafer retainer 30 that retains a wafer W in an MOCVD device includes a carrying member 40 that carries the wafer W and a ring-like regulating member 50 that is carried on the carrying member and regulates movement of the wafer W carried on the carrying member 40. On a top surface of the carrying member 40, a wafer carrying surface for carrying the wafer and a ring carrying surface for carrying the regulating member are provided. The wafer carrying surface is formed to protrude upwardly compared to the ring carrying surface and has a convex shape in which a center portion is higher than a circumferential edge portion, and an arithmetic average roughness Ra of the wafer carrying surface is set at not more than 0.5 [mu]m.

Description

The manufacturing installation of compound semiconductor and wafer holder
Technical field
The present invention relates to manufacturing installation and the wafer holder of compound semiconductor.
Background technology
In recent years, use the LED(Light Emitting Diode of compound semiconductor), FET(Field Effect Transistor), HEMT(High Electron Mobility Transistor) etc. various semiconductor elements be widely used gradually.
As making one of method of such compound semiconductor crystal growth, known chemical vapor-phase growing method (Chemical Vapor Deposition: hereinafter referred to as CVD method).In CVD method, the unstrpped gas of the raw material that becomes compound semiconductor crystal is supplied with together with carrier gas in reative cell, in reative cell, near of the substrate being heated unstrpped gas carried out to thermal decomposition, on substrate, make compound semiconductor crystal epitaxial growth, obtain thus compound semiconductor wafer.
The prior art of recording as communique, has a kind of processing unit, and it has: locating ring parts, the handled object that becomes substrate is loaded the support area in mounting table by it, and to along load in the one side of the handled object of support area to move forward into professional etiquette fixed; With mobile restriction mechanism, it is located at locating ring parts and mounting table, allows the relatively moving and limiting relatively move (with reference to the patent documentation 1) along ring component radially to locating ring parts and mounting table that the thermal contraction of locating ring parts is poor caused.
Formerly technical literature
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Application Publication 2001-525997 communique
Summary of the invention
In CVD method, conventionally near at substrate is carried out thermal decomposition to unstrpped gas and substrate is heated.Now, for example, if the different position on substrate (peripheral side and center side) substrate temperature there are differences, the composition of the compound semiconductor layer forming on substrate is sometimes according to position on substrate and change.Here, if the compound semiconductor layer forming on substrate produces composition inhomogeneous (composition deviation), in the case of being the light-emitting component as LED, can be because of the position on substrate, emission wavelength produces difference, in the case of being the such active element of FET, HEMT, to understand because of the position on substrate, the degree of excursion in electronics, hole produces the situation of difference.
Summary of the invention
Composition while the object of the invention is to suppress to make compound semiconductor epitaxial growth is inhomogeneous.
The present invention is a kind of manufacturing installation of compound semiconductor, is to use chemical vapor-phase growing method on wafer, to form the manufacturing installation of the compound semiconductor of compound semiconductor layer, it is characterized in that having: the reaction vessel of accommodating described wafer in inside; Be configured in described reaction vessel, with the wafer holder that keeps this wafer facing to the mode of top that is formed of the described compound semiconductor layer in described wafer; In from outside to described reaction vessel, supply with the supply unit of the unstrpped gas of the raw material that becomes described compound semiconductor layer; With the heating part that described wafer holder is heated, described wafer holder comprises: the loading part that loads described wafer; Be loaded on described loading part, and limit the limiting part of the movement of this wafer by the side face that encirclement is loaded on the described wafer of this loading part, described loading part has and loads the 1st loading surface of described wafer and be located at the surrounding of the 1st loading surface and load the 2nd loading surface of described limiting part, described the 1st loading surface, form highlightedly than described the 2nd loading surface, and the face shape with the convex of center side protuberance compared with peripheral side, the arithmetic average roughness Ra of the 1st loading surface is below 0.5 μ m.
In the manufacturing installation of such compound semiconductor, can make it is characterized in that, also have: can be configured in rotatably in described reaction vessel, can support rotatably the support of described wafer holder, described supply unit is supplied with described unstrpped gas from top or the side of described support.
In addition, can make it is characterized in that, described heating part is heated to 700 DEG C above below 1200 DEG C by described wafer.
Consider from other viewpoints, the present invention is a kind of wafer holder, it is to use chemical vapor-phase growing method to use form the manufacturing installation of compound semiconductor of compound semiconductor layer on wafer in, the wafer holder that this wafer is kept, it is characterized in that, comprising: the loading part that loads described wafer; Be loaded on described loading part, and limit the limiting part of the movement of this wafer by the side face that encirclement is loaded on the described wafer of this loading part, described loading part has: load the 1st loading surface of described wafer and be located at the surrounding of this wafer loading surface and load the 2nd loading surface of described limiting part, described the 1st loading surface forms highlightedly than described the 2nd loading surface, and the face shape with the convex of center side protuberance compared with peripheral side, the arithmetic average roughness Ra of the 1st loading surface is below 0.5 μ m.
In such wafer holder, can make it is characterized in that, described chemical vapor-phase growing method is organic metal vapor growth method, described compound semiconductor layer is III nitride semiconductor layer.
In addition, can make it is characterized in that, described wafer is made up of the sheet material that has been pre-formed compound semiconductor layer on substrate.
And then, can make it is characterized in that, described loading part is form on the surface of the base material being made up of carbon the coating being made up of SiC and form, described limiting part is made up of quartz.
According to the present invention, the composition can suppress to make compound semiconductor epitaxial growth time is inhomogeneous.
Brief description of the drawings
Fig. 1 represents MOCVD(Metal Organic Chemical Vapor Deposition) synoptic diagram of an example of the section constitution of device.
Fig. 2 is the II-II sectional view of the MOCVD device shown in Fig. 1.
Fig. 3 is for the figure for keep an example of the formation of the wafer holder of wafer at MOCVD device is described.
Fig. 4 is the exploded perspective view of wafer holder.
Fig. 5 is the figure of the formation of the loading part for wafer holder is described.
Fig. 6 is the figure of the formation of the limiting part for wafer holder is described.
Fig. 7 is the longitudinal section of wafer holder.
Fig. 8 is the figure of an example of the formation of the wafer loading surface for loading part is described.
Fig. 9 is the sectional view that represents an example of the formation of the laminated semiconductor wafer that utilizes the manufacture of MOCVD device.
Figure 10 be represent the 3D shape of wafer loading surface during embodiment 1 and comparative example 1～comparative example 3 are separately, wafer holder and the laminated semiconductor wafer that obtains in the figure of relation of PL Wavelength distribution.
Embodiment
Below, with reference to accompanying drawing, embodiments of the present invention are elaborated.
The formation > of < MOCVD device
Fig. 1 is the MOCVD(Metal Organic Chemical Vapor Deposition that represents to be used as one of chemical vapor-phase growing method: organic metal vapor growth method), the figure of the section constitution of MOCVD device 1.In addition, Fig. 2 is the II-II sectional view of the MOCVD device 1 shown in Fig. 1.
This MOCVD device 1 has following formation: with wafer W (by substrate 110(described later with reference to Fig. 9) or on substrate 110, form laminated base plate 100(that more than 1 layer compound semiconductor layer forms with reference to Fig. 9) form) and crystalline growth configure facing to the mode of top, will become the unstrpped gas of carrying out the epitaxially grown raw material that becomes compound semiconductor crystal from the top of wafer W or the upper surface side of side direction wafer W is supplied with.
MOCVD device 1 has: the reaction vessel 10 that is formed with reative cell in inside; Be configured in the reative cell of reaction vessel 10, support the support 20 of wafer holder 30 described later.
Wherein, reaction vessel 10 has: resettlement section 11, and it has shape cylindraceous and is formed with opening upward and accommodates support 20 therein; Cap 12, the top that it has discoideus shape and is arranged on this resettlement section 11.
Here, resettlement section 11 and cap 12 are made up of the metal of stainless steel etc.In addition, cap 12 opens and closes freely and installs with respect to resettlement section 11, in the situation that closing with respect to resettlement section 11, forms reative cell together with resettlement section 11.In addition,, at the position relative with cap 12, resettlement section 11, the seal of not shown O shape ring etc. is installed.
In addition, be formed with for from being located at the through hole of outside gas supply mechanism (not shown) to reative cell internal feed unstrpped gas at the central portion of cap 12.And, be connected to this through hole as the supply pipe 13 of an example of supply unit.And, from the position of the central portion bias of cap 12, be also formed with for the through hole from visual observation reative cell inside.
On the other hand, in the bottom surface of resettlement section 11, be formed through and be useful on multiple blast pipes that the unstrpped gas being supplied in reative cell is discharged to the outside of reative cell.And, be also formed with the through hole (not shown) for axle 21 described later is passed through in the bottom central part of resettlement section 11.
The unstrpped gas using in MOCVD device 1 is described here.
In the present embodiment, upper in wafer W (substrate 110 or laminated base plate 100), utilize MOCVD device 1, form the III nitride semiconductor layer as an example of compound semiconductor layer.For this reason, as raw material, use the organic metal that comprises III family element and the ammonia NH that comprises nitrogen 3.But, because organic metal is mainly liquid charging stock, so adopt nitrogen N in liquid organic metal 2with hydrogen H 2carry out bubbling, make nitrogen N by what obtain 2with hydrogen H 2and the organic metal gas MO that organic metal mixes supplies with as unstrpped gas.In the present embodiment, carry out organic metal gas MO and ammonia NH from supply pipe 13 3supply.In addition, also carry out carrier gas (for example hydrogen H from supply pipe 13 2) supply.
Moreover, as organic metal, can enumerate the trimethyl gallium (TMG) of the Ga that for example comprises III family or triethyl-gallium (TEG), for example comprise III family the trimethyl aluminium (TMA) of Al or triethyl aluminum (TEA), for example comprise III family trimethyl indium (TMI) or the triethylindium (TEI) of In.In addition, as the dopant of N-shaped, can be by monosilane (SiH 4), disilane (Si 2h 6) use as Si raw material, or, by Germane gas (GeH 4), tetramethyl germanium ((CH 3) 4ge), tetraethyl germanium ((C 2h 5) 4ge) use as Ge raw material.On the other hand, as the dopant of p-type, can be by for example two (cyclopentadienyl group) magnesium (Cp 2or two (ethyl cyclopentadienyl group) magnesium (EtCp Mg) 2mg) use as Mg raw material.And, also can use hydrazine (N 2h 4) replace ammonia.Moreover, also can be for also contain the formation of other III family element, the dopant that can contain Ge, Si, Mg, Ca, Zn, Be etc. as required beyond above-mentioned organic metal gas MO.And, be not limited to have a mind to the element that adds, also sometimes contain the impurity that depends on membrance casting condition etc. and contain inevitably and contained trace impurity in raw material, reaction tube material.
In addition, support 20, has discoideus shape, with a face be surface upward, and another side is that back side mode is downward configured in resettlement section 11.And the material that support 20 has applied by the outside of the base material being formed by carbon (C) coating being formed by SiC forms.Here, in the face side of support 20,6 rounded recesses are in a circumferential direction uniformly-spaced to form respectively.On the other hand, in the rear side of support 20, be provided with from its central portion metal axle 21 downward, this axle 21 via be located at resettlement section 11 bottom central part through hole and be projected into the outside of reaction vessel 10.And support 20, gives actuating force by the outside from reaction vessel 10 to axle 21 and can be along the arrow A direction rotation shown in Fig. 1 and Fig. 2.
Moreover, in the inside of support 20, be formed with for the bottom surface to 6 recesses being located at support 20 and supply with nitrogen N 2through hole (not shown).Nitrogen N is supplied with in the bottom surface that is located at 6 recesses on support 20 here, 2method, can set aptly change.
In addition, in 6 surperficial recesses of being located at support 20, be provided with and there is respectively circular wafer holder 30.These wafer holders 30 are formed with circular recess at face upward respectively, in each recess, wafer W are installed.Moreover, being formed with gap being located between the recess of support 20 and wafer holder 30, these 6 wafer holders 30 are installed and removed freely with respect to support 20.
Here, wafer W is the recess that mode that being formed of crystal exposed towards outside remains on wafer holder 30 with its crystalline growth face.Moreover wafer W is installed and removed freely with respect to wafer holder 30.And, each wafer holder 30 in each self-sustaining under the state of wafer W, by the nitrogen N being supplied to via above-mentioned not shown through hole 2flow and along the arrow B direction rotation shown in Fig. 2.Moreover, narrate in the back about the concrete structure of wafer holder 30.
In addition, between the rear side of support 20 and the bottom surface of resettlement section 11 of this MOCVD device 1, be provided with across support 20 and wafer holder 30 and the heating part 60 that wafer W is heated.This heating part 60 has the shape that is formed with the ring-type that makes the hole that axle 21 runs through, and contains coil therein.Moreover heating part 60 is by supplying with electric current and the carbon that forms support 20 is carried out to electromagnetic induction heating coil.
And; below the cap 12 of this MOCVD device 1 and support 20 above; be provided with guard block 70, thereby product that this guard block 70 generates by the reaction preventing because being supplied to the unstrpped gas in reative cell adheres to, piles up protection cap 12 at the inwall of cap 12.Here, guard block 70 has circle, same with cap 12, is formed with from outside to the through hole of the internal feed unstrpped gas of reative cell at central portion.In addition, on guard block 70, be similarly also formed with for the through hole from visual observation reative cell inside with cap 12.
And guard block 70, utilizes not shown installing component to be arranged on cap 12.Moreover installing component is installed and removed freely with respect to cap 12, accompany therewith, guard block 70 also can be installed and pull down with respect to cap 12.In addition, thus guard block 70 is fixed by utilizing installing component to be arranged on cap 12.
Moreover, as shown in phantom in Figure 2, guard block 70, under the state of having closed cap 12 with respect to resettlement section 11 from above observe, configure in the mode of whole that covers support 20.Therefore 6 pieces of wafer W that, are held in support 20 across each wafer holder 30 are positioned at the below of guard block 70.
In addition; between the support 20 and guard block 70 of this MOCVD device 1; exhaust component 80 is installed, this exhaust component 80 by be fed in reative cell and for the epitaxially grown unstrpped gas of crystal etc. to the discharge pipe side guiding of bottom surface of being located at resettlement section 11.This exhaust component 80 has the shape of ring-type.In addition, the inwall of exhaust component 80, the position outside being positioned at than 6 recesses being located at support 20.And, be formed with the multiple through holes (not shown) for the unstrpped gas after using etc. is discharged to outside at the inwall of exhaust component 80.Moreover, exhaust component 80, with the relative portion of the acies side of the peripheral part of support 20, form in the mode of the rotation that do not hinder support 20.In addition, in Fig. 2, omitted the record of exhaust component 80.
And, on the top of through hole (not shown) of cap 12 of being located at this MOCVD device 1, monitoring arrangement 90 is installed.This monitoring arrangement 90 monitors the state of the inside of reative cell by being located at respectively the through hole of cap 12 and guard block 70; more specifically, the state of the state of epitaxially grown crystal and the warpage of wafer W etc. is carried out in supervision in the wafer W that is held in support 20 across wafer holder 30.Moreover, in order to prevent flowing into unstrpped gas etc. by these through holes to monitoring arrangement 90, supply with for example nitrogen N from monitoring arrangement 90 to reative cell 2deng purge gas (purge gas).
The formation > of < wafer holder
Fig. 3 is the figure representing for keep an example of the formation of the wafer holder 30 of wafer W at the MOCVD device 1 shown in Fig. 1 etc.Here, Fig. 3 (a) is the vertical view from keeping wafer W unilateral observation wafer holder 30, and Fig. 3 (b) is the end view of observing the wafer holder 30 shown in Fig. 3 (a) from IIIB direction.In addition, Fig. 4 is the exploded perspective view of the wafer holder 30 shown in Fig. 3.But the wafer W that is held in wafer holder 30 is also shown in Fig. 4 in the lump.
The wafer holder 30 of present embodiment, has: the loading part 40 of loaded with wafers W; The limiting part 50 limiting with upper surface side by being arranged on loading part 40 and to being loaded into the movement of wafer W of loading part 40.Wherein, the shape that loading part 40 is in the form of annular discs, limiting part 50 shape in the form of a ring.And in the wafer holder 30 of present embodiment, with respect to loading part 40, limiting part 50 is installed and removed freely.
Fig. 5 is the figure of the formation of the loading part 40 for wafer holder 30 is described.Here, Fig. 5 (a) is for loading part 40 being described, loading the figure of the structure of the upper surface 41 of limiting part 50 and wafer W, Fig. 5 (b) for loading part 40 is described, be loaded into the figure of the structure of the bottom surface 42 of support 20.This loading part 40 with above-mentioned support 20(with reference to Fig. 1) similarly, the material that has been applied the coating being formed by SiC by the outside of the base material being formed by carbon (C) forms.
First, as shown in Fig. 5 (a), the upper surface 41 of loading part 40 has: for the wafer loading surface 411 of loaded with wafers W; Arrange highlightedly laterally with periphery from wafer loading surface 411, for loading the annular loading surface 412 of limiting part 50 of ring-type.Here, in the upper surface 41 shown in Fig. 5 (a), as the wafer loading surface 411 of an example of the 1st loading surface, than the annular loading surface 412 of the example as the 2nd loading surface, to nearby side-prominent (also with reference to Fig. 7 described later) in figure.
In addition, the profile of annular loading surface 412 is rounded.On the other hand, the profile of wafer loading surface 411 is also substantially rounded, but becomes: copy the shape of loaded wafer W, the profile of the incised notch portion with linearity corresponding with the formation position of the directional plane (orientation flat) in wafer W.Moreover in upper surface 41, wafer loading surface 411 and annular loading surface 412 configure with concentric circles.
And, on annular loading surface 412, be the 1st slot part the 4121, the 2nd slot part 4122 and the 3rd slot part 4123 that forms radially inboard depression in directed graph with the interval of 90 °.Moreover in this example, the 2nd slot part 4122 is with the 3rd slot part 4123 across wafer loading surface 411 and relative, the incised notch portion of the 1st slot part 4121 and the linearity corresponding with above-mentioned directional plane is across wafer loading surface 411 and relative.
Then, as shown in Fig. 5 (b), the bottom surface 42 of loading part 40 has: the face that is loaded 421 that is loaded in the ring-type on support 20; From be loaded face 421 outside periphery to foreign side arrange highlightedly and in the time being loaded on support 20 with regulation the gap outside opposite face 422 relative with support 20; Be located at than the inner inner side of periphery of inner side that is loaded face 421, in the time being loaded on support 20 with the gap inner side opposite face 423 relative with support 20 of regulation; With the central central indentation 424 that is located at inner side opposite face 423.Here, in the bottom surface 42 shown in Fig. 5 (b), be loaded face 421 compared with outside opposite face 422, inner side opposite face 423 and central indentation 424 to nearby side-prominent (also with reference to Fig. 7 described later) in figure.
Fig. 6 is the figure of the formation of the limiting part 50 for wafer holder 30 is described.Here, the figure of the structure of exposing face 51 that Fig. 6 (a) exposes upward for limiting part 50 is described, formed wafer holder 30 together with loading part 40 time, the figure of the structure of the contact-making surface 52 that Fig. 6 (b) contacts with the annular loading surface 412 of loading part 40 for limiting part 50 is described, formed wafer holder 30 together with loading part 40 time.This limiting part 50 is made up of the material different from above-mentioned loading part 40, for example quartz.
The profile of the limiting part 50 of present embodiment substantially in the form of a ring.But, the rounded shape in outside of limiting part 50, but its inner side becomes the shape with position corresponding with the formation position of the directional plane in wafer W, linearity.
First, as shown in Figure 6 (a), the face 51 that exposes of limiting part 50 is made up of smooth face.
On the other hand, as shown in Figure 6 (b), on the contact-making surface 52 of limiting part 50, be radially with the interval of 90 ° and form in directed graph the 1st nearby side-prominent the 521, the 2nd ridge portion 522 of ridge portion and the 3rd ridge portion 523.Moreover, in this example, space in ring of the 2nd ridge portion 522 and the 3rd ridge portion 523 and relative, the space of the position of the 1st ridge portion 521 and the linearity corresponding with above-mentioned directional plane in encircling and relative.
Fig. 7 is that the limiting part 50 shown in the loading part 40 shown in constitutional diagram 5 and Fig. 6 is that form, the longitudinal section of the wafer holder 30 shown in Fig. 3.Here, Fig. 7 (a) presentation graphs 3(a) in VIIA-VIIA cross section, Fig. 7 (b) presentation graphs 3(a) in VIIB-VIIB cross section, Fig. 7 (c) presentation graphs 3(a) in VIIC-VIIC cross section.
In the present embodiment, install so that the contact-making surface 52 in limiting part 50 contacts the mode of the annular loading surface 412 in the upper surface 41 of loading part 40, form thus wafer holder 30.Here, in the present embodiment, compared with the external diameter of the annular loading surface 412 in loading part 40, the internal diameter of limiting part 50 is set slightly greatly (large 1mm left and right).
And, in wafer holder 30, so that the correspondence position of the directional plane in loading part 40 mode consistent with the correspondence position of the directional plane in limiting part 50 carried out the installation (embedding) of limiting part 50 with respect to loading part 40.Now, for example as shown in Figure 7 (a), in the 1st slot part 4121 on the annular loading surface 412 in the upper surface 41 of being located at loading part 40, embed the 1st ridge portion 521 having on the contact-making surface 52 of being located at limiting part 50.In addition, for example as shown in Figure 7 (b) shows, in the 2nd slot part 4122 on the annular loading surface 412 of being located at loading part 40, embedding has the 2nd ridge portion 522 on the contact-making surface 52 of being located at limiting part 50, in the 3rd slot part 4123 on the annular loading surface 412 of being located at loading part 40, embed the 3rd ridge portion 523 having on the contact-making surface 52 of being located at limiting part 50.Thus, in the wafer holder 30 of present embodiment, can suppress limiting part 50 rocking with respect to loading part 40.
In addition, in the present embodiment, compare with wafer loading surface 411 in the upper surface 41 of loading part 40 and the high extent of step of annular loading surface 412, the height (exposing the distance of face 51 and contact-making surface 52) of limiting part 50 is set greatlyr.Thus, in wafer holder 30, around the wafer loading surface 411 of loading part 40, form the wall being formed by the inwall of limiting part 50.
Therefore, in wafer holder 30, loaded wafer W on the wafer loading surface 411 of loading part 40 time, the inwall that the periphery of this wafer W is limited parts 50 surrounds, wafer W is restricted with respect to the movement of wafer holder 30 movement of horizontal direction (more particularly, to).
Fig. 8 is the figure of an example of the formation of the wafer loading surface 411 for loading part 40 is described.Moreover the cross section of the loading part 40 shown in Fig. 8, is corresponding with the VIIC-VIIC cross section of Fig. 3 (a), but here, in order to contribute to the understanding to invention, concavo-convex in wafer loading surface 411 depicted large.
In the present embodiment, while observation from top, be the wafer loading surface 411 of circular shape, there is the cross sectional shape of the chevron (convex) increasing gradually towards central authorities from periphery in its cross section.Therefore, the isocontour roughly concentric circles that is distributed as in wafer loading surface 411.Moreover in the present note, in wafer loading surface 411, the position that absolute altitude is the highest is called top 4111, the height at the top 4111 taking the periphery of wafer loading surface 411 during as benchmark is called wafer loading surface height h.
, in the present embodiment, use the wafer W of 4 inches (100mm) here, wafer holder 30 is also constituted as the wafer W that can load 4 inches.Therefore, the diameter of the wafer loading surface 411 in loading part 40 (except the correspondence position of directional plane) is 100mm.And, in the present embodiment, be that 100mm is relative with the diameter of wafer loading surface 411, wafer loading surface height h is set under room temperature (25 DEG C) becomes 17.5 ± 7.5 μ m.In addition, the top 4111 in wafer loading surface 411, is positioned at the scope of radius 20mm from wafer loading surface 411 center (Yuan center).
And in the present embodiment, polishing (lap) processing based on grinding has been implemented on the surface (coating being formed by SiC) to the wafer loading surface 411 in loading part 40.Thus, the arithmetic average roughness Ra in wafer loading surface 411 is set to below 0.5 μ m, is more preferably set as 0.3 μ m ± 0.1 μ m(0.2 μ m～0.4 μ m).Moreover, on the surface (coating being formed by SiC) of the annular loading surface 412 of loading part 40, there is no to implement the polishing as wafer loading surface 411.Therefore, annular loading surface 412, than wafer loading surface 411, the value of arithmetic average roughness Ra is larger.
Here, the wafer holder 30 of present embodiment, consists of combination loading part 40 and limiting part 50 as mentioned above, and in the upper surface 41 of loading part 40, wafer loading surface 411 is positioned at topmost.Therefore, and loading part 40 and the integrated existing wafer holder forming of limiting part 50 are compared, the formation of the convex surface in wafer loading surface 411 and the grinding of established convex surface (polishing) become easily, and the precision of face also easily manifests.
The formation > of < laminated semiconductor wafer
Fig. 9 is the sectional view that represents to utilize an example of the laminated semiconductor wafer SW that above-mentioned MOCVD device 1 manufactures.Moreover the laminated semiconductor wafer SW shown in Fig. 9, becomes for the manufacture of output example as the parent material of the luminescence chip of blue light.
This laminated semiconductor wafer SW has: substrate 110, be formed on the intermediate layer 120 on substrate 110, the basalis 130 stacking gradually, N-shaped semiconductor layer 140, luminescent layer 150 and p-type semiconductor layer 160 on intermediate layer 120.
Here, N-shaped semiconductor layer 140 has the N-shaped contact layer 140a that is located at basalis 130 sides and the N-shaped coating 140b that is located at luminescent layer 150 sides.In addition, luminescent layer 150 has: barrier layer 150a and trap layer 150b are by alternately stacked and clipped the multi-quantum pit structure of a trap layer 150b by two barrier layer 150a.And p-type semiconductor layer 160 has the p-type coating 160a that is located at luminescent layer 150 sides and the p-type contact layer 160b that is located at the superiors.
Moreover, in the following description, substrate 110, intermediate layer 120 and basalis 130 are referred to as to laminated base plate 100, N-shaped semiconductor layer 140, luminescent layer 150 and p-type semiconductor layer 160 are referred to as to compound semiconductor layer 170.
(substrate 110)
Substrate 110 is made up of the material different from III iii-v nitride compound semiconductor, on substrate 110, and the epitaxial growth of III group-III nitride semiconductor crystal.As the material that forms substrate 110, can use such as sapphire, carborundum (SiC), silicon etc.
(intermediate layer 120)
As mentioned above, substrate 110 is made up of the material different from III iii-v nitride compound semiconductor.Therefore, preferably: before utilizing the MOCVD device 1 film forming compound semiconductor layer 170 shown in Fig. 1, on substrate 110, set in advance the intermediate layer 120 of performance pooling feature.Especially, consider from buffering function aspects, preferred interlayer 120 is mono-crystalline structures.On substrate 110 film forming have the intermediate layer 120 of mono-crystalline structures, the pooling feature in intermediate layer 120 plays a role effectively, and on intermediate layer 120, the basalis 130 of film forming and compound semiconductor layer 170 become and have good crystalline crystalline film.
Al is preferably contained in intermediate layer 120, particularly preferably contains the AlN as III group-III nitride.(basalis 130)
As the material for basalis 130, can use the III group-III nitride (GaN based compound semiconductor) that contains Ga, especially can preferably use AlGaN or GaN.The thickness of basalis 130 is more than 0.1 μ m, more than being preferably 0.5 μ m, more preferably more than 1 μ m.
(N-shaped semiconductor layer 140)
N-shaped semiconductor layer 140 is made up of N-shaped contact layer 140a and N-shaped coating 140b.
Here, as N-shaped contact layer 140a, use GaN based compound semiconductor same with basalis 130.In addition, the gallium nitride compound semiconductor that forms basalis 130 and N-shaped contact layer 140a, is preferably same composition, and the thickness of their total is set as to 0.1 μ m～20 μ m, be preferably set to 0.5 μ m～15 μ m, be more preferably set as the scope of 1 μ m～12 μ m.
On the other hand, N-shaped coating 140b can be formed by AlGaN, GaN, GaInN etc.In addition, also can adopt heterogeneous their the structure structure having engaged or stacked superlattice structure repeatedly.In the situation that adopting GaInN as N-shaped coating 140b, preferably make its band gap larger than the band gap of the GaInN of luminescent layer 150.The thickness of N-shaped coating 140b is preferably 5nm～500nm, more preferably in the scope of 5nm～100nm.
(luminescent layer 150)
Luminescent layer 150, to form by following sequential cascade: the barrier layer 150a that comprises gallium nitride compound semiconductor and the trap layer 150b that comprises the gallium nitride compound semiconductor that contains indium are alternately repeatedly stacked, and configure respectively barrier layer 150a in N-shaped semiconductor layer 140 sides and p-type semiconductor layer 160 sides.In the present embodiment, luminescent layer 150 becomes following formation: alternately lamination repeatedly of the trap layer 150b of the barrier layer 150a of 6 layers and 5 layers at the superiors and the orlop configuration barrier layer 150a of luminescent layer 150, configures trap layer 150b between each barrier layer 150a.
As barrier layer 150a, for example, can preferably use the large Al of band-gap energy compared with the trap layer 150b that comprises the gallium nitride compound semiconductor that contains indium cga 1-cn(0≤c≤0.3) etc. gallium nitride compound semiconductor.
In addition, in trap layer 150b, as the gallium nitride compound semiconductor that contains indium, for example, can use Ga 1-sin sn(0 < s < 0.4) etc. indium gallium nitride (being sometimes expressed as below " GaInN ").
As the thickness of luminescent layer 150 entirety, though be not particularly limited, be preferably the thickness of the degree that can obtain quantum effect, i.e. critical film thickness region.For example, the thickness of luminescent layer 150 is preferably the scope of 1nm～500nm, more preferably the thickness of 100nm left and right.In addition, as the thickness of trap layer 150b, though be not particularly limited, be preferably the thickness of the degree that can obtain quantum effect.
(p-type semiconductor layer 160)
P-type semiconductor layer 160 is made up of p-type coating 160a and p-type contact layer 160b.As p-type coating 160a, preferably enumerate Al dga 1-dn(0 < d≤0.4) layer.The thickness of p-type coating 160a is preferably 1nm～400nm, more preferably 5nm～100nm.
On the other hand, as p-type contact layer 160b, can enumerate and contain Al ega 1-en(0≤e < 0.5) gallium nitride system compound semiconductor layer that forms.The thickness of p-type contact layer 160b, though be not particularly limited, is preferably 10nm～500nm, more preferably 50nm～200nm.
Moreover, in the MOCVD of present embodiment device 1, implement following operation, that is: obtain the 1st stacked operation of laminated base plate 100 by stacked intermediate layer 120, basalis 130 on substrate 110; Obtain the 2nd stacked operation of laminated semiconductor wafer SW containing the compound semiconductor layer 170 of N-shaped semiconductor layer 140, luminescent layer 150 and p-type semiconductor layer 160 by the basalis 130 upper strata stacked packages at laminated base plate 100.Therefore, in the 1st stacked operation for example, substrate 110 becomes wafer W, and in addition, in the 2nd stacked operation for example, laminated base plate 100 becomes wafer W.
The manufacture method > of < laminated semiconductor wafer
Here, to using MOCVD device 1, the compound semiconductor layers 170 that dissolves on laminated base plate 100 upper stratas of the example as wafer W, the method for manufacturing thus laminated semiconductor wafer SW describes.
At first, laminated base plate 100 is arranged in the wafer holder 30 that combination loading part 40 and limiting part 50 form.Now, by making substrate 110 sides in laminated base plate 100 be loaded into the wafer loading surface 411 of the loading part 40 in wafer holder 30, and the basalis 130 in laminated base plate 100 is exposed to outside.In addition, accompany therewith, the side face (side) of laminated base plate 100 is relative with the internal face of the limiting part 50 in wafer holder 30, becomes the state having been embedded loosely with respect to wafer holder 30 laminated base plates 100.
Then, 6 wafer holders 30 that keep respectively laminated base plate 100 are placed on the support 20 of being located in MOCVD device 1.Be described more specifically, in MOCVD device 1, opening with respect to resettlement section 11 under the state of cap 12, by each self-sustaining 6 wafer holders 30 of laminated base plate 100 be configured in each recess (6 positions) of being located at support 20 in the mode upward of the basalis 130 in laminated base plate 100.Now, the face that is loaded 421 of the bottom surface 42 in the loading part 40 of each wafer holder 30, contacts with the bottom surface of each recess of being located at support 20.Then, close cap 12 with respect to resettlement section 11, carry out exhaust and make resettlement section 11 and cap 12 adherences (closely sealed), form thus reative cell.
Then, make support 20 along arrow A direction rotation by means of axle 21, and supply with nitrogen N by not shown through hole to each recess of being located at support 20 2, thus on the support 20 along arrow A direction rotation, make each wafer holder 30 and be maintained at laminated base plate 100 in each wafer holder 30 along arrow B direction rotation.In addition, start the supply of carrier gas via supply pipe 13.
And then, start the energising to heating part 60, be situated between, by support 20 and each wafer holder 30, the laminated base plate 100 remaining in each wafer holder 30 be heated to the design temperature (the 1st design temperature: be in this example 1090 DEG C) for epitaxial growth N-shaped contact layer 140a.And, be heated at laminated base plate 100 under the state of the 1st design temperature, start the supply of the unstrpped gas that N-shaped contact layer 140a uses via supply pipe 13.
So in the face side of the basalis 130 of laminated base plate 100, the unstrpped gas being supplied to from outside is because the heat of laminated base plate 100 reacts.Its result, on basalis 130, epitaxial growth goes out N-shaped contact layer 140a.
And one through predetermined time (obtaining the needed time of thickness as the N-shaped contact layer 140a of target), just stops the supply of the unstrpped gas of using via the N-shaped contact layer 140a of supply pipe 13.Thus, the stacked of N-shaped contact layer 140a completes.
Then, by changing as required the "on" position (current value) to heating part 60, be situated between and will remain on laminated base plate 100(in each wafer holder 30 here by support 20 and each wafer holder 30, comprise until the layer of N-shaped contact layer 140a, below identical) be heated to for making the epitaxially grown design temperature of N-shaped coating 140b (the 2nd design temperature: this example is 780 DEG C).And, be heated at laminated base plate 100 under the state of the 2nd design temperature, start the supply of the unstrpped gas that N-shaped coating 140b uses via supply pipe 13.
So, the face side of the N-shaped contact layer 140a in laminated base plate 100, the unstrpped gas being supplied to from outside is because the heat of laminated base plate 100 reacts.Its result, on N-shaped contact layer 140a, epitaxial growth goes out N-shaped coating 140b.
And one through predetermined time (obtaining the needed time of thickness as the N-shaped coating 140b of target), just stops the supply of the unstrpped gas of using via the N-shaped coating 140b of supply pipe 13.Thus, the stacked of N-shaped coating 140b completes.
Then, by changing as required to the "on" position of heating part 60, be situated between and will remain on laminated base plate 100(in each wafer holder 30 here by support 20 and each wafer holder 30, comprise until the layer of N-shaped coating 140b, below identical) be heated to for making the epitaxially grown design temperature of barrier layer 150a (the 3rd design temperature: be in this example 800 DEG C).And, be heated at laminated base plate 100 under the state of the 3rd design temperature, start the supply of the unstrpped gas that barrier layer 150a uses via supply pipe 13.
So, the face side of the N-shaped coating 140b in laminated base plate 100, the unstrpped gas being supplied to from outside is because the heat of laminated base plate 100 reacts.Its result, on N-shaped coating 140b, epitaxial growth goes out initial barrier layer 150a.
And one through predetermined time (obtaining the needed time of thickness as the barrier layer 150a of target), just stops the supply of the unstrpped gas of using via the barrier layer 150a of supply pipe 13.Thus, initial the stacked of barrier layer 150a completes.
And then then, by changing as required to the "on" position of heating part 60, be situated between and will remain on laminated base plate 100(in each wafer holder 30 here by support 20 and each wafer holder 30, comprise until the layer of initial barrier layer 150a, below identical) be heated to for making the epitaxially grown design temperature of trap layer 150b (the 4th design temperature: be in this example 800 DEG C).And, be heated at laminated base plate 100 under the state of the 4th design temperature, start the supply of the unstrpped gas that trap layer 150b use via supply pipe 13.
So the face side of the initial barrier layer 150a in laminated base plate 100, supplies with the unstrpped gas of coming because the heat of laminated base plate 100 reacts from outside.Its result, on initial barrier layer 150a, epitaxial growth goes out initial trap layer 150b.
And one through predetermined time (obtaining the needed time of thickness as the trap layer 150b of target), just stops the supply of the unstrpped gas of using via the trap layer 150b of supply pipe 13.Thus, stacked the completing of initial trap layer 150b.
After, the supply of the unstrpped gas of alternately repeatedly carrying out the supply of the unstrpped gas of using to heating and the barrier layer 150a of the 3rd design temperature and use to heating and the trap layer 150b of the 4th design temperature, the luminescent layer 150 that has obtained thus barrier layer 150a and trap layer 150b alternately laminated.Moreover the superiors in luminescent layer 150 are that last barrier layer 150a(is the barrier layer 150a of the 6th layer in this example).
Then, by changing as required to the "on" position of heating part 60, be situated between and will remain on laminated base plate 100(in each wafer holder 30 here by support 20 and each wafer holder 30, comprise until the layer of last barrier layer 150a, below identical) be heated to for making the epitaxially grown design temperature of p-type coating 160a (the 5th design temperature: be in this example 1090 DEG C).And, be heated at laminated base plate 100 under the state of the 5th design temperature, start the supply of the unstrpped gas that p-type coating 160a uses via supply pipe 13.
So the face side of the last barrier layer 150a in laminated base plate 100, supplies with the unstrpped gas of coming because the heat of laminated base plate 100 reacts from outside.Its result, on last barrier layer 150a, epitaxial growth goes out p-type coating 160a.
And one through predetermined time (obtaining the needed time of thickness as the p-type coating 160a of target), just stops the supply of the unstrpped gas of using via the p-type coating 160a of supply pipe 13.Thus, the stacked of p-type coating 160a completes.
Then, by changing as required to the "on" position of heating part 60, be situated between and will remain on laminated base plate 100(in each wafer holder 30 here by support 20 and each wafer holder 30, comprise until the layer of p-type coating 160a, below identical) be heated to for making the epitaxially grown design temperature of p-type contact layer 160b (the 6th design temperature: be in this example 1090 DEG C).And, be heated at laminated base plate 100 under the state of the 6th design temperature, start the supply of the unstrpped gas that p-type contact layer 160b uses via supply pipe 13.
So the face side of the p-type coating 160a in laminated base plate 100, supplies with the unstrpped gas of coming because the heat of laminated base plate 100 reacts from outside.Its result, on p-type coating 160a, epitaxial growth goes out p-type contact layer 160b.
And one through predetermined time (obtaining the needed time of thickness as the p-type contact layer 160b of target), just stops the supply of the unstrpped gas of using via the p-type contact layer 160b of supply pipe 13.Thus, the stacked of p-type contact layer 160b completes.
By above process, can obtain dissolving on laminated base plate 100 upper stratas that compound semiconductor layers 170 is that form, the laminated semiconductor wafer SW shown in Fig. 9.
The laminated semiconductor wafer SW that obtains like this, divided after the formation of having carried out electrode etc. thereafter, become multiple luminescence chips.Now, preferred: in the multiple luminescence chips that obtained by 1 piece of laminated semiconductor wafer SW, to reduce the deviation of the emission wavelength between luminescence chip as far as possible.
Here, the emission wavelength of luminescence chip, is made up of GaInN the trap layer 150b(that forms luminescent layer 150) in Ga and the ratio of In determine.Therefore,, in the manufacture of laminated semiconductor wafer SW that utilizes MOCVD device 1, composition while suppressing to make trap layer 150b epitaxial growth, GaInN is inhomogeneous very important.
And the composition of the GaInN in trap layer 150b is inhomogeneous, be to result to make luminescent layer 150(more specifically, trap layer 150b) non-uniform temperature (temperature deviation) when epitaxial growth, laminated base plate 100 and producing.Be described more specifically, make trap layer 150b growth on laminated base plate 100 time, in the relatively high region of temperature, low region relative to temperature compared, and in GaInN, the shared ratio of In easily reduces.Moreover, in GaInN, the shared ratio of In has reduced (ratio of Ga increased), the emission wavelength of luminescent layer 150 shortens, and in GaInN, the shared ratio of In has increased (ratio of Ga reduced), the emission wavelength of luminescent layer 150 is elongated.
Temperature distribution homogenization when making stacked luminescent layer 150, in wafer W, preferred: on the uniform basis of temperature of the wafer loading surface 411 in the loading part 40 that makes wafer holder 30, make the back side (face relative with wafer loading surface 411) and the contact condition of wafer loading surface 411 of wafer W even, make the heat conduction from wafer holder 30 to wafer W even.In order to make the equalizing temperature of the wafer loading surface 411 in loading part 40, for example, at the additional spot-facing of the bottom surface of loading part 40 42 sides (forming outside opposite face 422 and/or inner side opposite face 423), and make the thermal emissivity rate homogenizing of wafer loading surface 411, suppress to become important from the heat release of wafer loading surface 411 is inhomogeneous.For the temperature that makes wafer loading surface 411 evenly and make heat conduction from from wafer loading surface 411 to wafer W evenly, make the surface roughness (for example arithmetic average roughness Ra) of wafer loading surface 411 even, and at the temperature that luminescent layer 150 is grown (being in this example 800 DEG C), make the shape of the wafer loading surface 411 in the back side and the loading part 40 of wafer W become important with μ m level coupling.
Here, being laminated with until in the wafer W of the layer of N-shaped semiconductor layer 140 when stacked luminescent layer 150, if the shape of wafer W can be controlled to the state (close to smooth state) that almost there is no warpage, become and easily obtain the good film (luminescent layer 150) of quality that defect is few.But, owing to keeping the wafer holder 30 of wafer W, mainly heated from rear side (bottom surface 42 sides of loading part 40), thus with the upper surface 41(of loading part 40 including wafer loading surface 411) compared with, the temperature of bottom surface 42 easily uprises.Therefore,, under the growth temperature of luminescent layer 150, due to the thermal expansion difference of the table back of the body (upper surface 41 sides and bottom surface 42 sides) of loading part 40, loading part 40 becomes compared with the state of room temperature to the protruding state of bottom surface 42 sides.
By in loading part 40 and the integrated existing wafer holder forming of limiting part 50, observe from ring, the face of loaded with wafers is positioned at inboard, so be difficult to by grinding etc., its arithmetic average roughness Ra be managed, the value of arithmetic average roughness Ra can exceed 1 μ m, and its deviation is also large.In addition, in existing wafer holder, because reusing, easily there is deviation in the surface roughness of the face of loaded with wafers, accompany with it, thermal emissivity rate, contact heat resistance become inhomogeneous, so become at stacked luminescent layer 150(trap layer 150b) in produce the inhomogeneous reason of composition.
And, in existing wafer holder, though attempted with ring integrated state under, arrange surface configuration, the surface roughness of the face of loaded with wafers, but cannot use larger grinding stone etc. at the position close to ring in order to avoid ring, therefore, spread all over loaded with wafers face whole ground accurately control surface shape (convex) and surface roughness be very difficult, cause using and surface configuration as target and the larger wafer holder of surface roughness deviation.
Therefore, in the present embodiment, set the shape of the loading part 40 that forms wafer holder 30, make at room temperature, upper surface 41 sides (wafer loading surface 411 sides) become protruding.By setting in this wise the shape of loading part 40, near the growth temperature of luminescent layer 150, the surface configuration of wafer loading surface 411 becomes the state of general planar, can be close near the shape of the laminated base plate 100 growth temperature at luminescent layer 150.Its result, near the growth temperature of luminescent layer 150, in the roughly whole region of laminated base plate 100, can make the distance of the wafer loading surface 411 in the back side and the loading part 40 of laminated base plate 100 be close to below certain size.Therefore, the non-uniform temperature of the laminated base plate 100 when compound semiconductor layer 170 epitaxial growth that can suppress to make to contain trap layer 150b, the composition that can suppress the GaInN in trap layer 150b is inhomogeneous.As its result, can suppress to cut apart laminated semiconductor wafer SW and the deviation of emission wavelength in multiple luminescence chips of obtaining.
In addition, in the present embodiment, the arithmetic average roughness Ra that makes the wafer loading surface 411 in loading part 40 is below 0.5 μ m.Thus, that can suppress to discharge from wafer loading surface 411 is hot inhomogeneous, and inhomogeneous in the hot face of supplying with to laminated base plate 100, the composition that can further suppress the GaInN in trap layer 150b is inhomogeneous.
Here, in the present embodiment, forming in the loading part 40 of wafer holder 30, in bottom surface, 42 sides form outside opposite face 422 and inner side opposite faces 423, make thus the thickness of loading part 40 of outer circumferential side and inner circumferential side different from other position.And, the thickness of loading part 40 is arranged to the non-uniform temperature that distribution also contributes to the laminated base plate 100 that suppresses above-mentioned.
And, in the present embodiment, keep the wafer holder 30 as the laminated base plate 100 of wafer W, by loading the loading part 40 of laminated base plate 100 and forming by the limiting part 50 that the surrounding that encirclement is loaded into the laminated base plate 100 of loading part 40 limits the movement of laminated base plate 100.On laminated base plate 100, make in the epitaxially grown situation of compound semiconductor layer 170 also heat tracing and be out of shape (thermal expansion) of wafer holder 30 itself.Here, in the existing wafer holder that the loading part of loading laminated base plate 100 and the wall integrally that surrounds the ring-type around the laminated base plate 100 loading are formed, be accompanied by heating, when loading part distortion, sometimes due to the integrated wall of loading part portion, its distortion is hindered.In this situation, even if the loading surface of the wafer W in loading part is formed as the convex of central uplift compared with periphery under room temperature for example, in the time of heating, because of integrated wall portion, its shape also can deform, and existence cannot be deformed into the possibility of smooth shape.On the other hand, in the present embodiment, by forming wafer holder 30 by loading part 40 and limiting part 50, thereby be for example accompanied by heating loading part 40 be out of shape in the situation that, limiting part 50 is difficult to hinder its distortion, so in the time of heating, the wafer loading surface 411 in loading part 40 is easily from convex form to smooth transfer of shapes.Therefore, the non-uniform temperature of the laminated base plate 100 when compound semiconductor layer 170 epitaxial growth that also can suppress thus to make to comprise trap layer 150b, the composition that can suppress the GaInN in trap layer 150b is inhomogeneous.
In addition, the wafer holder 30 of present embodiment, consists of combination loading part 40 and limiting part 50, so after the manufacture of example laminated semiconductor wafer described above SW, can separate with limiting part 50 loading part 40, and to cleaning separately.In addition, after the manufacture of example laminated semiconductor wafer described above SW, can separate with limiting part 50 loading part 40, loading part 40 is cleaned and recycled, limiting part 50 is replaced by new limiting part 50.
And, for the loading part 40 after cleaning and after separating, not only can clean, can also carry out the reprocessing of wafer loading surface 411.Now, at the upper surface 41 of loading part 40, as mentioned above, wafer loading surface 411 is positioned at topmost, so grind again (polishing) of the convex surface that has formed and formed of the convex surface in wafer loading surface 411 is easier to.
Moreover in the present embodiment, the loading part 40 and the limiting part 50 that form wafer holder 30 adopt different materials to form, but are not limited to this, also can adopt identical material to form.
In addition, in the present embodiment, to be illustrated as example comprising the situation that makes the epitaxial growth of III nitride semiconductor layer obtain thus laminated semiconductor wafer SW on sapphire substrate 110, but be not limited to this.For example, can be also the situation of the compound semiconductor of stacked III-V compound semiconductor, II-VI compound semiconductor, IV-IV compound semiconductor etc. on substrate 110.
And, in the present embodiment, be illustrated as different types of situation as example taking substrate 110 and the compound semiconductor being stacked on substrate 110, but be not limited to this, for identical type in the situation that, also can apply.
Embodiment
Then, embodiments of the invention are described, but the invention is not restricted to embodiment.
The inventor utilizes the MOCVD device 1 shown in Fig. 1 etc., on laminated base plate 100, carry out the stacked of compound semiconductor layer 170, the relation of the photoluminescence property (PL Wavelength distribution) in the formation to the wafer holder 30 now using and the laminated semiconductor wafer SW obtaining is studied.
Figure 10 represents the 3D shape of wafer loading surface 411 during embodiment 1 and comparative example 1～comparative example 3 are separately, wafer holder 30 and the figure of the relation of the PL Wavelength distribution of the laminated semiconductor wafer SW that obtains.
In embodiment 1, use the wafer holder 30(having illustrated, loading part 40 and limiting part 50 are combined with reference to Fig. 3～Fig. 8 in execution mode here).In addition, in comparative example 1 and comparative example 2, used by loading part and limiting unit integrated, existing wafer holder 30.
In addition, as shown in figure 10, in embodiment 1, make the convex form that is shaped as central uplift compared with periphery of the wafer loading surface 411 under room temperature.Now, making the wafer loading surface height h of wafer loading surface 411 is 17.5 μ m, and the arithmetic average roughness Ra that makes wafer loading surface 411 is 0.3 μ m.
On the other hand, as shown in figure 10, in comparative example 1, make wafer loading surface 411 under room temperature be shaped as neither flat condition neither convex special-shaped shape.In comparative example 1, as used in figure as shown in straight line, there is the ridge part towards below, right side from left side central authorities here.
On the other hand, as shown in figure 10, in comparative example 2, make the shape of the wafer loading surface 411 under room temperature and comparative example 1 similarly for neither flat condition neither convex special-shaped shape.But, in comparative example 2, as used in figure as shown in straight line, there is the ridge part of below, left side above right side from figure.
On the other hand, as shown in figure 10, in comparative example 3, similarly to Example 1, make the convex form that is shaped as central uplift compared with periphery of the wafer loading surface 411 under room temperature.But making the wafer loading surface height h of wafer loading surface 411 is 17.5 μ m, the arithmetic average roughness Ra that makes on the other hand wafer loading surface 411 is 0.6 μ m.
Then, describe for the Wavelength distribution obtaining.
In embodiment 1, spread all over the roughly whole region of laminated semiconductor wafer SW, the deviation of PL wavelength diminishes.
On the other hand, in comparative example 1, in the center side of laminated semiconductor wafer SW, compared with peripheral side, partially in the elongated region of PL wavelength.
In addition, in comparative example 2, at the peripheral side of laminated semiconductor wafer SW, compared with other region, partially in two elongated regions of PL wavelength.
And, in comparative example 3, in the center side of laminated semiconductor wafer SW, compared with peripheral side, also partially in the elongated region of PL wavelength.
Known like this, by forming wafer holder 30 by loading part 40 and limiting part 50, and make loading part 40 wafer loading surface 411 be shaped as the convex towards central uplift from periphery, and when microscopic observation wafer loading surface 411, be smooth face (arithmetic average roughness Ra is that 0.5 μ m is following), can obtain the laminated semiconductor wafer SW that the deviation of PL wavelength and then the deviation of emission wavelength are few.
Description of reference numerals
1 ... MOCVD device, 10 ... reaction vessel, 20 ... support, 30 ... wafer holder; 40 ... loading part, 50 ... limiting part, 60 ... heating part, 70 ... guard block; 80 ... exhaust component, 90 ... monitoring arrangement, 100 ... laminated base plate; 110 ... substrate, 120 ... intermediate layer, 130 ... basalis; 140 ... N-shaped semiconductor layer, 150 ... luminescent layer, 160 ... p-type semiconductor layer; 170 ... compound semiconductor layer, W ... wafer, SW ... laminated semiconductor wafer.

Claims (7)

1. a manufacturing installation for compound semiconductor, is to use chemical vapor-phase growing method on wafer, to form the manufacturing installation of the compound semiconductor of compound semiconductor layer, it is characterized in that possessing:
Accommodate the reaction vessel of described wafer in inside;
Be configured in described reaction vessel, with the wafer holder that keeps this wafer facing to the mode of top that is formed of the described compound semiconductor layer in described wafer;
In from outside to described reaction vessel, supply with the supply unit of the unstrpped gas of the raw material that becomes described compound semiconductor layer; With
The heating part that described wafer holder is heated,
Described wafer holder comprises:
Load the loading part of described wafer; With
Be loaded on described loading part, and limit the limiting part of the movement of this wafer by the side face that encirclement is loaded on the described wafer of this loading part,
Described loading part possesses: loads the 1st loading surface of described wafer and is located at the surrounding of the 1st loading surface and loads the 2nd loading surface of described limiting part,
Described the 1st loading surface, forms highlightedly than described the 2nd loading surface, and has the face shape of the convex of center side protuberance compared with peripheral side, and the arithmetic average roughness Ra of the 1st loading surface is below 0.5 μ m.
2. the manufacturing installation of compound semiconductor according to claim 1, is characterized in that, also possesses support, and described support can be configured in described reaction vessel rotatably, and can support rotatably described wafer holder,
Described supply unit is supplied with described unstrpped gas from top or the side of described support.
3. the manufacturing installation of compound semiconductor according to claim 1 and 2, is characterized in that, described heating part is heated to 700 DEG C above below 1200 DEG C by described wafer.
4. a wafer holder, is to use chemical vapor-phase growing method to use form the manufacturing installation of compound semiconductor of compound semiconductor layer on wafer in, keeping the wafer holder of this wafer, it is characterized in that, comprising:
Load the loading part of described wafer;
Be loaded on described loading part, and limit the limiting part of the movement of this wafer by the side face that encirclement is loaded on the described wafer of this loading part,
Described loading part possesses: loads the 1st loading surface of described wafer and is located at the surrounding of this wafer loading surface and loads the 2nd loading surface of described limiting part,
Described the 1st loading surface, forms highlightedly than described the 2nd loading surface, and has the face shape of the convex of center side protuberance compared with peripheral side, and the arithmetic average roughness Ra of the 1st loading surface is below 0.5 μ m.
5. wafer holder according to claim 4, is characterized in that, described chemical vapor-phase growing method is organic metal vapor growth method, and described compound semiconductor layer is III nitride semiconductor layer.
6. according to the wafer holder described in claim 4 or 5, it is characterized in that, described wafer is made up of the sheet material that has been pre-formed compound semiconductor layer on substrate.
7. according to the wafer holder described in any one of claim 4～6, it is characterized in that, described loading part is form on the surface of the base material being made up of carbon the coating being made up of SiC and form, and described limiting part is made up of quartz.
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