CN103823704B - The analogy method and simulator of flash memory - Google Patents
The analogy method and simulator of flash memory Download PDFInfo
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- CN103823704B CN103823704B CN201210466885.5A CN201210466885A CN103823704B CN 103823704 B CN103823704 B CN 103823704B CN 201210466885 A CN201210466885 A CN 201210466885A CN 103823704 B CN103823704 B CN 103823704B
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Abstract
The present invention provides the analogy method and simulator of a kind of flash memory.This simulator is electrically connected to a Memory Controller.This analogy method includes：Set a preset reaction condition；Multiple instruction table is provided, each of which instruction catalogue is corresponding to a type of memory；Receive the first instruction from Memory Controller；The second instruction in above-mentioned instruction catalogue is recognized according to the first instruction；Judge whether the second instruction meets preset reaction condition；According to preset reaction condition, the first signal of the instruction of correspondence second is obtained；And the first signal is transmitted to Memory Controller.Thereby, the use of simulator can be flexible.
Description
Technical field
The invention relates to a kind of analogy method of flash memory and simulator.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage
The demand of media also rapidly increases.Because reproducible nonvolatile memorizer module (for example, flash memory) has data non-volatile
Property, power saving, small volume, and without characteristics such as mechanical structures, so mounted in above-mentioned illustrated various portable in being especially suitable for
In multimedia device.
In general, a flash memory can be electrically connected to a Memory Controller, and thus Memory Controller is assigned
Instruction.However, in some applications, Memory Controller can be electrically connected to the flash memory of different memory type, and difference is deposited
The flash memory of reservoir type may have different object properties or built-in function.When the operation hair between Memory Controller and flash memory
During raw mistake, it is not easy to be the discovery that because the operation of Memory Controller makes a mistake or the operation of flash memory makes a mistake.Cause
How this, produce a simulator to simulate flash memory so that this simulator can be controlled and can support different storages
Device type, is this art personnel subject under discussion of concern.
The content of the invention
The analogy method and simulator of a kind of flash memory are provided in embodiments of the invention, can support simulator different
Type of memory.
One embodiment of the invention provides a kind of analogy method of flash memory.The method is used for simulator, and this simulator is used to
It is electrically connected to a Memory Controller.This analogy method includes：Set a preset reaction condition；Multiple instruction table is provided, its
In each instruction catalogue be correspondence to a type of memory；Receive the first instruction from Memory Controller；According to first
The second instruction in the above-mentioned instruction catalogue of instruction identification；Judge whether the second instruction meets preset reaction condition；According to preset reaction
Condition, obtains the first signal of the instruction of correspondence second；And the first signal is transmitted to Memory Controller.
In one embodiment, the second above-mentioned instruction is write instruction, and write instruction is to indicate the first data of write-in
To first memory address.This analogy method also includes：By a caching of first data storage into simulator；Pass through simulation
The non-flash interface transmission interrupt signal of device, write instruction and first memory address to a data processing unit, its
Middle data processing unit is used to produce the first above-mentioned signal according to preset reaction condition；And passed through by data processing unit non-
Flash interface reads the first data and by the first data storage into data processing unit from caching.
In one embodiment, the second above-mentioned instruction reads instruction for one, and it is to indicate that reading second deposits to read instruction
Memory address.This analogy method also includes：Interrupt signal is transmitted by the non-flash interface of simulator, reads to instruct and is deposited with second
Memory location to data processing unit, wherein data processing unit is used to produce the first signal according to preset reaction condition；And
The second data corresponding to second memory address are write by delaying to simulator by non-flash interface by data processing unit
In depositing.
In one embodiment, above-mentioned analogy method also includes：There is provided Memory Controller described in type of memory its
One of identification information.
In one embodiment, above-mentioned instruction catalogue includes the first instruction catalogue, and the first instruction catalogue includes multiple three instructions.Its
It is middle according to first instruction recognize instruction catalogue in second instruction the step of include：Is obtained from an array according to an index
One instruction；Judge whether the first instruction meets one of the 3rd instruction；If first instruction meet the 3rd instruction wherein it
One, more New Set；And if the first instruction does not meet one of the 3rd instruction, maintains index constant.Wherein first instruction
The 3rd instruction met is the second instruction.
In one embodiment, above-mentioned analogy method also includes：If the first instruction meets one of the 3rd instruction, production
A raw reset signal.Wherein reset signal indicates to start to recognize the 4th instruction in array, and the array order of the 4th instruction is
After the array order of the first instruction.
In one embodiment, above-mentioned analogy method also includes：If the first instruction meets one of the 3rd instruction, pass
A busy signal is sent to Memory Controller.
In one embodiment, above-mentioned analogy method also includes：If the first instruction meets one of the 3rd instruction, pass
An interrupt signal is sent to data processing unit to notify the second instruction.
For another angle, one embodiment of the invention provides a kind of simulator, to simulate flash memory.This simulator
Including：Flash interface, detector, processor and non-flash interface.Flash interface is to be electrically connected to Memory Controller,
And receive the first instruction from Memory Controller.Detector is electrically connected to flash interface, to provide multiple fingers
Make table.Each of which instruction catalogue is that correspondence a to type of memory, and detector is used to recognize these according to the first instruction
The second instruction in instruction catalogue.Processor is electrically connected to detector.Non-flash interface is electrically connected to processor, is used to
It is electrically connected to a data processing unit.Data processing unit judges the second instruction to set a preset reaction condition
Whether preset reaction condition is met.Processor is used to the first signal that the instruction of correspondence second is obtained according to preset reaction condition, and
And the first signal is transmitted to Memory Controller.
In one embodiment, the second above-mentioned instruction is write instruction, and this write instruction is to indicate that write-in first is counted
According to first memory address.In addition, simulator also includes a caching.Processor also to by the first data storage to cache,
And interrupt signal, write instruction and first memory address are transmitted to data processing unit by non-flash interface.At data
Unit is managed to be used to produce the first signal according to preset reaction condition.Also, data processing unit can be read by non-flash interface
The first data in caching, and by the first data storage into data processing unit.
In one embodiment, the second above-mentioned instruction is reads instruction, and it is to indicate that reading second deposits that this, which reads instruction,
Memory address.Processor can be transmitted interrupt signal by non-flash interface, be read at instruction and second memory position to data
Manage unit.Data processing unit is used to produce the first signal according to preset reaction condition, and data processing unit can be by non-
Flash interface writes the second data corresponding to second memory address into caching.
In one embodiment, above-mentioned processor also to provide type of memory described in Memory Controller wherein it
One identification information.
In one embodiment, above-mentioned instruction catalogue includes the first instruction catalogue, and the first instruction catalogue includes multiple three instructions.
Above-mentioned detector includes subelement, and this subelement includes target generator, multiplexer, instruction analysis device with being compared
Device.Target generator is to produce an index.Multiplexer is electrically connected to target generator, to according to index from
First is obtained in an array to instruct.Instruction analysis device is electrically connected to multiplexer, to analyze the first instruction to produce
Analysis result.Comparator, is electrically connected to instruction analysis device and target generator, to judge the first finger according to this analysis result
Whether order meets one of the 3rd instruction.If the first instruction meets one of the 3rd instruction, target generator is used to
More New Set.The 3rd instruction that wherein first instruction meets is the second instruction.If the first instruction does not meet the 3rd instruction wherein
One of, target generator is to maintain index constant.
In one embodiment, above-mentioned subelement also includes a reset signal maker.If the first instruction meets the 3rd finger
One of order, reset signal maker is to produce reset signal.This reset signal indicates to start to recognize the in array
Four instructions, and the array order of the 4th instruction is after the array order of the first instruction.
In one embodiment, above-mentioned subelement also includes a busy signal maker.If the first instruction meets the 3rd finger
One of order, busy signal maker is to transmit a busy signal to Memory Controller.
In one embodiment, above-mentioned subelement also includes an interrupt signal maker.If the first instruction meets the 3rd finger
One of order, interrupt signal maker is to transmit interrupt signal to data processing unit to notify the second instruction.
Based on above-mentioned, analogy method and simulator that the embodiment of the present invention is provided, different memory classes can be supported
Type.Also, the instruction catalogue corresponding to each type of memory can be updated.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Fig. 1 is the schematic block diagram for showing memory storage apparatus；
Fig. 2 is the system schematic that an implementation exemplifies simulation flash memory；
Fig. 3 is the operation chart that an implementation exemplifies a subelement；
Fig. 4 is the flow chart for the analogy method that an implementation exemplifies flash memory.
Description of reference numerals
100：Memory storage apparatus；
101：Host computer system；
102：Connector；
104：Memory Controller
106：Type nonvolatile；
108 (0)~108 (A)：Entity deletes unit；
200：Simulator；
202：Flash interface；
210：Detector；
211~214：Subelement；
220：Processor；
230：Non-flash interface；
240：Caching；
250：Data processing unit；
310：Array；
311、312：Instruction；
320：Target generator；
330：Multiplexer；
340：Instruction analysis device；
350：Comparator；
360：Instruction catalogue；
370：Busy signal maker；
380：Reset signal maker；
390：Interrupt signal maker；
S402、S404、S406、S408、S410、S412、S414：The analogy method of type nonvolatile
Step.
Embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories
Device module and Memory Controller (also referred to as, controlling circuit).Being commonly stored device storage device is used together with host computer system, with
Host computer system is set to write data into memory storage apparatus or be read from memory storage apparatus data.
Fig. 1 is the schematic block diagram for showing memory storage apparatus.
Fig. 1 is refer to, it is non-that memory storage apparatus 100 includes connector 102, Memory Controller 104 and duplicative
Volatile 106.
Connector 102 is to be electrically connected to host computer system 101.Host computer system 101 can assign instruction and be deposited to memory
Storage device 100.In the present embodiment, connector 102 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced
Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connector 102
Can be meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard,
Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE)
1394 standards, high-speed peripheral part connection peripheral interconnecting interface (Peripheral Component
InterconnectExpress, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) mark
Standard, secure digital (Secure Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) connect
Mouth standard, the generation of ultrahigh speed two (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS)
Interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, down enter formula built-in multimedia storage card
(Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS)
Interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electronic integrated circuit equipment interface
(Integrated Device Electronics, IDE) standard or other suitable standards.
Memory Controller 104 is to perform multiple gates with hardware pattern or firmware pattern implementation or control to refer to
Order, and according to the instruction of host computer system 101 carried out in reproducible nonvolatile memorizer module 106 data write-in,
The operation such as reading and deletion.On the other hand, the data for being intended to write to reproducible nonvolatile memorizer module 106 can be by depositing
Memory controller 104 is converted to the receptible form of the institute of reproducible nonvolatile memorizer module 106.
Reproducible nonvolatile memorizer module 106 (also referred to as flash memory) is electrically connected to Memory Controller 104, and
And the data write to host system 101.It is single that there is reproducible nonvolatile memorizer module 106 entity to delete
First 108 (0)~108 (A).For example, entity delete unit 108 (0)~108 (A) can belong to same memory crystal grain (die) or
Person belongs to different memory crystal grains.Each entity deletes unit has a plurality of entity program units respectively, and belongs to
The entity program unit that same entity deletes unit can be written independently and simultaneously be deleted.For example, each entity
Unit is deleted to be made up of 128 entity program units.However, it is necessary to be appreciated that, the invention is not restricted to this, Mei Yishi
Body deletion unit is can be by 64 entity program units, 256 entity program units or other any entity program
Unit is constituted.
In more detail, the least unit that entity deletes unit to delete.That is, each entity, which deletes unit, contains minimum
The memory cell deleted in the lump of number.Entity program unit is the minimum unit of sequencing.That is, entity program unit is
Write the minimum unit of data.Each entity program unit generally includes data bit area and redundancy ratio special zone.Data bit
Area includes the data multiple entity access addresses to store user, and redundancy ratio special zone is used to the data (example of storage system
Such as, control information and error correcting code).In the present embodiment, it can be wrapped in the data bit area of each entity program unit
Size containing 4 entity access addresses, and an entity access address is 512 bit groups (byte, B).However, in other implementations
In example, 8,16 or the more or less entity access addresses of number can be also included in data bit area, the present invention is not limited
The size and number of entity access address processed.For example, entity deletes unit for physical blocks, and entity program unit is
Physical page or entity fan.
In the present embodiment, reproducible nonvolatile memorizer module 106 is multistage memory cell (MultiLevel
Cell, MLC) at least two bit data can be stored in the memory cell of NAND-type flash memory module, i.e., one.However, the invention is not restricted to
This, reproducible nonvolatile memorizer module 106 may also be single-order memory cell (Single Level Cell, SLC) NAND
Flash memory module, Complex Order memory cell (Trinary Level Cell, TLC) NAND-type flash memory module, other flash memory modules or its
He has the memory module of identical characteristic.
Fig. 2 is the system schematic that an implementation exemplifies simulation flash memory.
Fig. 2 is refer to, simulator 200 is electrically connected to Memory Controller 104 and data processing unit 250.Simulator
200 be the behavior for simulating reproducible nonvolatile memorizer module 106.Specifically, simulator can support difference
Type of memory.For example, single-order memory cell NAND-type flash memory module, multistage memory cell NAND-type flash memory module and Complex Order are remembered
Different type of memory can be belonged to by recalling born of the same parents' NAND-type flash memory module.Or, the duplicative manufactured by different manufacturers
Non-volatile memory module 106 can belong to different type of memory.It is worth noting that, different type of memory can be right
It should arrive different instruction catalogues, and may be incompatible between different instruction catalogue.For example, write defined in a certain manufacturer
Instruction likely differs from write instruction defined in another manufacturer.However, simulator 200 can provide multiple type of memory
Corresponding multiple instruction table, and these instruction catalogues can be updated.
Data processing unit 250 includes one or more processors and a memory cell, and the meeting of data processing unit 250
Set a preset reaction condition.If data processing unit 250 is received at an instruction for coming from simulator 200, data
Reason unit 250 can judge whether this instruction meets this preset reaction condition and produce one first according to this preset reaction condition
Signal.In addition, data processing unit 250 can send this first signal to simulator 200.For example, if preset reaction bar
Part is the response that a write-in failure is produced to n-th write instruction, and wherein n is positive integer, then when data processing unit 250 is from mould
Intend device 200 and have received a write instruction, and this write instruction is to write a pen data to an entity program unit.
And, then data processing unit 250 can judge whether this write instruction is to be received from simulator 200 according to this preset reaction condition
N-th instruction, wherein n be positive integer.If this write instruction is n-th instruction, data processing unit 250 can produce representative
The first information of failure is write, and sends the first information to simulator 200.However, data processing unit 250 can also be set
Fixed other preset reaction conditions, read error information can also be produced according to preset reaction condition, successful information is read or writes
Enter successful information, it is of the invention and not subject to the limits.It is worth noting that, in the present embodiment, may not in data processing unit 250
Go to perform the program really write, and directly reply write-in failure, or data processing unit 250 does not have entity program list
Member, the first information of above-mentioned representative write-in failure simulates.
Specifically, simulator 200 includes flash interface 202, detector 210, processor 220, non-flash interface 230
With caching 240.
Flash interface 202 is to be electrically connected to Memory Controller 104.For example, flash interface 202 can include one or
Multiple pin positions and at least one bus.Data are simultaneously placed in bus by these pin of the meeting enable position of Memory Controller 104, are thereby passed
One is sent to instruct to simulator 200.
Detector 210 is electrically connected to flash interface 202.Detector 210 is received from Memory Controller 104
Instruction (also referred to as first instruction), and one in the multiple instruction table provided according to this first instruction identification simulator 200
Individual second instruction.For example, including subelement 211~214 in detector 210.Each subelement 211~214 is to correspond to extremely
One instruction catalogue, and also include multiple instruction in each instruction catalogue.After detector 210 receives the first instruction, son is single
Member 211 can judge whether this first instruction meets one of corresponding multiple instruction.Identical, subelement 212~214
Also it can judge whether the first instruction meets one of corresponding multiple instruction.However, in other embodiments, detector
It may include the more or less subelements of number in 210, it is of the invention and not subject to the limits.
Processor 220 is the integrated operation for controlling simulator 200.For example, processor 220 is microprocessor.However,
In other embodiments, processor 220 can also be programmable controller, Application Specific Integrated Circuit (Application
Specific Integrated Circuits, ASIC) or programmable logic device (Programmable Logic
Device, PLD).
Non-flash interface 230 is electrically connected to processor 220, and is electrically connected to data processing unit 250.
In the present embodiment, non-flash interface 230 is compatible to USB standard.However, in other embodiments, non-flash interface 230 may also be
It is compatible to PATA standards, IEEE1394 standards, PCI Express standards, SATA standard, SD interface standard, UHS-I interface marks
Standard, UHS-II interface standards, MS interface standards, MMC interface standards, eMMC interface standards, UFS interface standards, CF interface standards,
IDE standards or other suitable wireless communication standards (for example, WiFi or bluetooth communication).
Caching 240 is electrically connected to detector 210, processor 220 and non-flash interface 230, to data storage or refers to
Order.Wherein, in the present embodiment, simulator 200 can be a chips, i.e., by flash interface 202, detector 210, processor
220th, non-flash interface 230 encapsulates (system with caching 240 with system single chip (System-on-a-chip, SoC) or system
In package, SiP) mode be encapsulated in a chips.
After simulator 200 is electrically connected to Memory Controller 104, processor 220 can by flash interface 202 with
Memory Controller 104 exchanges multiple information.For example, processor 220 can determine the memory being simulated of simulator 200
Type, and the information of identification code of this type of memory is transmitted to Memory Controller 104.Memory Controller 104 can root
Identification information judges that simulator 200 is the flash memory for belonging to SLC or MLC types accordingly.Or, Memory Controller 104 can also
Manufacturer's identification code of a flash memory is obtained according to this identification information.It is identified after information, Memory Controller 104 can be passed
The instruction for meeting the type of memory that simulator 200 is simulated is sent to simulator 200.
Memory Controller 104 can transmit one by the pin on flash interface 202 and bus and instruct to simulator
200.For example, one write-in pin of the meeting of Memory Controller 104 enable, and one instruction identification code of transmission in bus.Mould
Plan device 200 is detected can read instruction identification code from bus after write-in pin is enabled.Then, the meeting of Memory Controller 104
One storage address is transmitted with the first data to be write to simulator 200 by bus.Thereby, Memory Controller
One write instruction can be sent to simulator 200 by 104.In other words, this write instruction can include an instruction identification code word
Section, a storage address field and one data word section, difference store instruction identification code, storage address and the first data.
After simulator 200 receives an instruction, subelement 211~214 can recognize whether this instruction meets corresponding instruction catalogue.
Fig. 3 is the operation chart that an implementation exemplifies a subelement.
Fig. 3 is refer to, subelement 211 is corresponding to some type of memory, and instruction catalogue 360 can include corresponding to this
The multiple instruction of type of memory.Subelement 211 include target generator 320, multiplexer 330, instruction analysis device 340,
Comparator 350, busy signal maker 370, reset signal maker 380 and interrupt signal maker 390.Wherein multiplex
Device 330 is electrically connected to target generator 320, and instruction analysis device 340 is electrically connected to multiplexer 330, and comparator
350 are electrically connected to instruction analysis device 340 and target generator 320.
If subelement 211 receives an instruction from Memory Controller 104, this instruction can be stored in array 310 and worked as
In.For example, subelement 211 is first to receive instruction 311, then receive instruction 312.Wherein instruction 312 array order be
After the array order of instruction 311.In this embodiment, array 310 is stored among caching 240.However, in other implementations
In example, array 310 can also be stored among a memory of subelement 211, of the invention and not subject to the limits.
Target generator 320 can produce an index, and multiplexer 330 can be selected according to this index from array 310
One instructs and sends this instruction to instruction analysis device 340.It is assumed herein that multiplexer 330 have selected instruction 311.Instruction
Analyzer 340 understands analysis instruction 311 to produce an analysis result.For example, instruction analysis device 340 can be wrapped in decision instruction 311
Instruction identification code field, storage address field, and data field are included.Instruction analysis device 340 can pass this analysis result
Give comparator 350.Comparator 350 can be more according to included by whether this analysis result decision instruction 311 meets instruction catalogue 360
One of individual instruction (also referred to as the 3rd instruction).For example, the finger that each in the meeting decision instruction of comparator 350 table 360 is instructed
Make whether identification code is same as the instruction identification code of instruction 311.Comparator 350 can also be determined whether in instruction catalogue 360
Whether instruction has corresponding storage address field and data field.If the decision instruction 311 of comparator 350 meets instruction catalogue
One in 360 instruction (also referred to as the second instruction), then comparator 350 can drive target generator 320 with more New Set (for example,
1) index is added, and the index after updating is to point to the next instruction in array 310 (for example, instruction 312).If comparing
The decision instruction 311 of device 350 does not meet any one instruction in instruction catalogue 360, then target generator 320 can maintain index not
Become.
If in addition, the decision instruction 311 of comparator 350 meets the first instruction in instruction catalogue 360, busy signal maker
370th, reset signal maker 380 can produce corresponding signal with interrupt signal maker 390.If for example, instruction 311 meets finger
A write instruction in table 360 is made, then busy signal maker 370 can produce a busy signal and send memory control to
Device 104 processed, to represent that simulator 200 is handling an instruction, can not receive other signals.In addition, reset signal is given birth to
Growing up to be a useful person 380 can produce a reset signal, and this reset signal is to indicate to start to recognize the next instruction in array 310.
For example, reset signal can be used to change parameter or index in subelement 211.On the other hand, interrupt signal maker 390 can be produced
A raw interrupt signal, this interrupting information is to send data processing unit 250 to notify the second instruction identified.
Fig. 2 is refer to back, if the instruction that detector 210 is identified is write instruction, processor 220 can refer to this write-in
The first data storage to be write is made in caching 240.Processor 220 also can be by produced by interrupt signal maker 390
Interrupting information, this write instruction, this write instruction storage address to be write (also referred to as first memory address) are sent to
Data processing unit 250.Data processing unit 250 can judge whether write instruction meets preset reaction condition, and according to pre-
Survey condition produces first signal.Data processing unit 250 can send this first signal to processor 220.Also, data
Processing unit 250 can send one and read instruction to non-flash interface 230, thereby read the first data from caching 240.Data
Processing unit 250 can be by memory cell of this first data storage among data processing unit 250 (for example, a volatibility
Memory or hard disc).Next, detector 210 can be in enable flash interface 202 one gets out/busy (Ready/
Busy) pin.Memory Controller 104 detect be ready to/after busy pin is enabled, Memory Controller 104 can be after
It is continuous to assign another and instruct to simulator 200.
On the other hand, if the instruction that detector 210 is identified instructs to read, processor 220 can give birth to interrupt signal
Grow up to be a useful person the interrupting information produced by 390, this read instruction, this reads instruction storage address to be read and (is also referred to as second to deposit
Memory address) send data processing unit 250 to.Receive after this reading instruction, data processing unit 250 can judge that this reads
Whether instruction fetch meets preset reaction condition, and produces the first signal according to predicted condition.In addition, data processing unit 250
Also the second data corresponding to second memory address can be obtained.For example, data processing unit 250 can one of which storage
The data corresponding to each storage address are noted down in unit, data processing unit 250 can be according to second memory address
The second data are obtained from memory cell.Then, data processing unit 250 can assign a write instruction and give non-flash interface
230, thereby the second data are write to caching 240.Detector 210 can be ready in enable flash interface 202/busy connects
Pin.If Memory Controller 104 detect be ready to/busy pin is enabled, a reading that can be in enable flash interface 202
Pin, the thereby meeting of detector 210 sends the second data to Memory Controller 104 by flash interface 202.
In another embodiment, the step performed by data processing unit 250 is and the data as performed by processor 220
Processing unit 250 can be implemented as an external memory storage.Also, processor 220 understands be write write instruction first
Data storage is among this external memory storage.
Fig. 4 is the flow chart for the analogy method that an implementation exemplifies flash memory.
Fig. 4 is refer to, in step S402, a preset reaction condition is set.There is provided multiple instruction in step s 404
Table, each of which instruction catalogue is corresponding to a type of memory.In step S406, the from Memory Controller is received
One instruction.In step S408, the second instruction in above-mentioned instruction catalogue is recognized according to the first instruction.In step S410, judge
Whether preset reaction condition is met.In step S412, according to preset reaction condition, a signal of the instruction of correspondence second is obtained.
In step S414, this signal is transmitted to Memory Controller.
It is worth noting that, in this embodiment, step S402, S410 and S412 can by data processing unit 250 or
It is that processor 220 is performed, and each step can have other execution sequences (for example, step S402 can be executed in Fig. 4
After step S408), it is of the invention and not subject to the limits.However, each step it is stated that as above, just repeat no more herein in Fig. 4.
In summary, the embodiment of the present invention is provided analogy method and simulator, can support different memory classes
Type, and the instruction catalogue of these type of memory can be updated.In addition, the signal response to Memory Controller is according to preset
Produced by reaction condition.Therefore, the use of this simulator can be more flexible.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：It is still
Technical scheme described in foregoing embodiments can be modified, or which part or all technical characteristic are carried out
Equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technical side
The scope of case.
Claims (17)
1. a kind of analogy method of flash memory, for a simulator, it is characterised in that the simulator is electrically connected to a storage
Device controller, the analogy method includes：
Set a preset reaction condition；
Multiple instruction table is provided, those instruction catalogues of each of which are corresponding to a type of memory；
Receive one first instruction from the Memory Controller；
According to one second instruction in the first instruction identification instruction catalogue；
Judge whether second instruction meets the preset reaction condition；
According to the preset reaction condition, obtain to should the second instruction one first signal；And
First signal is transmitted to the Memory Controller.
2. analogy method according to claim 1, it is characterised in that second instruction is a write instruction, and this is write
It is to indicate one first data of write-in to a first memory address to enter instruction, and the analogy method also includes：
By a caching of first data storage into the simulator；
One interrupt signal, the write instruction and the first memory address are transmitted to one by a non-flash interface of the simulator
Data processing unit, the wherein data processing unit according to the preset reaction condition to produce first signal；And
First data are read and by first data from the caching by the non-flash interface by the data processing unit
Store into the data processing unit.
3. analogy method according to claim 1, it is characterised in that second instruction reads instruction, and the reading for one
Instruction fetch is to indicate to read a second memory address, and the analogy method also includes：
One interrupt signal, reading instruction and the second memory position to one are transmitted by a non-flash interface of the simulator
Data processing unit, the wherein data processing unit according to the preset reaction condition to produce first signal；And
It will be write by the data processing unit by the non-flash interface corresponding to one second data of the second memory address
Into a caching of the simulator.
4. analogy method according to claim 1, it is characterised in that also include：
One identification information of one of the Memory Controller those type of memory is provided, and deposited in the reception from this
In the step of first instruction of memory controller, first instruction is the instruction for belonging to one of them type of memory.
5. analogy method according to claim 1, it is characterised in that those instruction catalogues include one first instruction catalogue, and
First instruction catalogue includes multiple three instructions, wherein recognizing second instruction in those instruction catalogues according to first instruction
Step includes：
First instruction is obtained from an array according to an index；
Judge whether first instruction meets one of those the 3rd instructions；
If first instruction meets one of those the 3rd instructions, the index is updated, what wherein first instruction met should
3rd instruction is second instruction；And
If first instruction does not meet one of those the 3rd instructions, maintain the index constant.
6. analogy method according to claim 5, it is characterised in that also include：
If first instruction meets one of those the 3rd instructions, a reset signal is produced, the wherein reset signal is indicated
Start to recognize one the 4th instruction in the array, an array order of the wherein the 4th instruction is an array in first instruction
After order.
7. analogy method according to claim 5, it is characterised in that also include：
If first instruction meets one of those the 3rd instructions, one busy signal of transmission gives the Memory Controller.
8. analogy method according to claim 5, it is characterised in that also include：
If first instruction meets one of those the 3rd instructions, one interrupt signal of transmission is to a data processing unit with logical
Know second instruction.
9. a kind of simulator, to simulate a flash memory, it is characterised in that the simulator includes：
One flash interface, is electrically connected to a Memory Controller, and receive from the Memory Controller one the
One instruction；
One detector, is electrically connected to the flash interface, and to provide multiple instruction table, each of which instruction catalogue is corresponding to one
Type of memory, and the detector is to recognize one second instruction in those instruction catalogues according to first instruction；
One processor, is electrically connected to the detector；And
One non-flash interface, is electrically connected to the processor, is electrically connected to a data processing unit, wherein at the data
Reason unit judges whether second instruction meets the preset reaction condition to set a preset reaction condition,
Wherein the processor is used to according to the preset reaction condition, obtain to should the second instruction one first signal, and pass
First signal is given to the Memory Controller.
10. simulator according to claim 9, it is characterised in that second instruction is a write instruction, the write instruction
It is to indicate one first data of write-in to a first memory address, the simulator also includes：
One caching,
Wherein, the processor is also first data storage is transmitted in one to the caching, and by the non-flash interface
Break signal, the write instruction and the first memory address to the data processing unit,
Wherein, the data processing unit is to read first data in the caching by the non-flash interface, and should
First data storage is into the data processing unit.
11. simulator according to claim 9, it is characterised in that second instruction reads instruction, and the reading for one
Instruction is to indicate to read a second memory address, and the simulator also includes：
One caching,
Wherein, the processor transmits an interrupt signal, reading instruction and the second memory position by the non-flash interface
To the data processing unit, wherein the data processing unit by the non-flash interface by corresponding to the second memory address
One second data are write into the caching.
12. simulator according to claim 9, it is characterised in that the processor is also to provide the Memory Controller
One identification information of one of those type of memory.
13. simulator according to claim 9, it is characterised in that those instruction catalogues include one first instruction catalogue, and this first
Instruction catalogue includes multiple three instructions, and the detector includes a subelement, and the subelement includes：
One target generator, to produce an index；
One multiplexer, is electrically connected to the target generator, to obtain first finger from an array according to the index
Order；
One instruction analysis device, is electrically connected to the multiplexer, to analyze first instruction to produce an analysis result；With
And
One comparator, is electrically connected to the instruction analysis device and the target generator, to according to the analysis result judge this
Whether one instruction meets one of those the 3rd instructions,
If first instruction meets one of those the 3rd instructions, the target generator wherein should to update the index
The 3rd instruction that first instruction meets is second instruction,
If first instruction does not meet one of those the 3rd instructions, the target generator is to maintain the index constant.
14. simulator according to claim 13, it is characterised in that the subelement also includes a reset signal maker,
If this first instruction meet those the 3rd instruction one of, the reset signal maker to produce a reset signal, its
In the reset signal indicate start recognize the array in one the 4th instruction, and the 4th instruction an array order be at this
After an array order of first instruction.
15. simulator according to claim 13, it is characterised in that the subelement also includes a busy signal maker,
If first instruction meets one of those the 3rd instructions, the busy signal maker is to transmit a busy signal to this
Memory Controller.
16. simulator according to claim 13, it is characterised in that the subelement also includes an interrupt signal maker,
If first instruction meets one of those the 3rd instructions, the interrupt signal maker is to transmit an interrupt signal to this
Data processing unit with notify this second instruction.
17. simulator according to claim 9, it is characterised in that the flash interface, the detector, the processor, this is non-
Flash interface with a caching is encapsulated in the way of system single chip or system encapsulation.
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