CN1038075C - 非易失性半导体存储器 - Google Patents

非易失性半导体存储器 Download PDF

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Publication number
CN1038075C
CN1038075C CN95105048A CN95105048A CN1038075C CN 1038075 C CN1038075 C CN 1038075C CN 95105048 A CN95105048 A CN 95105048A CN 95105048 A CN95105048 A CN 95105048A CN 1038075 C CN1038075 C CN 1038075C
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CN
China
Prior art keywords
signal
mentioned
change
test pattern
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN95105048A
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English (en)
Chinese (zh)
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CN1120740A (zh
Inventor
山崎昭浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1120740A publication Critical patent/CN1120740A/zh
Application granted granted Critical
Publication of CN1038075C publication Critical patent/CN1038075C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders

Landscapes

  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
CN95105048A 1994-04-27 1995-04-27 非易失性半导体存储器 Expired - Fee Related CN1038075C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP089495/94 1994-04-27
JP8949594A JP3015661B2 (ja) 1994-04-27 1994-04-27 不揮発性半導体メモリ

Publications (2)

Publication Number Publication Date
CN1120740A CN1120740A (zh) 1996-04-17
CN1038075C true CN1038075C (zh) 1998-04-15

Family

ID=13972348

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95105048A Expired - Fee Related CN1038075C (zh) 1994-04-27 1995-04-27 非易失性半导体存储器

Country Status (7)

Country Link
US (1) US5579270A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0680050B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP3015661B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR0159447B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1038075C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69513434T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW270996B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399526C (zh) * 2002-11-22 2008-07-02 松下电器产业株式会社 半导体器件的布局检验方法
CN100407334C (zh) * 2002-07-16 2008-07-30 富士通株式会社 非易失性半导体存储器及其操作方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745430A (en) * 1996-12-30 1998-04-28 Siemens Aktiengesellschaft Circuit and method to externally adjust internal circuit timing
EP0994417A3 (de) * 1998-09-09 2004-06-02 Siemens Aktiengesellschaft Schaltungsanordnung und Verfahren zur Überprüfung von Daten
TW439029B (en) * 1998-11-27 2001-06-07 Acer Peripherals Inc Method for preventing flash memory data from being lost or miswritten
TW473728B (en) * 1999-07-22 2002-01-21 Koninkl Philips Electronics Nv A method for testing a memory array and a memory-based device so testable with a fault response signalizing mode for when finding predetermined correspondence between fault patterns signalizing one such fault pattern only in the form of a compressed resp
US7007131B2 (en) * 2000-12-27 2006-02-28 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
JP2003016800A (ja) * 2001-07-03 2003-01-17 Mitsubishi Electric Corp 半導体装置
JP4424952B2 (ja) * 2003-09-16 2010-03-03 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
DE102004034042A1 (de) * 2004-07-13 2006-02-09 Endress + Hauser Gmbh + Co. Kg Elektronisches Gerät mit einem nicht flüchtigen beschreibbaren Datenspeicher

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280446A (en) * 1990-09-20 1994-01-18 Bright Microelectronics, Inc. Flash eprom memory circuit having source side programming

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5233562A (en) * 1991-12-30 1993-08-03 Intel Corporation Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
JP2716906B2 (ja) * 1992-03-27 1998-02-18 株式会社東芝 不揮発性半導体記憶装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280446A (en) * 1990-09-20 1994-01-18 Bright Microelectronics, Inc. Flash eprom memory circuit having source side programming

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100407334C (zh) * 2002-07-16 2008-07-30 富士通株式会社 非易失性半导体存储器及其操作方法
CN100399526C (zh) * 2002-11-22 2008-07-02 松下电器产业株式会社 半导体器件的布局检验方法

Also Published As

Publication number Publication date
EP0680050B1 (en) 1999-11-24
EP0680050A1 (en) 1995-11-02
US5579270A (en) 1996-11-26
JP3015661B2 (ja) 2000-03-06
KR0159447B1 (ko) 1999-02-01
TW270996B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-02-21
JPH07296599A (ja) 1995-11-10
DE69513434T2 (de) 2000-05-04
CN1120740A (zh) 1996-04-17
DE69513434D1 (de) 1999-12-30
KR950034838A (ko) 1995-12-28

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 19980415

Termination date: 20130427