CN103794575A - Encapsulation structure and method - Google Patents

Encapsulation structure and method Download PDF

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Publication number
CN103794575A
CN103794575A CN 201410033771 CN201410033771A CN103794575A CN 103794575 A CN103794575 A CN 103794575A CN 201410033771 CN201410033771 CN 201410033771 CN 201410033771 A CN201410033771 A CN 201410033771A CN 103794575 A CN103794575 A CN 103794575A
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CN
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Prior art keywords
chip
cover sheet
substrate
method
package structure
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CN 201410033771
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Chinese (zh)
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王谦
程熙云
蔡坚
谭琳
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清华大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention discloses an encapsulation structure and method. The encapsulation method comprises the steps that a chip is attached to a substrate; a lead is connected between the substrate and the chip, and the lead is covered with a molding component; the chip is covered with a cover plate, and the cover plate is connected with the chip through heat-conducting glue. According to the encapsulation structure and method, the cover plate is connected to the chip through the heat-conducting glue, the chip is coated with the heat-conducting glue, a large amount of heat generated by the chip can be effectively transmitted to the outside through the cover plate with a high heat conductivity coefficient, and therefore the heat dissipation performance and the reliability of the chip are both remarkably improved.

Description

一种封装结构及封装方法 A package structure and method of packaging

技术领域 FIELD

[0001] 本发明涉及封装技术,具体地,涉及一种封装结构及封装方法。 [0001] The present invention relates to a packaging technology, particularly, relates to a package structure and a packaging method.

背景技术 Background technique

[0002] 传统的引线键合封装产品主要由芯片、基板(或引线框架)、引线和塑封料几部分构成。 [0002] The conventional wire bond packages major product, and a molding compound leads several parts by the chip, the substrate (or leadframe). 其中,塑封料是保护芯片和引线不受外界灰尘、潮气和机械冲击等的影响,保证电连接的可靠性。 Wherein the plastic material is lead and protect the chip from external dirt, moisture, mechanical shock, and the like, to ensure the reliability of electrical connection.

[0003] 然而,塑封料的导热系数较低,因而被完全包裹在塑封料中的芯片无法将工作所产生的大量热量有效地传递到外界。 [0003] However, low thermal conductivity of plastic materials, a large amount of heat and thus is completely wrapped in the plastic compound will not work chips generated efficiently transferred to the outside.

发明内容 SUMMARY

[0004] 本发明的目的是提供一种封装结构及封装方法,用于解决传统引线键合产品散热性能差的问题。 [0004] The object of the present invention is to provide a package structure and a packaging method for solving the conventional wire bonding differential thermal performance problems.

[0005] 为了实现上述目的,本发明提供一种封装结构,该结构包括:基板;芯片,贴装在所述基板上;引线,连接在所述基板与芯片之间,且该引线包覆有塑封料;以及盖片,覆盖所述芯片并通过导热胶与所述芯片接合。 [0005] To achieve the above object, the present invention provides a package structure, the structure comprising: a substrate; chip mounted on the substrate; a lead connected between the substrate and the chip, and the wire is coated with plastic material; and a cover sheet covering said chip and joined by a thermally conductive adhesive to the chip.

[0006] 相应地,本发明还提供了一种封装方法,该方法包括:将芯片贴装在基板上;在所述基板与芯片之间连接引线,且该引线包覆有塑封料;以及盖片覆盖所述芯片并通过导热胶与所述芯片接合。 [0006] Accordingly, the present invention also provides a packaging method comprising: mounting a chip on a substrate; connecting leads between the substrate and the chip, and the wire is coated with plastic material; and a cover cover sheet and said chip joined by a thermally conductive adhesive to the chip.

[0007] 通过上述技术方案,本发明将盖片通过涂覆在芯片上的导热胶连接在芯片上,可以通过导热系数高的盖片将芯片产生的大量热量有效地传递到外界,对芯片的散热性能和可靠性都有显著的提高。 [0007] Through the above technical solution, the present invention is connected to the cover sheet on the chip by coating the thermally conductive adhesive on the chip, a large amount of heat by a high thermal conductivity of the cover sheet generated by the chip is efficiently transmitted to the outside of the chip thermal performance and reliability are significantly improved.

[0008] 本发明的其他特征和优点将在随后的具体实施方式部分予以详细说明。 [0008] Other features and advantages of the present invention will be described in detail in a subsequent portion of the detailed description.

附图说明 BRIEF DESCRIPTION

[0009] 附图是用来提供对本发明的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但并不构成对本发明的限制。 [0009] The drawings are provided for further understanding of the invention and constitute a part of this specification, the following detailed description serve to explain the embodiments of the present invention, but not limit the present invention. 在附图中: In the drawings:

[0010] 图la、图lb、图1c分别示出了本发明提供的封装结构的示意图;以及 [0010] FIG. La, FIG lb, respectively, in FIG. 1c shows a schematic diagram of the present invention provides a package structure; and

[0011] 图2是本发明提供的封装方法的流程图。 [0011] FIG 2 is a flowchart illustrating the packaging method of the present invention provides.

[0012] 附图标记说明 [0012] REFERENCE NUMERALS

[0013] 1、基板 2、芯片 [0013] 1, the substrate 2, the chip

[0014] 3、引线 4、盖片 [0014] 3, lead wire 4, the cover sheet

[0015] 5、塑封料6、导热胶 [0015] 5, 6 plastic materials, thermal plastic

具体实施方式 detailed description

[0016] 以下结合附图对本发明的具体实施方式进行详细说明。 [0016] The following specific embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. 应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。 It should be understood that the specific embodiments described herein are only to illustrate and explain the present invention and are not intended to limit the present invention.

[0017] 图la、图lb、图1c分别示出了三种不同形式的盖片。 [0017] FIG. La, FIG lb, FIG. 1c illustrate three different forms of the cover sheet. 如图1a所示,该封装结构包括基板1、芯片2、引线3和盖片4。 As shown in FIG 1a, the package structure includes a substrate 1, chip 2, wire 3 and the cover sheet 4. 其中,芯片2贴装在基板I上,在基板I与芯片2之间连接有引线3以通过引线3电连接基板I与芯片2,并且该引线3包覆有塑封料5,盖片4覆盖芯片2,并且该盖片4通过导热胶6与芯片2接合。 Wherein the chip 2 is mounted on the substrate I, I and the chip between the substrate 2 are connected to the lead 3 is connected through three electrical leads of the substrate I with the chip 2 and the wire 3 coated with a plastic material 5, the cover sheet 4 covers chip 2 and the cover sheet 46 bonded to the chip 2 through the thermally conductive glue.

[0018] 图1a示出了一种盖片4仅覆盖芯片2的封装结构,此时盖片4为方块形,图1b和图1c分别示出了盖片4既覆盖芯片2又覆盖包覆引线3的塑封料5的封装结构,其中,图1b中的盖片4对应于芯片2的部分相对于该盖片4整体凸出,图1c中的盖片4对应于芯片2的部分相对于该盖片4整体凹入。 [0018] Figure 1a shows a cover sheet 4 covers only the chip package structure 2, where the cover sheet 4 is a block-shaped, 1b and 1c illustrate both cover sheet 4 covers the chip 2 and cover coating 3 portion of the lead molding compound encapsulating structure 5, wherein the cover sheet of Figure 1b corresponding to 4 chip 2 with respect to the cover plate 4 integrally projecting, 1c in FIG. 4 corresponds to the portion of the cover sheet with respect to the chip 2 the cover sheet 4 integrally recess. 在图1b和图1c中,盖片4通过导热胶6与芯片2和塑封料5接合。 In Figures 1b and 1c, the heat conductive adhesive sheet 4 cover 6 is engaged with the chip 2 through 5 and the molding compound.

[0019] 其中,图1a和图1c所示出的封装结构可以节省制作盖片4的材料,还能够降低加工成本。 [0019] wherein the package structure shown in Figures 1a and 1c can save material of the cover sheet 4, can also reduce processing costs. 并且图1c的盖片4可以由平板经冲压工艺制成。 1c and FIG cover sheet 4 may be made flat by a stamping process.

[0020] 其中,导热胶6除了用于粘接之外,还用于填补芯片2与盖片4接合时产生的微空隙及芯片2和盖片4的表面凹凸不平的空洞,这样可以减小传热接触热阻,以使得在芯片2工作时产生的热量可以直接通过盖片4传递到外界。 [0020] wherein, in addition to the heat conductive adhesive 6 for bonding, but also for the uneven surface of the micro voids and chip 2 and the cover sheet generated when the flap 4 joined to fill a cavity 4 of chip 2, which can be reduced contact thermal resistance of heat transfer, so that the heat generated in the chip 2 may be directly working cover sheet 4 is transmitted to the outside through. 若采用图1b或图1c所示的结构,芯片2边缘的热量可以通过塑封料5再通过盖片4传递到外界。 Figure 1b or the use of a structure as shown in FIG. 1c, the edge of the chip 2 can be heat plastic materials through the cover sheet 5 and then transmitted to the outside through 4.

[0021] 其中,盖片4的材料可以为金属或合金或陶瓷,例如,可以为铜或铝。 [0021] wherein the cover sheet material 4 may be a metal or alloy or ceramic, for example, copper or aluminum. 而盖片4对应于芯片2部分的厚度(也就是位于芯片2上部的盖片的厚度)可以为0.3mm至1_,太薄则散热性能不佳,太厚则体积太大,重量也会太重。 And the cover sheet 2 corresponding to the portion of the chip 4 having a thickness (i.e. thickness of the cover sheet 2 located in the upper portion of the chip) may be 0.3mm to 1_, poor thermal performance is too thin, the volume is too thick, the weight will be too weight.

[0022] 相应地,本发明还提供了一种封装方法,首先将芯片2贴装在基板I上,然后在基板2与芯片2之间连接引线3,且该引线3包覆有塑封料5,再用盖片4覆盖芯片2并通过导热胶6将盖片4与芯片2接合,如果盖片4还覆盖包覆引线3的塑封料5,可以通过导热胶6与塑封料5接合。 [0022] Accordingly, the present invention also provides a method of packaging, the chip 2 is first mounted on the substrate I, and the lead 3 is connected between the substrate 2 and the chip 2, and 3 of the lead coated with plastic material 5 , then the cover sheet 4 covers the chip 2 and the cover sheet 6 and the die 4 bonded by a thermally conductive adhesive 2, if the cover plate 4 also covers the lead-coated molding compound 53 to be engaged with the plastic material 5 by a thermally conductive adhesive 6.

[0023] 此外,为了能够进一步提高散热性能,将封装体连接到PCB板(印刷电路板)上时,还可以将传统方法中安装在塑封料或芯片上的散热装置安装在盖片4上(图中未示出),如散热片,以进一步提高散热性能。 The heat dissipation device when the [0023] Further, in order to further improve the heat dissipation performance of the package is connected to the PCB (printed circuit board), may also be the conventional method is mounted on a plastic material or chips mounted on the cover plate 4 ( FIG not shown), such as fins, to further improve the heat dissipation performance.

[0024] 图2是本发明提供的封装方法的流程图,如图2所示,首先将芯片2贴装在基板I上,然后通过引线3使芯片2与基板I电连接,即进行引线3键合操作。 [0024] FIG 2 is a flowchart of a method of the present invention provides a package, as shown in FIG. 2, the chip 2 is first mounted on the substrate I, and then the chip 2 via the lead 3 is electrically connected with the substrate I, i.e. wire-3 bonding operations. 将用于填充塑封料5的模板放置到基板I上,以便于填充塑封料5,然后进行塑封料5填充和塑封料5固化,其中,塑封料5固化的方式是采取加热的方式,使塑封料5发生固化反应。 The template for filling the plastic material 5 is placed on the substrate I, 5 in order to fill the molding compound, and then molding material 5 is filled and cured molding compound 5, wherein the cured plastic material 5 is to take the way of heat to the plastic 5 material curing reaction. 在塑封料5固化之后,将模板去除,再进行导热胶6涂覆,如果采用图1a的封装结构,则仅在芯片2上涂覆导热胶6,如果采用图1b和图1c的封装结构,则在芯片2和包覆引线3的塑封料5上均涂覆导热胶6,此外,无论采取哪种封装结构,均可以在盖片4上涂覆导热胶6,其中导热胶6的涂覆方法可以采用点胶法进行涂覆。 After the plastic material 5 is cured, the template is removed, then the heat conductive adhesive coating 6, if the package structure of Figure 1a, the thermally conductive adhesive coating 6, and if Fig. 1b only on the chip package of FIG. 1c, 2, the coating on the chip 2 and the lead molding material 53 are coated with a thermally conductive adhesive 6, in addition, regardless of which package taken, thermally conductive adhesive can be coated on the cover sheet 46, wherein the coating thermally conductive adhesive 6 The method may be performed using a dispensing method and coating. 在导热胶6涂覆完成之后,可以进行盖片4贴放,这里可以使用本领域技术人员熟知的贴装机进行盖片4的贴放。 After the heat conductive adhesive 6 applied, the cover sheet 4 may be placed, may be used herein are well known to those skilled in the cover plate affixed placement machines put 4. 最后,进行导热胶6固化的操作,导热胶6的固化可以采取本领域技术人员熟知的在传送式加热炉或箱式加热炉中进行加热的固化方式。 Finally, a thermally conductive adhesive curing operation 6, the cured thermally conductive adhesive 6 can take well known to those skilled in the way of heating in the curing furnace or a conveyor furnace box.

[0025] 在图2提供的流程之后,可以进行常规的植球、切割等后续步骤。 [0025] After the process provided in FIG. 2, the conventional step may be performed subsequent bumping, cutting and the like.

[0026] 需要说明的是,本发明提供的封装方法的具体细节及益处与本发明提供的封装结构相对应,于此不予赘述。 [0026] Incidentally, details of the package structure of the present invention provides a method of encapsulation and the benefits provided by the present invention correspond to this are not repeated.

[0027] 以上结合附图详细描述了本发明的优选实施方式,但是,本发明并不限于上述实施方式中的具体细节,在本发明的技术构思范围内,可以对本发明的技术方案进行多种简单变型,这些简单变型均属于本发明的保护范围。 [0027] described above in conjunction with the accompanying drawings of the preferred embodiment of the present invention, however, the present invention is not limited to the specific details of the above embodiment, within the technical scope of the spirit of the present invention, various technical solutions of the present invention. simple variations, these simple modifications belong to the scope of the present invention.

[0028] 本发明提供的技术可以适用于需要通过模塑工艺对引线及其键合进行保护的封装结构,例如,FBGA (细间距球栅阵列)、QFN (方形扁平无引脚封装)、QFP (方型扁平式封装)等基板或引线框架的封装形式。 [0028] The present invention provides techniques may be applied to the need for wire bonding and encapsulation structure is protected by a molding process, e.g., FBGA (Fine Pitch Ball Grid Array), QFN (quad flat no-lead package), a QFP package (Quad flat package) and the like of the substrate or leadframe. 此外,本发明通过将露出的芯片上表面与导热系数较高的盖片接合,使芯片工作时产生的热量有效地通过盖片传递到外界,从而提高了芯片的可靠性,并且盖片比较容易实现回收利用,因而与传统技术相比,本发明具有一定的环保意义。 Further, the present invention is higher by a chip on the exposed surface of the cover sheet and the thermal conductivity of engagement, so that heat generated when the chip operates efficiently transmitted to the outside through the cover sheet, thereby improving the reliability of the chip, and the cover sheet is relatively easy recycling achieved, as compared with the conventional art, the present invention has certain environmental significance.

[0029] 另外需要说明的是,在上述具体实施方式中所描述的各个具体技术特征,在不矛盾的情况下,可以通过任何合适的方式进行组合。 [0029] Further to be noted that, in various specific features of the above-described specific embodiment described, without conflict, may be combined in any suitable manner. 为了避免不必要的重复,本发明对各种可能的组合方式不再另行说明。 To avoid unnecessary repetition, the present invention without further description of the various possible combinations.

[0030] 此外,本发明的各种不同的实施方式之间也可以进行任意组合,只要其不违背本发明的思想,其同样应当视为本发明所公开的内容。 [0030] Further, among various embodiments of the present invention may be arbitrarily combined as long as it does not violate the spirit of the invention, which should also be considered as the disclosure of the present invention.

Claims (10)

  1. 1.一种封装结构,其特征在于,该结构包括: 基板; 芯片,贴装在所述基板上; 引线,连接在所述基板与芯片之间,且该引线包覆有塑封料;以及盖片,覆盖所述芯片并通过导热胶与所述芯片接合。 1. A package structure, wherein the structure comprising: a substrate; chip mounted on the substrate; a lead connected between the substrate and the chip, and the wire is coated with plastic material; and a cover sheet, covering the chip and thermally bonded by adhesive to the chip.
  2. 2.根据权利要求1所述的封装结构,其特征在于,所述盖片还覆盖包覆所述引线的塑封料,并通过导热胶与该塑封料接合。 2. The package structure according to claim 1, wherein said cover sheet further covers the lead-coated plastic materials, plastic materials and by engagement with the thermally conductive glue.
  3. 3.根据权利要求2所述的封装结构,其特征在于,所述盖片对应于所述芯片的部分相对于该盖片整体凸出或凹入。 3. The package structure according to claim 2, wherein the portion of the lid sheet corresponding to the chip to the cover sheet relative to the overall convex or concave.
  4. 4.根据权利要求1所述的封装结构,其特征在于,所述盖片的材料为金属或合金或陶瓷。 4. The package structure according to claim 1, wherein said cover sheet material is a metal or an alloy or a ceramic.
  5. 5.根据权利要求4所述的封装结构,其特征在于,所述盖片的材料为铜或铝。 5. The package structure according to claim 4, wherein said cover sheet material is copper or aluminum.
  6. 6.根据权利要求1或2所述的封装结构,其特征在于,所述盖片对应于所述芯片的部分的厚度为0.3mm至1mm。 The package structure according to claim 1 or claim 2, characterized in that the cover plate corresponding to the thickness of the portion of the chip is 0.3mm to 1mm.
  7. 7.一种封装方法,其特征在于,该方法包括: 将芯片贴装在基板上; 在所述基板与芯片之间连接引线,且该引线包覆有塑封料;以及将盖片覆盖在所述芯片上并通过导热胶与所述芯片接合。 A packaging method, wherein the method comprising: mounting a chip on a substrate; connecting leads between the substrate and the chip, and the wire is coated with plastic material; and in that the cover slip and said chip joined by a thermally conductive adhesive to the chip.
  8. 8.根据权利要求7所述的封装方法,其特征在于,所述盖片还覆盖包覆所述引线的塑封料,并通过导热胶与该塑封料接合。 8. A method of packaging according to claim 7, wherein said cover sheet further covers the lead-coated plastic materials, plastic materials and by engagement with the thermally conductive glue.
  9. 9.根据权利要求7所述的封装方法,其特征在于,所述盖片对应于所述芯片的部分相对于该盖片整体凸出或凹入。 9. A method of packaging according to claim 7, wherein the flap portion corresponding to the chip to the cover sheet with respect to the overall convex or concave.
  10. 10.根据权利要求7所述的封装方法,其特征在于,所述导热胶采用点胶法进行涂覆。 10. A method of packaging according to claim 7, wherein said thermally conductive adhesive is coated using dispensing method.
CN 201410033771 2014-01-24 2014-01-24 Encapsulation structure and method CN103794575A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1187037A (en) * 1996-12-30 1998-07-08 Lg半导体株式会社 Semiconductor package and method for fabricating same
CN1577815A (en) * 2003-06-28 2005-02-09 三星电机株式会社 High-density chip scale package and method of manufacturing the same
CN101101881A (en) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 Heat-radiation type package structure and its method for making

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1187037A (en) * 1996-12-30 1998-07-08 Lg半导体株式会社 Semiconductor package and method for fabricating same
CN1577815A (en) * 2003-06-28 2005-02-09 三星电机株式会社 High-density chip scale package and method of manufacturing the same
CN101101881A (en) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 Heat-radiation type package structure and its method for making

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