CN103779317B - Semiconductor structure and the method for reducing signal interference in semiconductor structure - Google Patents

Semiconductor structure and the method for reducing signal interference in semiconductor structure Download PDF

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Publication number
CN103779317B
CN103779317B CN201210413876.XA CN201210413876A CN103779317B CN 103779317 B CN103779317 B CN 103779317B CN 201210413876 A CN201210413876 A CN 201210413876A CN 103779317 B CN103779317 B CN 103779317B
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electrode
semiconductor structure
capacitance
substrate
penetrating electrode
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CN103779317A (en
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李宗霖
吴浚昌
曾誌裕
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United Microelectronics Corp
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United Microelectronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

The invention provides a kind of semiconductor structure, includes a substrate, one first silicon penetrating electrode, an induction structure and a capacitance structure.First silicon penetrating electrode is set in the substrate, and has one first signal.Induction structure is set in the substrate.Capacitance structure is electrical connected with induction structure, and forms a lc circuit with induction structure to obstruct the interference of the first signal.Present invention also offers a kind of method for reducing signal interference in semiconductor structure.

Description

Semiconductor structure and the method for reducing signal interference in semiconductor structure
Technical field
The present invention be on a kind of semiconductor structure, especially for, be that one kind can avoid high-frequency signal to neighbouring circuit Form the semiconductor structure of interference.
Background technology
In the information-intensive society in modern times, the microprocessor system that is made up of integrated circuit (integrated circuit, IC) System is generally applied to the every aspect of life, such as electrical home appliances, mobile communication equipment, the individual calculus automatically controlled already Machine etc., there is the use of integrated circuit.And increasingly progressing greatly with science and technology, and human society is thought for the various of electronic product As so that integrated circuit also develops toward more polynary, more accurate, smaller direction.
General alleged integrated circuit, is formed via the crystal grain (die) produced in manufacture of semiconductor.Manufacture crystal grain Process, it is by producing a wafer (wafer):First, multiple regions are distinguished on wafer, and in each region On, by various manufacture of semiconductor such as deposition, lithographic, etching or planarization process, to form various required circuit traces.So Afterwards, carrying out in general testing procedure whether can smooth operation to test inner member.Then, then to the regional on wafer Carry out cutting and form each crystal grain, and be packaged into chip (chip), finally chip is electrically connected to a circuit board, such as a print again Printed circuit board (printed circuit board, PCB), after making the pin of chip and printed circuit board (PCB) (pin) electrical connection, The processing of various programmings can be performed.
In order to improve chip functions and efficiency, increase and actively spend so as to which more semiconductor elements can be accommodated under the confined space Part, relevant manufactures develop the stacking of many semiconductor chips, include chip package (flip-chip) technology, multicore Piece encapsulation (multi-chip package, MCP) technology, encapsulation storehouse (packageon package, PoP) technology, encapsulation in Packaging body (package in package, the PiP) technology of Tibetan etc., can be increased by mutual storehouse between chip or packaging body Add the positive degree of semiconductor element in unit volume.Develop a kind of referred to as silicon through hole (through silicon again in recent years Via, TSV) technology, the interior bonds (interconnect) of each chip chamber in packaging body can be promoted, by storehouse efficiency Further up lifted.
However, the existing circuit transmitted using silicon penetrating electrode as signal is also encountered by some problems, because silicon is through electricity For pole is compared to known metal interconnecting system, the volume that it occupies is larger, therefore works as the letter that silicon penetrating electrode is transmitted Number it is also easier to produce noise to other circuits, have impact on the quality of element.
The content of the invention
The present invention is in there is provided a kind of semiconductor structure, to solve foregoing problems.
According to one embodiment of present invention, the invention provides a kind of semiconductor structure, a substrate, one first silicon are included Penetrating electrode, an induction structure and a capacitance structure.First silicon penetrating electrode is set in the substrate, and with one first letter Number.Induction structure is set in the substrate.Capacitance structure is electrical connected with induction structure, and with induction structure formed a lc circuit with Obstruct the interference of the first signal.
According to another embodiment of the invention, the invention provides a kind of side for reducing signal interference in semiconductor structure Method.Semiconductor structure is provided first, comprising a substrate, one first silicon penetrating electrode set in the substrate, an induction structure sets Put in substrate, a capacitance structure, be electrically connected with induction structure to form a lc circuit, and lc circuit has a resonant frequency. Then, one first signal is provided to the first silicon penetrating electrode, wherein the frequency of the first signal and resonant frequency are substantially the same.
Inductance is used as by silicon penetrating electrode, can with capacitance structure formed lc circuit, its resonant frequency can and high frequency Signal Matching, and then reduce influence of the high-frequency signal to other electron component.Therefore, the element of a better quality can be obtained.
Brief description of the drawings
Fig. 1 to Figure 11 is a kind of schematic diagram of semiconductor structure of the present invention.
[main element label declaration]
300 substrate 324a capacitance structures
302 dielectric layer 324b capacitance structures
302b inner layer dielectric layer 324c capacitance structures
304 first silicon penetrating electrode 324d capacitance structures
The first electrode of 306 first line 326
308 second silicon penetrating electrode 326a first electrodes
308a the second silicon penetrating electrode 326b first electrodes
The capacitance dielectric layer of the second silicon of 308b penetrating electrode 328
308c the second silicon penetrating electrode 328a capacitance dielectric layers
310 second circuit 328b capacitance dielectric layers
The second electrode of 312 the 3rd silicon penetrating electrode 330
314 tertiary circuit 330a second electrodes
316 metal interconnecting system 330b second electrodes
The connection line of 318 first signal 332
The connection line of 320 the 3rd signal 334
The connection line of 322 electronic component 336
The voltage providing unit of 324 capacitance structure 340
Embodiment
To enable those skilled in the art to be further understood that the present invention, the hereafter special several preferably implementations for enumerating the present invention Example, and coordinates institute's accompanying drawings, describe in detail the present invention constitution content and it is to be reached the effect of.
Fig. 1, Fig. 2 and Fig. 3 are refer to, depicted is a kind of schematic diagram of semiconductor structure of the present invention, and wherein Fig. 2 is Fig. 1 In along AA ' lines diagrammatic cross-section, and Fig. 3 be Fig. 1 and Fig. 2 equivalent circuit diagram.As shown in Figures 1 and 2, of the invention half Conductor structure 400 includes a substrate 300 and the multilayer dielectric layer 302 being arranged in substrate 300.Substrate 300 is, for example, silicon substrate Bottom (silicon substrate), epitaxy silicon base (epitaxial silicon substrate), silicon germanium semiconductor substrate (silicon germaniumsubstrate), silicon carbide substrate (silicon carbide substrate) or silicon-coated insulated Substrate (silicon-on-insulator substrate, SOI substrate).Dielectric layer 302 includes various dielectric materials, Preferably low-k material, e.g. silica (SiO2), methyl silicate dielectric material Materials such as (methylsilsesquioxane, MSQ), but be not limited thereto.
The present invention semiconductor structure 400 also comprising one first silicon penetrating electrode 304, one second silicon penetrating electrode 308 with And one the 3rd silicon penetrating electrode 312, it is arranged in substrate 300 and runs through substrate 300.In one embodiment of the invention, first Silicon penetrating electrode 304, the second silicon penetrating electrode 308 and the 3rd silicon penetrating electrode 312 one of them, two or can also all prolong Extend in one or more layers of dielectric layer 302.First silicon penetrating electrode 304, the second silicon penetrating electrode 308 and the 3rd silicon Penetrating electrode 312 includes conductive layer (not shown) and the insulating barrier (not shown) being arranged between conductive layer and substrate 300, leads Electric layer can include one or more layers metal level, such as a metal level (such as metallic copper) and a barrier layer (such as titanium nitride).
In addition, the semiconductor structure 400 of the present invention also includes a metal interconnecting system (metalinterconnection System) 316, it is arranged in dielectric layer 302, and positioned at the first silicon penetrating electrode 304, the second silicon penetrating electrode 308 and the Three tops of at least one of silicon penetrating electrode 312.The metal interconnection wire preparing process preferably known to use of metal interconnecting system 316 Formed, its material for example comprising silver-colored (Ag), copper (Cu), aluminium (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or above-mentioned nitride, but It is not limited thereto.In an embodiment, metal interconnecting system 316 include a first line 306, one second circuit 310 with And a tertiary circuit 314, it is electrically connected the first silicon penetrating electrode 304, the second silicon penetrating electrode 308 and the 3rd silicon and passed through Wear electrode 312.
The silicon penetrating electrode 304 of first line 306 and first is electrically connected with one first signal 318, preferably implements in of the invention In example, the first signal 318 is a kind of high-frequency signal, such as frequency is higher than 3MHz signal.In an embodiment, the first signal 318 be a radio frequency (radio frequency, RF) signal.The silicon penetrating electrode 312 of tertiary circuit 314 and the 3rd is electrically connected with one 3rd signal 320, the 3rd signal 320 are then the input/output signal needed for general electronic component, pass through this 3rd signal 320 The electronic component 322 that tertiary circuit 314 is connected in substrate 300, e.g. a metal-oxide semiconductor (MOS) crystal can be driven Manage (metal oxide semiconductor transistor, MO S transistor).
Because the first signal 318 is a kind of high-frequency signal, therefore easily the 3rd neighbouring signal 320 is produced when running Disturb (noise), and then have impact on the apparent mass of electronic component 322.Therefore the one of feature of the present invention is the provision of One extra " lc circuit " is in semiconductor structure 400, to reduce foregoing problems.As shown in Fig. 3 equivalent circuit diagram, the present invention One " lc circuit " is provided in semiconductor structure 400, its resonant frequency (resonant frequency, fr) can pass through following public affairs Formula 1 obtains:
(formula 1)
Wherein C refers to capacitance, and L refers to inductance value.By suitably adjusting capacitance and inductance value, make being total to for lc circuit First signal 318 of vibration frequency and high frequency is identical, when the first signal 318 of high frequency pass through the first silicon penetrating electrode 304 with And during first line 306, its resonance noise will be absorbed by this lc circuit, and then reduce to the 3rd silicon penetrating electrode 312, the The interference of three circuits 314 and electronic component 322.
On the embodiment of lc circuit of the present invention, Fig. 2 refer again to.As shown in Fig. 2 wherein the second silicon is through electricity Pole 308 is as the inductance L in lc circuit, then has a capacitance structure 324 in the second circuit 310 to be used as the electricity in lc circuit Hold C.In the present embodiment, capacitance structure 324 has a first electrode 326, a second electrode 330 and is arranged between Capacitance dielectric layer 328, therefore form one " metal-insulator-metal (metal-insulator-metal, MIM) " knot Structure.
In an embodiment, the first silicon penetrating electrode 304, the second silicon penetrating electrode 308 and the 3rd silicon penetrating electrode 312 exist The relative position of substrate 300 can adjust depending on product design.As shown in figure 4, the second silicon penetrating electrode 308 of the present embodiment It can be not arranged between the first silicon penetrating electrode 304 and the 3rd silicon penetrating electrode 312, for example, the second silicon penetrating electrode 308 The edge or corner of substrate 300 in crystal grain (die) or chip (chip) can be arranged on.
As shown in figure 5, in another embodiment of the present invention, can run through as inductance in lc circuit comprising multiple second silicon Electrode 308, such as the second silicon penetrating electrode 308a, the second silicon penetrating electrode 308b and the second silicon penetrating electrode 308c.Yu Ben In invention preferred embodiment, these the second silicon penetrating electrode 308 are (in series) in series with each other, for example, the second silicon runs through Electrode 308a is electrically connected with by a connection line 332 and the second silicon penetrating electrode 308b, and the second silicon penetrating electrode 308b passes through One connection line 334 and the second silicon penetrating electrode 308c are electrically connected with.Preferably, connection line 332 are located at connection line 334 Not on homonymy of substrate 300.Finally, the second silicon penetrating electrode 308a is equally electrical with the capacitance structure 324 in the second circuit 310 Connection.By the series connection between multiple second silicon penetrating electrode 308, the inductance value in lc circuit can be increased.As shown in fig. 6, If the inductance in lc circuit includes multiple second silicon penetrating electrode 308, the arrangement between them preferably may enclose the first silicon Penetrating electrode 304, to provide preferable noise suppression effect.And in another embodiment, these the second silicon penetrating electrode 308 Other positions can be arranged on, such as surround the 3rd silicon penetrating electrode 312, or considers product design and is arranged on chip Corner or edge.
As shown in fig. 7, in another embodiment of the present invention, the second silicon penetrating electrode 308 as inductance can also have Continuous annular cross-section, it can surround the first silicon penetrating electrode 304 completely, and can provide shield effectiveness can also conduct simultaneously Inductance.In an embodiment, the serial section of the second silicon penetrating electrode 308 can be arbitrary shape, such as circular, rectangle Deng.
Electric capacity in the RC circuits of the present invention, except the MIM being arranged in metal interconnecting system 316 electricity shown in Fig. 2 Hold beyond structure, it is possible to have different embodiments.As shown in figure 8, first electrode 326a in capacitance structure 324a with Second electrode 330a material can be metal, for example, silver-colored (Ag), copper (Cu), aluminium (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or Above-mentioned nitride, and capacitance dielectric layer 328a can be then other materials different from dielectric layer 302, e.g. high dielectric is normal Material is counted, in this way hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium silicon oxide, HfSiO4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON) etc., but be not limited thereto. Using high dielectric constant material and metal material, capacitance structure 324a capacitance can be increased.
As shown in figure 9, the capacitance structure 324b of the present embodiment is provided in multilayer dielectric layer 302 near substrate 300 Dielectric layer 302 in, i.e., general alleged inner layer dielectric layer (inter-layer dielectric, ILD) 302b.In this implementation In example, the second silicon penetrating electrode 308 does not extend through dielectric layer 302, connects electric capacity not over metal interconnecting system 316 yet Structure 324b, but it is directly in electrical contact with capacitance structure 324b.In the present embodiment, this capacitance structure 324b includes one first The capacitance dielectric layer 228b of electrode 326b, second electrode 330b and setting in both.In an embodiment, first electrode 326b and second electrode 330b is polysilicon (poly-silicon), and capacitance dielectric layer 328b can be silica, with shape Into " polysilicon-insulating layer-polysilicon (poly-insulation-poly, PIP) " structure.In an embodiment, the first electricity One of them is polysilicon to pole 326b and second electrode 330b, and another is metal level.In the present embodiment, this capacitance structure Can the arrange in pairs or groups processing procedures of electronic component 322 of 324b are formed together, re-form inner layer dielectric layer 302b covering capacitance structures afterwards 324b and electronic component 322, finally re-form the metal interconnecting system 316 above inner layer dielectric layer 302b.
The capacitance structure of the present invention can also be located in another chip (chip), and be run through by circuit and the second silicon Electrode 308 is electrically connected with.As shown in Figure 10, the semiconductor structure of the present embodiment includes at least one first chip 402 and one the Two chips 404, both mutual storehouses.The structure of first chip 402 is similar with Fig. 2 chip structure.As shown in Figure 10, this implementation The capacitance structure 324c of example is arranged in the second chip 404, and the second silicon penetrating electrode 308 is then arranged in the first chip 402. Wherein, capacitance structure 324c is connected by connection line 336 with the second circuit 310 in the first chip 402, to be electrically connected to Second silicon penetrating electrode 308.In an embodiment, connection line 336 can be tin ball (solderbump) or reroute layer (redistribution layer,RLD).Or as shown in figure 11, connection line 336 can also be routing (wiring bonding).In other embodiments of the present invention, multiple chips of the invention also can be according to other encapsulation procedures and with difference Embodiment.For example, in an embodiment, the second chip 402 can be various circuit board (print circuit board, PCB) or silicon intermediary layer (Siinterposer), and capacitance structure can be discrete (discrete) member on circuit boards Part.
And in another embodiment of the present invention, as shown in figure 11, capacitance structure 324d can also be further attached to an electricity Pressure provides unit 340.By appropriate voltage is provided capacitance structure 324d, can adjust capacitance structure 324d capacitance, So that lc circuit can more match the frequency of the first signal 318, to reach optimal signal blocker effect.
It is worth noting that, can arbitrarily be arranged in pairs or groups previously with regard to the embodiment of capacitance structure and inductance, such as shown in Fig. 5 Second silicon penetrating electrode 308 of multiple series connection Figure 10 capacitance structures 324c that can arrange in pairs or groups is located at the embodiment party of another chip Formula, or, this capacitance structure 324c can also be further attached to a voltage providing unit 340 as shown in figure 11, or, in Fig. 5 The inductance of series winding can also be located on another chip, or be discrete element on circuit boards.The capacitance structure of the present invention 324 are also not necessarily limited to foregoing embodiment, for example, capacitance structure 324 can also be coronal electric capacity (crown capacitor) or Deep channel capacitor (deep trench capacitor) etc., also, it is any so that multiple capacitance structures or induction structure be in parallel, string The mode of connection should all belong to the exposure scope of the present invention in a manner of forming lc circuit.
According to the features of the present invention, high frequency is reduced using silicon penetrating electrode and capacitance structure present invention also offers a kind of The method of signal.Related diagram may be referred to Fig. 2.Semiconductor structure 400 is provided first, and wherein semiconductor structure 400 has There are a substrate 300 and the multilayer dielectric layer 302 being arranged in substrate 300, wherein substrate 300 has one first silicon penetrating electrode 304 and one second silicon penetrating electrode 308, there is a first line 306 and a capacitance structure 324 in dielectric layer 302.First Silicon penetrating electrode 304 is electrically connected with first line 306, and the second silicon penetrating electrode 308 is electrically connected with capacitance structure 324, both shapes Into a lc circuit, and there is a resonant frequency.Then, one first is provided through through hole 304 to the silicon of first line 306 and first Signal 318, wherein the frequency of the first signal 318 and the resonant frequency are substantially the same.
In summary, invention provides a kind of semiconductor structure and using the silicon in the semiconductor structure through electricity Pole is used as the method for reducing high-frequency signal noise with capacitance structure., can be with capacitive junctions by silicon penetrating electrode as inductance Lc circuit is configured to, its resonant frequency can match with high-frequency signal, and then reduce shadow of the high-frequency signal to other electron component Ring.Therefore, the element of a better quality can be obtained.
The foregoing is only presently preferred embodiments of the present invention, all equivalent changes done according to scope of the invention as claimed with Modification, it should all belong to the covering scope of the present invention.

Claims (17)

1. a kind of semiconductor structure, comprising:
One substrate;
One first silicon penetrating electrode, is arranged in the substrate, and the first silicon penetrating electrode has one first signal;
One induction structure is arranged in the substrate, and wherein the inductance includes one second silicon penetrating electrode;And
One capacitance structure is electrical connected with the induction structure, and wherein the capacitance structure includes a first electrode, a capacitance dielectric layer And a second electrode, the capacitance dielectric layer are arranged between the first electrode and the second electrode, the capacitance structure and the electricity Sense structure forms a lc circuit to obstruct the interference of first signal.
2. a frequency of semiconductor structure according to claim 1, wherein first signal and a resonance of the lc circuit Frequency is substantially the same.
3. semiconductor structure according to claim 1, wherein first signal are a radiofrequency signal.
4. semiconductor structure according to claim 1, wherein the second silicon penetrating electrode have a continuous closed section, its The first silicon penetrating electrode is surrounded completely.
5. semiconductor structure according to claim 1, wherein the second silicon penetrating electrode are arranged on the edge of the substrate.
6. semiconductor structure according to claim 1, the wherein inductance are arranged on this comprising multiple second silicon penetrating electrode In substrate.
7. semiconductor structure according to claim 6, wherein the plurality of second silicon penetrating electrode is in series with each other.
8. semiconductor structure according to claim 1, also set on this substrate comprising multiple dielectric layers, and the capacitive junctions Structure is arranged in the plurality of dielectric layer.
9. semiconductor structure according to claim 8, the wherein electric capacity are arranged in the plurality of dielectric layer near the base One layer of bottom.
10. semiconductor structure according to claim 1, the wherein first electrode include metal with the second electrode.
11. semiconductor structure according to claim 1, the wherein first electrode or the second electrode at least one of which bag Containing polysilicon.
12. semiconductor structure according to claim 1, the wherein induction structure are arranged in one first chip, and this is partly Conductor structure also includes one second chip, and wherein the capacitance structure is arranged in second chip, and the capacitance structure passes through one Connection line is electrically connected with the induction structure.
13. semiconductor structure according to claim 12, the wherein connection line include a tin ball, a redistribution layer or a dozen Line.
14. semiconductor structure according to claim 1, the wherein capacitance structure are also electrically connected with a voltage providing unit.
15. a kind of method for reducing signal interference in semiconductor structure, comprising:
Semiconductor structure is provided, comprising:
One substrate;
One first silicon penetrating electrode, is arranged in the substrate;
One induction structure, it is arranged in the substrate, the inductance includes one second silicon penetrating electrode;And
One capacitance structure, it is electrically connected with the induction structure to form a lc circuit, the capacitance structure includes a first electrode, one Capacitance dielectric layer and a second electrode, the capacitance dielectric layer are arranged between the first electrode and the second electrode, LC electricity Road has a resonant frequency;And
One first signal, the wherein frequency of first signal and the substantial phase of the resonant frequency are provided to the first silicon penetrating electrode Together.
16. the method according to claim 15 for reducing signal interference in semiconductor structure, the wherein inductance include multiple Second silicon penetrating electrode is arranged in the substrate, in series with each other.
17. the method according to claim 15 for reducing signal interference in semiconductor structure, the wherein semiconductor structure are also Set on this substrate comprising multiple dielectric layers, and the capacitance structure is arranged in the plurality of dielectric layer.
CN201210413876.XA 2012-10-25 2012-10-25 Semiconductor structure and the method for reducing signal interference in semiconductor structure Active CN103779317B (en)

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TWI441270B (en) * 2008-12-17 2014-06-11 Ind Tech Res Inst The process monitor control apparatus and method for through-silicon vias of a three dimension integrated circuit
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