CN103762166A - Manufacturing method of precisely-aligned bridged-grain polysilicon thin film transistor - Google Patents
Manufacturing method of precisely-aligned bridged-grain polysilicon thin film transistor Download PDFInfo
- Publication number
- CN103762166A CN103762166A CN201110461842.3A CN201110461842A CN103762166A CN 103762166 A CN103762166 A CN 103762166A CN 201110461842 A CN201110461842 A CN 201110461842A CN 103762166 A CN103762166 A CN 103762166A
- Authority
- CN
- China
- Prior art keywords
- manufacture method
- transparent area
- gate
- bridged
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 41
- 239000010409 thin film Substances 0.000 title abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 57
- 238000002513 implantation Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 49
- 239000013078 crystal Substances 0.000 description 26
- 239000010408 film Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000003292 glue Substances 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 238000007715 excimer laser crystallization Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 244000233952 Polygonum bistorta Species 0.000 description 1
- 206010044565 Tremor Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
The invention provides a manufacturing method of a precisely-aligned bridged-grain polysilicon thin film transistor. The manufacturing method includes the following steps that: 1) a polysilicon layer is formed on a substrate; 2) a gate insulating layer, a gate layer and a photoresist are formed on the polysilicon layer; 3) a gray-scale photo-etching mask plate is adopted to expose the photoresist such that a gate mask can be formed, wherein the gray-scale photo-etching mask plate comprises light-transmitting areas at two sides as well as light tight areas and partial light-transmitting areas which are located between the light-transmitting areas and are arranged alternately, wherein the light-transmitting areas at the two sides are adjacent to the light tight areas, and portions in the gate mask, which are corresponding to the partial light-transmitting areas, form grooves, and the depth of the grooves is smaller than the total thickness of the gate mask; and 4), with the gate mask adopted as a barrier, etching is performed, such that a gate can be formed, and ion implantation is performed such that the polysilicon layer can be doped, and therefore, a bridged-grain line as well as a source region and a drain region can be formed.
Description
Technical field
The present invention relates generally to polycrystalline SiTFT (TFT) technology, more specifically, relate to a kind of when having simplified manufacture craft, bridged-grain polycrystalline SiTFT and manufacture method thereof that gate regions is accurately aimed at active layer district.
Background technology
For realizing the industrialization manufacture of multi-crystal TFT Active Matrix Display panel, conventionally need high-quality polysilicon film.It need to meet following requirement: low temperature process, can be lining with realization, low manufacturing cost, stable manufacturing process, high-performance, consistent characteristic and the high reliability of multi-crystal TFT in large-area glass.
High temperature polysilicon technology can be used for realizing high performance TFT, but it can not be used for the simple glass substrate that business display pannel is used.Under such situation, must use low temperature polycrystalline silicon (LTPS).Wherein, comprise three kinds of main LTPS technology: 1, by the solid-phase crystallization (SPC) at 600 ℃ of long term annealings; 2, Excimer-Laser Crystallization (ELC) or flash lamp annealing; 3, crystallization inducing metal (MIC) and relevant variant thereof.But ELC produces best result is expensive.But the minimum time spent of SPC cost is long.
And all polycrystal film materials common be that the crystal grain of film is in size, crystal orientation and random distribution substantially in shape.Crystal boundary is conventionally also harmful to the formation of good TFT, and when this polycrystal film is used as the active layer in TFT, electrical characteristics depend in active channel, there are how many grain and grain boundaries.
The common problem of current all prior aries is that they form much crystal grain with random pattern (pattern) in TFT active channel.The distribution of crystal grain is random, makes electrical characteristics skewness on substrate of TFT.The wide distribution of these electrical characteristics is harmful to and can causes the problem such as mura defect and brightness irregularities the performance of display.
For any semi-conducting material for example silicon, germanium, sige alloy, iii v compound semiconductor and organic semiconductor, the transistorized crystal grain of polycrystal film can form random network.The conduction of crystal grain inside is almost identical with crystalline material, and it is poorer to stride across the conduction meeting of crystal boundary, therefore causes mobility totally to reduce and increase threshold voltage.In the active channel inside of the thin-film transistor of being made by this polycrystal film (TFT), grainiess is almost two-dimensional random network.Randomness and consequential variable-conductance adversely affect display performance and picture quality.
Typical polysilicon structure as shown in Figure 1a, low temperature polycrystalline silicon film 1101 comprises crystal grain 1102.Between adjacent crystal grain 1102, there is obvious crystal boundary 1103.The length scale of each crystal grain 1102 is from tens nanometer to several microns, and is considered to monocrystalline.The defect distribution of many dislocations, stacking fault and dangling bonds is in described crystal boundary 1103.Due to different preparation methods, the crystal grain 1102 of low temperature polycrystalline silicon film 1101 inside can random distribution or along definite direction orientation.As for conventional low temperature polycrystalline silicon film 1101, in crystal boundary 1103, there is serious defect, as shown in Figure 1 b.Major defect in crystal boundary 1103 will be introduced high potential barrier 1104, perpendicular to the described potential barrier 1104 that transports direction (or incline and tremble the vertical component of potential barrier) of charge carrier 1105, will affect initial condition and the ability of charge carrier.For the thin-film transistor of manufacturing on this low temperature polycrystalline silicon film 1101, threshold voltage and field-effect mobility are limited by crystal boundary potential barrier 1104.The crystal boundary 1103 being distributed in when high reverse gate voltage is applied in TFT in drain junction region also causes large leakage current.
Summary of the invention
The present invention proposes a kind of manufacture method of bridged-grain polycrystalline SiTFT, when making it possible to preserve polycrystalline SiTFT (TFT) advantage of bridged-grain (BG) structure, can simplify again technique and accurately aim at.
The manufacture method that the invention provides a kind of bridged-grain polycrystalline SiTFT, comprising: 1) on substrate, form polysilicon layer; 2) on polysilicon layer, form gate insulator, grid layer, photoresist; 3), by photoetching agent pattern, form gate mask, and there is groove in this gate mask; 4) with gate mask for stopping, carry out etching to form grid, and carry out Implantation and form bridged-grain line and source/drain region with doping in polysilicon layer.
According to manufacture method provided by the invention, wherein grid layer consists of low temperature polycrystalline silicon.
According to manufacture method provided by the invention, wherein step 3) in, adopt gray scale lay photoetching mask plate to expose, this gray scale lay photoetching mask plate comprises transparent area, light tight district and part transparent area.
According to manufacture method provided by the invention, wherein the degree of depth of the groove in gate mask is less than the gross thickness of gate mask.According to manufacture method provided by the invention, wherein the degree of depth of the groove in gate mask equals the gross thickness of gate mask, in step 4) the rear grid that forms multi-gate structure.
According to manufacture method provided by the invention, wherein step 4) in, first carry out etching to form grid, then carry out Implantation.According to manufacture method provided by the invention, wherein step 4) in, first carry out Implantation, then carry out etching to form grid.According to manufacture method provided by the invention, wherein the direction of Implantation is perpendicular to substrate.
According to manufacture method provided by the invention, wherein, in gray scale lay photoetching mask plate, transparent area is positioned at both sides, and in the middle of the transparent area alternately, and transparent area is adjacent with light tight district for light tight district and part transparent area
The present invention also provides a kind of bridged-grain polycrystalline SiTFT, utilizes above-mentioned manufacture method to make.
The present invention forms the photo etched mask of BG polysilicon by change tradition, optimize the technique of BG multi-crystal TFT, when simplifying the manufacturing process of BG polycrystalline SiTFT, and realized grid and aimed at the accurate of bridging active area, bridging doping process and source/drain electrode doping process have been merged into a step, and two step photoetching have been merged into a step, manufacturing process and manufacturing cycle and cost have been simplified, and improved the otherness of each TFT on panel, make each TFT electrology characteristic on panel more even, the randomness of grain mobility and grain boundary resistance reduces, there is less leakage current and parasitic capacitance, reduce costs, simplify technique and shortened the processing time.
Accompanying drawing explanation
Fig. 1 a is typical polysilicon structure in prior art;
Fig. 1 b is the figure of the corresponding potential barrier of Fig. 1 a;
Fig. 2 a-2e is the polycrystalline SiTFT fabrication processing figure in U.S. Pat 2010/0171546A1 with BG structure, and wherein Fig. 2 a is depicted as the polysilicon membrane preparing; Fig. 2 b is depicted as and on polysilicon membrane, is coated with photoresist and carries out exposure imaging, and using photoetching offset plate figure as mask, carries out Implantation and form the polysilicon membrane with BG line structure; Fig. 2 c is depicted as and forms gate insulator and grid; Fig. 2 d is depicted as source/drain electrode doping; Fig. 2 e is depicted as formation insulating barrier, and increase income/drain contact hole splash-proofing sputtering metal form contact electrode;
Fig. 3 a-3b is depicted as BG line and aims at the situation while misplacing with grid appearance;
Fig. 4 a-4c is respectively according to the manufacturing flow chart of the method for embodiment 1;
Fig. 5 a-5b is respectively according to the manufacturing flow chart of the method for embodiment 2;
Fig. 6 a-6d is respectively according to the manufacturing flow chart of the method for embodiment 3.
Embodiment
Below in conjunction with the drawings and specific embodiments, a kind of bridged-grain polycrystalline SiTFT and manufacture method thereof of simplifying technique and accurately aim at provided by the invention is described in detail.
Meanwhile, here do to illustrate, in order to make embodiment more detailed, the following examples are best, preferred embodiment, for some known technology those skilled in the art, also can adopt other alternative and implement; Meanwhile, accompanying drawing is not strictly to draw in proportion, and its emphasis is to be only placed in disclosed principle.
In U.S. Pat 2010/0171546 A1, disclosed the polycrystalline SiTFT (TFT) of a kind of bridged-grain (BG) structure.Adopt doping BG polysilicon lines, intrinsic-OR light dope passage is separated into multiple regions.Single gate has covered the whole active channel that comprises the line that adulterates, and is used for controlling flowing of electric current.Use BG polysilicon as active layer, TFT is designed to make electric current vertical current to cross the parallel lines at passage crystal region, and the impact of crystal boundary can reduce.Compared with traditional low temperature polycrystalline silicon TFT, the reliability of BG multi-crystal TFT, uniformity and electric property are all significantly improved.
Brief description is the manufacture process of the BG TFT of U.S. Pat 2010/0171546 A1 once.As shown in Figure 2 a, in glass substrate 1501, deposit one deck low temperature oxide (LTO) as barrier layer 1502, then on barrier layer 1502, form polysilicon layer 1503.
Fig. 2 b is the sectional view of producing bridged-grain structures.On low temperature polycrystalline silicon, be coated with one deck photoresist, utilize the graphical photoresist of mask 1604, make photoresist form dentation 1603.Dopant implant ion, makes exposed area 1601 become doped silicon 1602.At this moment, polysilicon layer 1503 has just become BG polysilicon layer.
With reference to Fig. 2 c, utilize traditional photoetching process to form active island one by one, utilize LPCVD (low-pressure chemical vapor deposition) directly in top, active island deposition LTO gate insulation layer 1801, covering doped region 1701 and not doped region 1702.Then Al/Si-1% alloy is deposited and is photo-etched into gate electrode 1802.
Fig. 2 d is the source of low-temperature polysilicon film transistor and the schematic diagram that drain electrode is injected.As shown in Figure 2 d, utilize gate electrode with ion 1903, to inject raceway groove as ion barrier layer.Source and drain electrode 1902 are formed.Gate electrode 1802 raceway groove 1901 below does not adulterate.
Fig. 2 e is the sectional view of the formation of the metal electrode of low-temperature polysilicon film transistor.Utilize PECVD (plasma enhanced chemical vapor deposition) deposition oxide interlayer insulator 1001, will offer thereafter contact hole, sputtered aluminum-1% silicon is source-drain electrode contact electrode.Last sintering also carries out dopant activation.Utilize bridged-grain structures low temperature polycrystalline silicon just to complete as the TFT manufacturing process of active layer.
From the step of Fig. 2 b, the manufacture craft of BG TFT is than many step photoetching and the doping of traditional multi-crystal TFT.With reference to Fig. 2 c, due to after grid is formed in bridge formation, so also there will be as shown in Figure 3 a various, the situation of the active area misalignment of grid and bridging.Fig. 3 b is on the basis of Fig. 3 a, using grid as stopping the schematic diagram that forms source-drain electrode.In order to reach the object that strides across transverse grain boundaries, the distance between BG line must be less than the size of average crystal grain half originally, is conventionally less than 1 micron.For Fig. 3 b, due to source-drain electrode area and the close together of doping BG line, and doping content is larger, and in follow-up processing, the source-drain electrode alloy of part TFT just there will be situation about being connected with adjacent doping BG line by diffusion, thereby affects the uniformity of TFT.In the time of less for the number of BG line, will have influence on the performance of TFT.
Compare with above-mentioned prior art, the present invention is by forming BG pattern on the mask forming grid, can make grid accurately aim at BG active area, and BG doping and source-drain electrode area doping can complete in same doping step, and can prevent that source-drain electrode alloy is connected with adjacent doping BG line by diffusion.Specific embodiment of the invention method is as follows:
Embodiment 1
The present embodiment provides a kind of manufacture method of bridged-grain polycrystalline SiTFT, as shown in Fig. 4 a-4c, comprising:
1), in glass substrate 101, deposit one deck low temperature oxide (LTO) as barrier layer 102, on barrier layer 102, form polysilicon layer 103;
2), polysilicon layer 103 is etched into isolated silicon island;
3), by LPCVD (low-pressure chemical vapor deposition) method, directly on polysilicon layer 103, deposit LTO gate insulation layer 201;
4), on gate insulation layer 201, deposit the low temperature polycrystalline silicon of 200nm, as grid layer 301;
5), at grid layer 301, apply the positive glue 401 of the photoetching for etching of 1 micron;
6), as shown in Fig. 4 a, adopt gray scale lay photoetching mask plate to expose, this gray scale lay photoetching mask plate comprises the transparent area 701 that is positioned at both sides, and be positioned at light tight district 702 alternately and the part transparent area 703 in the middle of transparent area 701, and make transparent area 701 adjacent with light tight district 702, the positive glue 401 of patterning photoetching is to form the gate mask with BG pattern 402 as shown in Figure 4 b, gate mask 402 has groove corresponding to 703 places, part transparent area, and the degree of depth of groove is less than the gross thickness of gate mask 402;
7), with gate mask 402 for stopping, device shown in Fig. 4 c is carried out to the Implantation of vertical direction, after Implantation as shown in the figure, formation source/drain region 104 and the active area that formed by doping BG line 105 and undoped polycrystalline silicon 106 intervals in polysilicon layer 103;
8), with gate mask 402 for stopping, etching grid layer 301, forms grid 302 rear removal photoresist 402;
9), utilize PECVD (plasma enhanced chemical vapor deposition) deposition oxide interlayer insulator, and in interlevel insulator, offer contact hole, sputtered aluminum-1% silicon is as source-drain electrode contact electrode;
10), sintering carry out dopant activation.
In the manufacture method that the present embodiment provides, because the doping of BG line and graphical grid are all used same photoresist 402 as stopping, solve the problem that grid is aimed at active channel, also saved photoetching process simultaneously.Mask plate transparent area 701 should be adjacent with non-transparent area 702, guaranteed that like this source-drain electrode can be not adjacent with the BG line that adulterates, be conducive to like this reduce the parasitic capacitance between source-drain electrode and grid, this Alignment Process makes the each TFT on panel have identical structure, has guaranteed the uniformity of TFT.
Embodiment 2
The present embodiment provides a kind of manufacture method of bridged-grain polycrystalline SiTFT, as shown in Fig. 4 a, 4b, 5a, 5b, comprising:
1), as shown in Fig. 4 a, in glass substrate 101, deposit one deck low temperature oxide (LTO) as barrier layer 102, on barrier layer 102, form polysilicon layer 103;
2), polysilicon layer 103 is etched into isolated silicon island;
3), by LPCVD (low-pressure chemical vapor deposition) method, directly on polysilicon layer 103, deposit LTO gate insulation layer 201;
4), on gate insulation layer 201, deposit the low temperature polycrystalline silicon of 200nm, as grid layer 301;
5), at grid layer 301, apply the positive glue 401 of the photoetching for etching of 1 micron;
6), as shown in Fig. 4 a, adopt gray scale lay photoetching mask plate to expose, this gray scale lay photoetching mask plate comprises and is positioned at the transparent area 701 of both sides and is positioned at light tight district 702 alternately and the part transparent area 703 in the middle of transparent area 701, and make transparent area 701 adjacent with light tight district 702, the positive glue 401 of patterning photoetching is to form the gate mask with BG pattern 402 as shown in Figure 4 b, gate mask 402 has groove corresponding to 703 places, part transparent area, and the degree of depth of groove is less than the gross thickness of gate mask 402;
7), as shown in Figure 5 a, with gate mask 402, for stopping, etching grid layer 301, forms grid 302;
8), as shown in Figure 5 b, with gate mask 402 for stopping, device shown in Fig. 5 b is carried out to the Implantation of vertical direction, after Implantation as shown in Figure 5 b, in polysilicon layer 103, formation source/drain region 104 and the active area that is comprised of doping BG line 105 and undoped polycrystalline silicon 106 intervals, then remove photoresist 402;
9), utilize PECVD (plasma enhanced chemical vapor deposition) deposition oxide interlayer insulator, and in interlevel insulator, offer contact hole, sputtered aluminum-1% silicon is as source-drain electrode contact electrode;
10), sintering carry out dopant activation.
Step in the basic step of the present embodiment and embodiment 1 is roughly the same, and its difference is that first etching forms grid, and then device is carried out to ion implantation doping.
In the manufacture method that the present embodiment provides, because the doping of BG line and graphical grid are all used same photoresist 402 as stopping, solve the problem that grid is aimed at active channel, also saved photoetching process simultaneously.Mask plate transparent area 701 should be adjacent with non-transparent area 702, guaranteed that like this source-drain electrode can be not adjacent with the BG line that adulterates, be conducive to like this reduce the parasitic capacitance between source-drain electrode and grid, this Alignment Process makes the each TFT on panel have identical structure, has guaranteed the uniformity of TFT.
Embodiment 3
The present embodiment provides a kind of manufacture method of bridged-grain polycrystalline SiTFT, as shown in Fig. 6 a-6c, comprising:
1), in glass substrate 101, deposit one deck low temperature oxide (LTO) as barrier layer 102, on barrier layer 102, form polysilicon layer 103;
2), polysilicon layer 103 is etched into isolated silicon island;
3), by LPCVD (low-pressure chemical vapor deposition) method, directly on polysilicon layer 103, deposit LTO gate insulation layer 201;
4), on gate insulation layer 201, deposit the low temperature polycrystalline silicon of 200nm, as grid layer 301;
5), at grid layer 301, apply the positive glue 401 of the photoetching for etching of 1 micron;
6), as shown in Figure 6 a, adopt lay photoetching mask plate to expose, this lay photoetching mask plate comprises in the full transparent area 701 of both sides and the non-transparent area 702 alternately between full transparent area 701, full transparent area 704, and guarantee that transparent area 701 is adjacent with light tight district 702, the positive glue 401 of patterning photoetching is to form the gate mask with BG pattern 403 as shown in Figure 6 b, gate mask 403 has groove corresponding to 703 places, full transparent area, and the degree of depth of groove equals the gross thickness of gate mask 403;
7), with gate mask 403 for stopping, etching grid layer 301, forms the grid 302 of multi-gate structure;
8), with gate mask 403 for stopping, device shown in Fig. 6 c is carried out to the Implantation of vertical direction, after Implantation as shown in Fig. 6 d, in polysilicon layer 103, formation source/drain region 104 and the active area that is comprised of doping BG line 105 and undoped polycrystalline silicon 106 intervals, then remove gate mask 403;
9), utilize PECVD (plasma enhanced chemical vapor deposition) deposition oxide interlayer insulator, and in interlevel insulator, offer contact hole, sputtered aluminum-1% silicon is as source-drain electrode contact electrode;
10), sintering carry out dopant activation.
In the manufacture method that the present embodiment provides, because the doping of BG line and graphical grid are all used same gate mask as stopping, solved the problem that grid is aimed at active channel, also saved photoetching process simultaneously, also can guarantee that source-drain electrode can be not adjacent with the BG line that adulterates, be conducive to like this reduce the parasitic capacitance between source-drain electrode and grid, this Alignment Process makes the each TFT on panel have identical structure, has guaranteed the uniformity of TFT.
In the present embodiment, also can be by step 7) and step 8) order exchange, first etching forms grid, and then device is carried out to ion implantation doping.
The present invention by forming BG pattern in gate mask, formation and the available same gate mask of BG doping of grid are formed, in other embodiments of the invention, the method that the formation method of the BG pattern in gate mask is not limited to provide in above-described embodiment, for example, can also form BG pattern with dimension nano processing methods such as laser interferance method, nano impression methods in gate mask.
According to one embodiment of present invention, also can adopt photoetching to bear glue in lithography step, those skilled in the art can easily expect adopting the lay photoetching mask plate matching with the negative glue of photoetching to carry out photoetching.
Finally it should be noted that, above embodiment is only in order to describe technical scheme of the present invention rather than this technical method is limited, the present invention can extend to other modification, variation, application and embodiment in application, and therefore thinks that all such modifications, variation, application, embodiment are in spirit of the present invention and teachings.
Claims (10)
1. a manufacture method for bridged-grain polycrystalline SiTFT, comprising:
1) on substrate, form polysilicon layer;
2) on polysilicon layer, form gate insulator, grid layer, photoresist;
3) adopt gray scale lay photoetching mask plate to expose to form gate mask to photoresist, this gray scale lay photoetching mask plate comprises light tight district alternately and the part transparent area in transparent area, both sides and between transparent area, and the transparent area of both sides is adjacent with light tight district, wherein in gate mask, the part corresponding to part transparent area forms groove, and the degree of depth of groove is less than the gross thickness of gate mask;
4) with gate mask for stopping, carry out etching to form grid, and carry out Implantation and form bridged-grain line and source/drain region with doping in polysilicon layer.
2. manufacture method according to claim 1, wherein step 4) in, first carry out etching to form grid, then carry out Implantation.
3. manufacture method according to claim 1, wherein step 4) in, first carry out Implantation, then carry out etching to form grid.
4. manufacture method according to claim 1, is wherein removed after development corresponding to the part of transparent area, both sides in photoresist.
5. manufacture method according to claim 1, wherein in polysilicon layer corresponding to the part of transparent area, both sides by ion implantation doping and formation source/drain region.
6. manufacture method according to claim 1, wherein in polysilicon layer, the part corresponding to part transparent area is formed bridged-grain line by ion implantation doping.
7. manufacture method according to claim 1, wherein in polysilicon layer corresponding to the part in light tight district not by ion implantation doping.
8. manufacture method according to claim 1, wherein the direction of Implantation is perpendicular to substrate.
9. manufacture method according to claim 3, wherein grid layer consists of low temperature polycrystalline silicon.
10. a bridged-grain polycrystalline SiTFT, utilizes manufacture method as claimed in claim 1 to make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110461842.3A CN103762166A (en) | 2011-12-31 | 2011-12-31 | Manufacturing method of precisely-aligned bridged-grain polysilicon thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110461842.3A CN103762166A (en) | 2011-12-31 | 2011-12-31 | Manufacturing method of precisely-aligned bridged-grain polysilicon thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103762166A true CN103762166A (en) | 2014-04-30 |
Family
ID=50529388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110461842.3A Pending CN103762166A (en) | 2011-12-31 | 2011-12-31 | Manufacturing method of precisely-aligned bridged-grain polysilicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103762166A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104438A (en) * | 1992-09-22 | 1994-04-15 | Casio Comput Co Ltd | Film transistor |
| CN1375735A (en) * | 2001-02-06 | 2002-10-23 | 株式会社日立制作所 | Display apparatus and its mfg. method |
| US20100171546A1 (en) * | 2007-06-22 | 2010-07-08 | The Hong Kong University Of Science And Technology | Polycrystalline silicon thin film transistors with bridged-grain structures |
-
2011
- 2011-12-31 CN CN201110461842.3A patent/CN103762166A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104438A (en) * | 1992-09-22 | 1994-04-15 | Casio Comput Co Ltd | Film transistor |
| CN1375735A (en) * | 2001-02-06 | 2002-10-23 | 株式会社日立制作所 | Display apparatus and its mfg. method |
| US20100171546A1 (en) * | 2007-06-22 | 2010-07-08 | The Hong Kong University Of Science And Technology | Polycrystalline silicon thin film transistors with bridged-grain structures |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8426865B2 (en) | Polycrystalline silicon thin film transistors with bridged-grain structures | |
| JP6896627B2 (en) | TFT array substrate, its manufacturing method, display device | |
| CN105390451B (en) | The preparation method of low temperature polycrystalline silicon TFT substrate | |
| CN105702623B (en) | The production method of tft array substrate | |
| CN104681628A (en) | Polycrystalline silicon thin film transistor, array substrate, manufacturing methods and display device | |
| US9324743B2 (en) | Flat panel display device with oxide thin film transistor and method of fabricating the same | |
| CN103839825A (en) | Low-temperature polycrystalline silicon thin film transistor, array substrate and manufacturing method of array substrate | |
| WO2018000478A1 (en) | Method of manufacturing thin film transistor and method of manufacturing array panel | |
| US10042211B2 (en) | Liquid crystal display panel, array substrate and manufacturing method thereof | |
| WO2017092172A1 (en) | Manufacturing method for tft substrate | |
| US11895870B2 (en) | Display panel and display device | |
| WO2017000335A1 (en) | Manufacturing method for and structure of tft back plate | |
| CN203480182U (en) | Array substrate and display device | |
| WO2020062426A1 (en) | Array substrate and preparation method therefor, and display device | |
| CN105655407A (en) | Polycrystalline silicon thin film transistor and preparation method thereof, array substrate and display device | |
| US10192903B2 (en) | Method for manufacturing TFT substrate | |
| CN109817644A (en) | A kind of tft array substrate and preparation method thereof | |
| CN109616479A (en) | The production method of LTPS TFT substrate | |
| CN106653695B (en) | A kind of low temperature polycrystalline silicon array substrate and preparation method thereof | |
| WO2018119865A1 (en) | Low-temperature polysilicon array substrate and manufacturing method thereof | |
| US11469329B2 (en) | Active switch, manufacturing method thereof and display device | |
| CN103762165A (en) | Simplified manufacturing method of bridged-grain polysilicon thin film transistor | |
| CN106847828B (en) | Low-temperature polycrystalline silicon array substrate and manufacturing method thereof | |
| WO2016165223A1 (en) | Polycrystalline silicon thin-film transistor, manufacturing method therefor, and display device | |
| CN103762169A (en) | Bottom gate thin film transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140430 |