CN103681232B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN103681232B CN103681232B CN201210324637.7A CN201210324637A CN103681232B CN 103681232 B CN103681232 B CN 103681232B CN 201210324637 A CN201210324637 A CN 201210324637A CN 103681232 B CN103681232 B CN 103681232B
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000011162 core material Substances 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 238000004070 electrodeposition Methods 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 11
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 32
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.The method comprises the following steps：Step S101：It is being formed with the figure of formation core-material in the Semiconductor substrate of film to be patterned；Step S102：Core-material is processed, so that core-material different surfaces have different electrodeposition substance rates；Step S103：Material spacer layer film is formed on the semiconductor substrate；Step S104：The material spacer layer film is etched to form the figure of wall；Step S105：Remove the core-material；Step S106：The film to be patterned is patterned；Step S107：Remove the wall.The method is improved double-pattern technology, the cutting etching technics after wall is formed in traditional double-pattern technology is eliminated, while technique, reduces cost is simplified, it is ensured that product yield.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
As semiconductor fabrication develops into 22 nanometer nodes and following, double-pattern technology（double
patterning）As in less and less critical size（CD）A lower very promising side for realizing more accurately figure
Method.
Traditional double-pattern technology is needed in wall（spacer）Cutting etching technics is carried out after formation（cutting
photo）, which results in process complication and to be aligned precision propose challenge.
Below, with reference to Figure 1A to Fig. 1 F, traditional method using double-pattern technology manufacture semiconductor devices is carried out
Explanation.Wherein, Figure 1A -1, Figure 1B -1, Fig. 1 C-1, Fig. 1 D-1, Fig. 1 E-1 and Fig. 1 F-1 are the pattern of formation after the completion of each technique
Front view；Figure 1A -2, Figure 1B -2, Fig. 1 C-2, Fig. 1 D-2, Fig. 1 E-2 and Fig. 1 F-2 are the pattern of formation after the completion of each technique
Top view.The method that traditional utilization double-pattern technology manufactures semiconductor devices, generally comprises the steps：
Step 1：Form the figure of core-material.
Specifically, there is provided form film to be patterned（film to pattern）101 Semiconductor substrate 100, to be patterned
Patterned core-material 102 is formed on film 101, as shown in Figure 1A.Wherein, core-material 102 is single layer structure.
Step 2：Form wall.
The surrounding of patterned core-material 102 in Semiconductor substrate 101, forms wall 103, the interval insulant
The tangent plane of layer 103 is rectangle, as shown in Figure 1B.
Step 3：Removal core-material.
By techniques such as etchings, core-material 102 is removed, the figure of formation is as shown in Figure 1 C.
Step 4：Cutting etching technics treatment is carried out to wall and forms final wall.
Cutting etching technics is carried out to wall 103（cutting photo）Treatment, removes two phases of wall 103
To side, form final wall 103 ', as shown in figure iD.
Step 5：Patterned thin is treated to be patterned.
By the use of final wall 103 ' as mask, treat patterned thin 101 and perform etching treatment, formed and intend what is realized
Final graphics 101 ', as referring to figure 1E.
Step 6：Removal wall 103 ', as shown in fig. 1F.
In the method, semi-conductor device manufacturing method of above-mentioned application double-pattern technology, needed to wall in step 4
（spacer）Carry out cutting etching technics（cutting photo）Treatment, this not only result in the complication of process, and
Precision to being aligned proposes challenge.The complication of technique, will increase the manufacturing cost of semiconductor devices；And if alignment precision
Not enough, the decline of product yield will be easily caused.
Therefore, how technique is simplified, product yield is ensured while reduces cost, into the urgent need to being solved
Problem.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：
Step S101：It is being formed with the figure of formation core-material in the Semiconductor substrate of film to be patterned；
Step S102：Core-material is processed, so that there are core-material different surfaces different materials to sink
Product rate；
Step S103：Material spacer layer film is formed on the semiconductor substrate；
Step S104：The material spacer layer film is etched to form the figure of wall；
Step S105：Remove the core-material；
Step S106：The film to be patterned is patterned；
Step S107：Remove the wall.
Further, the step S101 includes：
Offer is formed with the Semiconductor substrate of film to be patterned, and core material film is formed on the film to be patterned,
Treatment is performed etching to the core material film, the figure of core-material is formed.
Further, the core material film that formed on the film to be patterned includes：In the film to be patterned
On, successive sedimentation nitride film and sull.
Further, thickness of the thickness of the nitride film more than the sull.
Further, in step s 102, it is described treatment is carried out to core-material to include：From the two opposite sides in left and right
To carrying out fluorine injection treatment to the core-material.
Further, the material spacer layer film is HARP.
Further, the step S104 includes：
The material spacer layer film is carried out without pattern etching treatment, in the side of the left and right of the core-material two
Retain material spacer layer, form the figure of wall.
Further, the step S105 includes：
The Semiconductor substrate for completing step S104 is soaked into phosphoric acid, to remove core-material.
Further, the step S106 includes：
By the use of the wall as mask, treatment is performed etching to the film to be patterned, formed and intend the final of realization
Figure.
Further, the method that the etching processing is used is reactive ion etching.
The manufacture method of the semiconductor devices that the present invention is provided, is improved double-pattern technology, by core
Material layer carries out specially treated, realizes different sedimentation rates of the material spacer layer on the core-material not surface of homonymy, enters
And the cutting etching technics in eliminating traditional double-pattern technology after wall is formed（cutting photo）.The method
While technique, reduces cost is simplified, it is ensured that product yield.
Brief description of the drawings
Drawings below of the invention is in this as a part of the invention for understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining principle of the invention.
In accompanying drawing：
Figure 1A-Fig. 1 F are the schematic diagram of each step of manufacture method of semiconductor devices in the prior art；
Fig. 2A-Fig. 2 G are the schematic diagram of each step of manufacture method of semiconductor devices proposed by the present invention；
Fig. 3 is a kind of flow chart of the manufacture method of semiconductor devices proposed by the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Semiconductor devices manufacture method.Obviously, the technical staff that execution of the invention is not limited to semiconductor applications is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
It should be appreciated that when use in this manual term "comprising" and/or " including " when, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more other features, entirety,
Step, operation, element, component and/or combinations thereof.
Below, reference picture 2A- Fig. 2 G and Fig. 3 describe one example of manufacture method of semiconductor devices proposed by the present invention
The detailed step of property method.The method applies the improved double-pattern skill that to wall need not cut etching processing
Art, product yield is ensure that while technique, reduces cost is simplified.
Reference picture 2A- Fig. 2 G, each step that illustrated therein is the manufacture method of semiconductor devices proposed by the present invention is shown
Meaning property profile.Wherein, Fig. 2A -1, Fig. 2 B-1, Fig. 2 C-1, Fig. 2 D-1, Fig. 2 E-1, Fig. 2 F-1 and Fig. 2 G-1 are shape after each technique
Into figure front view；Fig. 2A -2, Fig. 2 B-2, Fig. 2 C-2, Fig. 2 D-2, Fig. 2 E-2, Fig. 2 F-2 and Fig. 2 G-2 are for after each technique
The top view of the figure of formation.
Step S101：It is being formed with the figure of formation core-material in the Semiconductor substrate of film to be patterned.
Specifically, there is provided be formed with film to be patterned（film to pattern）201 Semiconductor substrate 200, is treating structure
Patterned core-material 202 is formed on figure film 201, as shown in Figure 2 A（Wherein Fig. 2A -1 is front view, Fig. 2A -2 to bow
View）.
Wherein, in the present embodiment, core-material 202 is double-decker, including nitride layer 2021 and disposed thereon
Oxide skin(coating) 2022, as shown in Figure 2 A.Certainly, core-material 202 can also use single layer structure of the prior art.Using
Double-decker as described above, is more beneficial in subsequent technique realizing the different depositions of material spacer layer.In above-mentioned double-deck knot
In the core-material 202 of structure, it is preferred that thickness of the thickness of nitride layer 2021 more than oxide skin(coating) 2022.
In the present embodiment, the specific method for forming the figure of core-material 202 is：
Offer is formed with film to be patterned（film to pattern）201 Semiconductor substrate 200, in film to be patterned
（film to pattern）Successive sedimentation nitride film and sull on 201, perform etching treatment, form nitride
The figure of layer 2021 and oxide skin(coating) 2022 disposed thereon, wherein nitride layer 2021 and oxide skin(coating) 2022 constitute core
Material layer 202.Preferably, the thickness of nitride film is more than the thickness of sull, i.e. the thickness of nitride layer 2021 is big
In the thickness of oxide skin(coating) 2022.
As an example, in the present embodiment, the Semiconductor substrate is constituted from single crystal silicon material.In semiconductor lining
Isolation structure is formed with bottom, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation
Semiconductor substrate is divided into NMOS parts and PMOS parts by structure, the isolation structure.Also formed in the Semiconductor substrate 200
There is various traps (well) structure, to put it more simply, being omitted in diagram.Above-mentioned formation trap (well) structure, isolation structure, grid
The processing step of structure is familiar with by those skilled in the art, is no longer been described by detail herein.
Step S102：Core-material is processed, so that there are core-material different surfaces different materials to sink
Product rate.
In this step, it is necessary to process core-material 202, treatment or other ions note are such as injected using fluorine
Enter treatment etc., to cause that the different surfaces of core-material 202 have different electrodeposition substance rates（deposition rate）,
As shown in Figure 2 B（Wherein Fig. 2 B-1 are front view, Fig. 2 B-2 are top view）.In this manner it is possible to realize interval in subsequent technique
Different depositions of the layer material in core material layer surface diverse location.
After being processed, should ensure that core-material 202 needs to retain material spacer layer to be formed in subsequent technique
On that two relative surfaces of wall, electrodeposition substance rate is more than other surfaces.
Below, as a example by specifically being processed using fluorine injection, illustrate.
Fluorine injection treatment is carried out from left and right both direction to core-material 202, as shown in Figure 2 B, the side of the fluorine injection
There is an angle to the horizontal plane with the Semiconductor substrate 200, to ensure the same side energy to the core-material 202
Carry out fluorine injection treatment simultaneously.Wherein, left and right both direction, refers to need to retain material spacer layer in subsequent technique to be formed
That two relative directions of wall.By after fluorine treatment, core-material, will be with more on the surface processed by fluorine
Big electrodeposition substance rate.
Step S103：Material spacer layer film is formed on the semiconductor substrate.
Formed on a semiconductor substrate（Such as deposit）One interlayer interlayer material, forms an interlayer interlayer material film 203,
As shown in Figure 2 C（Wherein Fig. 2 C-1 are front view, Fig. 2 C-2 are top view）.Because abovementioned steps S202 is to core-material 202
Processed so that the surface of core-material 202 is provided with different electrodeposition substance rates, therefore, material spacer layer is in core
The deposition of material layer 202 is different, and then diverse location of the material spacer layer film 203 on the surface of core-material 202 is thick
Degree is different.As shown in Fig. 2 C-2, the material spacer layer film is high-aspect-ratio processing procedure（HARP）Film, in core-material 202
Thickness in the both direction of left and right is significantly greater than the thickness in two other direction.
Step S104：The material spacer layer film is etched to form the figure of wall.
Material spacer layer film 203 is etched comprehensively（blanket etch）, the figure of wall 203 ' is formed,
Interlayer material is retained only on the side of the left and right of core-material 202 two, i.e., wall 203 ' is only located at core-material
On 202 side of left and right two, as shown in Figure 2 D（Wherein Fig. 2 D-1 are front view, Fig. 2 D-2 are top view）.
Because fluorine injection treatment realizes different depositions of the material spacer layer on the surface of core-material 202, and then make
The material spacer layer film 203 of formation is in the both direction of left and right（I.e. on the side of the left and right of core-material 202 two）Thickness
Degree is significantly greater than two other direction, therefore, can realize that wall 203 ' is located only within a left side for core-material 202 after etching
On right two sides.That is, by foregoing series of steps, the interval layer pattern of formation, with cut in the prior art
Etching technics（cutting photo）Final wall after treatment（103 ' in Fig. 1 D）Shape it is identical.Therefore, originally
In inventive embodiments, it is convenient to omit carry out cutting etching technics to wall（cutting photo）The step for the treatment of.Simplify
Manufacturing process, reduces cost, while also further ensuring product yield.
Step S105：Remove the core-material.
By techniques such as wet etchings, core-material 202 is removed, the figure after treatment is as shown in Figure 2 E（Wherein Fig. 2 E-
1 is front view, Fig. 2 E-2 are top view）.Wherein, the specific method of core-material 202 is removed, can is to use phosphoric acid
（H3PO4）Immersion, i.e. the Semiconductor substrate 200 for completing step S104 is soaked into phosphoric acid, to remove core-material 202.
Step S106：The film to be patterned is patterned.
By the use of wall 203 ' as mask, treat patterned thin 201 and perform etching treatment, formed and intend the final of realization
Figure 201 ', as shown in Figure 2 F（Wherein Fig. 2 F-1 are front view, Fig. 2 F-2 are top view）.Wherein, the method for the etching processing,
Preferably reactive ion etching（RIE）.
Step S107：Remove the wall.
By techniques such as etching, strippings, wall 203 ' is removed, retain final pattern 203 ', as shown in Figure 2 G（Wherein scheme
2G-1 is front view, Fig. 2 G-2 are top view）.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed.The present invention is implemented
The manufacture method of the semiconductor devices of example, is really realized to a certain film layer using double-pattern technology（Film）It is patterned
Method, in can apply to the manufacturing process of various semiconductor devices, such as random access memory etc..
The manufacture method of the semiconductor devices of the embodiment of the present invention, relative to application double-pattern technology of the prior art
Method, eliminate carries out cutting etching technics to wall（cutting photo）The processing step for the treatment of, has simplified manufacture
Technique, reduces cost, while also further ensuring the yield of product.
Fig. 3 shows the flow chart of the manufacture method of semiconductor devices proposed by the present invention, for schematically illustrating whole system
Make the flow of technique.
In step S101, the figure of formation core-material in the Semiconductor substrate of film to be patterned is being formed with；
In step s 102, core-material is processed, so that core-material different surfaces have different things
Matter deposition；
In step s 103, material spacer layer film is formed on the semiconductor substrate；
In step S104, etch the material spacer layer film to form the figure of wall；
In step S105, the core-material is removed；
In step s 106, the film to be patterned is patterned；
In step s 107, the wall is removed.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching of the invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described comprises the following steps：
Step S101：It is being formed with the figure of formation core-material in the Semiconductor substrate of film to be patterned；
Step S102：Relative two side to the preboarding of core-material layer at interval is processed, so that by institute
State other sides of the electrodeposition substance rate on the side of the core-material after treatment more than the undressed core-material
Electrodeposition substance rate on face；
Step S103：Material spacer layer film is formed on the semiconductor substrate, wherein, the material spacer layer film is in institute
State core-material through the thickness on two sides after the treatment more than the unprocessed core-material other
Thickness on side；
Step S104：The material spacer layer film is etched to form the figure of wall, wherein, the wall is only located at institute
State core-material through on two sides after the treatment；
Step S105：Remove the core-material；
Step S106：The film to be patterned is patterned；
Step S107：Remove the wall.
2. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the step S101 includes：
Offer is formed with the Semiconductor substrate of film to be patterned, core material film is formed on the film to be patterned, to institute
State core material film and perform etching treatment, form the figure of core-material.
3. the manufacture method of semiconductor devices as claimed in claim 2, it is characterised in that described on the film to be patterned
Forming core material film includes：On the film to be patterned, successive sedimentation nitride film and sull.
4. the manufacture method of semiconductor devices as claimed in claim 3, it is characterised in that the thickness of the nitride film is big
In the thickness of the sull.
5. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that in step s 102, described to core
The heartwood bed of material carries out treatment to be included：Relative two side to the preboarding of core-material layer at interval is carried out at fluorine injection
Reason.
6. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the material spacer layer film is
HARP。
7. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the step S104 includes：
Comprehensive etching processing is carried out to the material spacer layer film, in the core-material through two after the treatment
Retain material spacer layer on side, form the figure of wall.
8. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the step S105 includes：
The Semiconductor substrate for completing step S104 is soaked into phosphoric acid, to remove core-material.
9. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the step S106 includes：
By the use of the wall as mask, treatment is performed etching to the film to be patterned, form the final figure for intending realizing
Shape.
10. the manufacture method of semiconductor devices as claimed in claim 9, it is characterised in that the side that the etching processing is used
Method is reactive ion etching.
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| CN101388328A (en) * | 2007-09-12 | 2009-03-18 | 海力士半导体有限公司 | Method for forming micropatterns in semiconductor device |
| CN102498543A (en) * | 2009-08-20 | 2012-06-13 | 瓦里安半导体设备公司 | Methods and system for patterning a substrate |
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| US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
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| CN102498543A (en) * | 2009-08-20 | 2012-06-13 | 瓦里安半导体设备公司 | Methods and system for patterning a substrate |
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