CN103594507A - 高击穿电压iii族氮化物器件 - Google Patents

高击穿电压iii族氮化物器件 Download PDF

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CN103594507A
CN103594507A CN201310350393.4A CN201310350393A CN103594507A CN 103594507 A CN103594507 A CN 103594507A CN 201310350393 A CN201310350393 A CN 201310350393A CN 103594507 A CN103594507 A CN 103594507A
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O.赫贝尔伦
C.奥斯特迈尔
G.普雷希特尔
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Infineon Technologies Austria AG
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Abstract

本发明涉及高击穿电压III族氮化物器件。一种半导体器件包括在衬底上具有复合半导体材料的半导体本体。复合半导体材料具有沟道区域。源极区域延伸到复合半导体材料。漏极区域也延伸到复合半导体材料并且通过沟道区域与源极区域间隔开。绝缘区域被掩埋在半导体器件的有源区域中的衬底和复合半导体材料之间的半导体本体中。有源区域包括器件的源极，漏极和沟道区域。绝缘区域在源极区域和漏极区域之间的沟道区域的长度上是不连续的。

Description

高击穿电压III族氮化物器件
技术领域
本申请涉及III族氮化物器件，并且更具体地涉及高击穿电压III族氮化物器件。
背景技术
由于氮化镓（GaN）的3.4eV的高能量带隙，基于氮化镓（GaN）的高电子迁移率晶体管（HEMT）很适合作为高击穿电压器件。这意味着较小器件长度可以经受住相对更大的阻断电压，导致较低导通电阻和电容。由于外延加工广泛用来制作多层HEMT结构，大多数的常规HEMT是具有可选插塞连接的横向源极-漏极器件，所述插塞连接延伸穿过III族氮化物外延叠层以便实现准垂直器件。这种结构的III族氮化物外延叠层的厚度必须经受住与源极-漏极延伸的横向阻断电压相同的阻断电压。
传统HEMT器件的电压等级可以通过变化外延厚度被调整。这种方法需要长的和昂贵的GaN层沉积，其在高温加工期间造成显著的晶片弯曲。因此，在任何后外延（post-epitaxial）加工中只能应用有限的温度预算，潜在地消除n+源极/漏极区域注入/活化的可能性。
可以去除在横向GaN HEMT下面的衬底以提高器件的击穿电压鲁棒性。然而，由于最终器件厚度只有几微米，对于大功率器件来说实现衬底的去除相当困难。另外，优选大体上平坦的器件背侧以提供与引线框的良好的热连接，所述引线框防止了在漂移区域下面使用深沟槽。
发明内容
根据此处描述的实施例，通过用绝缘区域替代部分外延层和/或下面的衬底，III族氮化物器件的外延厚度被减小，而不会不利地影响器件的击穿电压。
根据半导体器件的实施例，该半导体器件包括在衬底上包含复合半导体材料的半导体本体。复合半导体材料具有沟道区域。源极区域延伸到复合半导体材料。漏极区域也延伸到复合半导体材料并且通过沟道区域与源极区域间隔开。绝缘区域被掩埋在半导体器件的有源区域中的衬底和复合半导体材料之间的半导体本体中。有源区域包括半导体器件的源极，漏极和沟道区域。绝缘区域在源极区域和漏极区域之间的沟道区域的长度上是不连续的。
根据半导体器件的另一实施例，该半导体器件包括半导体衬底和生长在半导体衬底上的复合半导体外延材料。复合半导体外延材料具有沟道区域和比半导体衬底更高的能量带隙。第一掺杂区域延伸到复合半导体外延材料。第二掺杂区域也延伸到复合半导体外延材料并且通过沟道区域与第一掺杂区域间隔开。绝缘区域被设置在复合半导体外延材料和衬底之间的沟道区域下面，并且在与半导体衬底的主表面平行的方向上横向延伸。绝缘区域在第一和第二掺杂区域之间的沟道区域的长度上是不连续的。
根据制造半导体器件的方法的实施例，该方法包括：在衬底上形成包含复合半导体材料的半导体本体，复合半导体材料具有沟道区域；形成延伸到复合半导体材料的源极区域；形成延伸到复合半导体材料并且通过沟道区域与源极区域间隔开的漏极区域；以及形成掩埋在半导体器件的有源区域中的衬底和复合半导体材料之间的半导体本体中的绝缘区域，有源区域包括源极，漏极和沟道区域。绝缘区域在源极区域和漏极区域之间的沟道区域的长度上是不连续的。
在阅读下面的详细描述时，并且在阅览附图时，本领域技术人员将认识到另外的特征和优点。
附图说明
在附图中的部件不必要成比例，而是将重点放在说明本发明的原理上。而且，在附图中，相似的参考数字表示相应的部分。在附图中：
图1示出高击穿电压复合半导体器件的自顶向下的视图，其中在器件的不同部分中不同层被去除。
图2和3示出根据不同实施例的沿着标注为‘A-A’线的复合半导体器件的截面图。
图4示出根据实施例的沿着标注为‘B-B’线的复合半导体器件的截面图。
图5示出根据实施例的沿着标注为‘C-C’线的复合半导体器件的截面图。
图6示出高击穿电压复合半导体器件的另一实施例的截面图。
图7示出高击穿电压复合半导体器件的又一实施例的截面图。
图8A到8E示出在制造工艺的不同阶段期间半导体本体的截面图。
图9示出在不同制造工艺期间半导体本体的截面图。
具体实施方式
接下来描述的是例如异质结构场效应晶体管（HFET）的复合半导体器件的实施例，该异质结构场效应晶体管具有不会不利地影响器件的击穿电压的减小的外延厚度。术语HFET也通常被称作HEMT（高电子迁移率晶体管），MODFET（调制掺杂FET）或者MESFET（金属半导体场效应晶体管）。术语复合半导体器件，HFET，HEMT，MESFET和MODFET在此可互换地用来指代并入两种具有不同带隙的材料之间的结（即异质结）作为沟道的器件。例如，GaAs可以与AlGaAs结合，GaN可以与AlGaN结合，InGaAs可以与InAlAs结合，GaN可以与InGaN结合等。而且，晶体管可以具有AlInN/AIN/GaN阻挡/间隔/缓冲层结构。如此处使用的术语复合半导体器件还可以指代使用例如外延SiC的单个外延复合半导体外延制作的晶体管。
在每种情况下，通过用绝缘区域来代替部分外延（缩写为epi）和/或下面的衬底，在不会不利地影响器件的击穿电压的情况下，复合半导体器件的外延厚度被减小。这样做降低了器件的总成本，并且降低了由于可能由厚的外延引起的晶片弯曲而导致的高温工艺的复杂性。对于准垂直器件结构，可以使用高度导电的衬底，其通常将会需要相对较厚的外延层以便经受住与在横向设计中相同的阻断电压。这里描述的技术也最小化了由于使用例如氧化硅，氮化硅，金刚石等的低k材料（相对于外延的介电常数）而产生的寄生电容。
图1示出复合半导体器件的自顶向下的视图，其中在器件的不同部分中不同层被去除。图2和3示出沿着在图1中在半导体器件的有源区域100中标注为‘A-A’的线的半导体器件的替代实施例的截面图。图4示出沿着在图1中在半导体器件的有源区域100中标注为‘B-B’的线的半导体器件的截面图。图5示出沿着在图1中在半导体器件的无源区域102（例如器件边缘或者在器件的所谓的指状物（平行有源区域）之间）中标注为‘C-C’的线的半导体器件的截面图。
半导体器件包括包含复合半导体材料106（例如生长在衬底108上的外延（缩写为epi）层或者外延层的叠层）的半导体本体104。复合半导体材料在图2-5中被示作III族氮化物外延层的叠层，例如在一个或者多个过渡层110上的GaN缓冲层112和在GaN缓冲层112上的GaN合金阻挡层114，例如AlGaN，InAlN，AlN或者InAlGaN。然而，复合半导体材料106可以是例如SiC的单个外延层。在每种情况下，衬底108可以是掺杂的或者未掺杂的硅或者复合半导体晶片并且钝化层116可被提供在半导体本体104上。沟道区域118形成在复合半导体材料106中，例如对于GaN技术在与上覆的GaN合金阻挡层114的界面附近的GaN缓冲层112中。
利用GaN技术，极化电荷和应变效应的存在导致二维电荷运载气体的实现，其是以非常高的载流子密度和载流子迁移率为特征的二维电子或者空穴反型层。这样的二维电荷运载气体，例如2DEG（二维电子气）或者2DHG（二维空穴气），形成了器件的沟道区域118。薄的（例如1-2nm）AlN层可被提供在GaN缓冲层112和GaN合金阻挡层114之间以最小化合金散射并且增强2DEG迁移率。也可以使用具有二维电子气或者空穴气的其它复合半导体技术。在每种情况下，极化电荷导致器件的沟道区域118的形成。如在本领域中熟知的，可以使用III-V族半导体材料的其它组合以便在复合半导体材料106中形成2DEG或者2DHG沟道区域118。通常，在带不连续性是器件构思的原因的情况下，可以使用任何异质结构。例如，在AlGaAs系统的情况下没有压电效应，但是涉及布置用于限制沟道区域118的量子阱的限制构思是可能的。
复合半导体器件进一步包括延伸到在一端处与沟道区域118接触的复合半导体材料106的源极区域（S）。漏极区域（D）延伸到在另一端处与沟道区域118的接触的复合半导体材料106，并且通过沟道区域118与源极区域间隔开。源极和漏极可以由复合半导体材料106的掺杂限定的区域形成。栅极（G）被提供在复合半导体材料106上或者被提供在复合半导体材料106中，用于控制沟道区域118。
器件可以是横向器件，因为源极，漏极和栅极在半导体本体104的相同侧被接触（例如，如在图2中所示的），并且电流通常在源极和漏极之间沿横向方向流动。可替代地，器件可以是准垂直器件，因为源极和漏极在半导体本体的相对侧被接触并且电流部分地在源极和漏极之间沿横向方向流动且部分地在源极和漏极之间沿垂直方向流动。例如，如在图3中示出的，导电插塞120可以从漏极穿过复合半导体材料106延伸到衬底108的背离复合半导体材料106的一侧109。可替代地，导电插塞120可以被提供在源极侧。在每种情况下，如本领域中熟知的，器件可以是常开型或者常关型。
复合半导体器件还包括掩埋在器件100的有源区域中和/或在无源区域102中（有源区域包括源极，漏极和沟道区域118）的衬底108和复合半导体材料106之间的半导体本体104中的绝缘区域122。对于基于GaN的技术，如在图2-5中所示，绝缘区域122被设置在GaN合金阻挡层114的下面。通常，绝缘区域122被设置在沟道区域118的下面。绝缘区域122可被设置在器件的源极侧或者被设置在漏极侧，但不是从一侧连续地延伸到另一侧。也就是说，绝缘区域122在源极和漏极之间的沟道的长度（L_channel）上是不连续的。如此，对于例如如在图2中示出的绝缘区域122被部分地设置在复合半导体材料106中的实施例，复合半导体材料106在绝缘区域122上面较薄并且其它地方较厚。另外，如果绝缘区域122被完全地设置在下面的衬底108中（例如如在图6中示出的，其在本文后面被更详细地描述），复合半导体材料106可以在绝缘区域122上和其它地方具有相同的厚度。绝缘区域122在与半导体衬底108的主表面109平行的方向上横向延伸。
在每种情况下，通过用绝缘区域122代替部分复合半导体材料106和/或下面的衬底108，在没有不利地影响器件的击穿电压的情况下，复合半导体材料106的厚度可以被减小。与传统的具有相同外延厚度的器件相比，这样做提高了器件的击穿电压能力，或者提供了与具有更厚外延的传统器件相同的击穿电压能力。
在一个实施例中，绝缘区域122包括填充有绝缘材料126（例如氧化硅，氮化硅，金刚石，或者任何其它合适的具有比周围半导体材料的介电常数更低的介电常数的绝缘材料）的腔体124。腔体124具有由用来形成腔体124的蚀刻工艺确定的高度（h）。被设置在腔体124中的绝缘材料126可以是单个均匀结构或者包括不同材料的叠层。如在图2-5中所示，腔体124可以被部分地形成在复合半导体材料106中并且被部分地形成在衬底108中。可替代地，如在图6中所示，腔体124可以被完全地形成在复合半导体材料106下面的衬底108中。
在每种情况下，沟槽128可以被形成在器件的无源区域102中，其从复合半导体材料106的主表面107延伸到对应于将随后形成腔体124的顶部的地方的深度（d）。沟槽128被用来使用绝缘材料126来填充后面形成的腔体124以形成绝缘区域122，绝缘区域122被掩埋在器件的有源区域100中的衬底108和复合半导体材料106之间的半导体本体104中，如在图1和图5中示出的。这个沟槽128在绝缘区域122的长度（L）上垂直于源极和漏极延伸，使得腔体124可以用绝缘材料126完全填充。如在图1和4中示出的，也可在有源器件区域100中形成附加的沟槽130。根据这些实施例，沟槽128，130均具有足以共同地确保腔体124用绝缘材料126完全填充的宽度（w）。例如，至少在无源区域102中的沟槽128的宽度（w）可以是与下面的腔体124的填充高度（h）大约相同的宽度。因此，使用具有高达20的纵横比的标准LPCVD（低压化学汽相沉积）工艺的填充工艺可以在没有明显面积代价（area penalty）的情况下产生合理的腔体填充。
对于GaN技术，沟道128，130被用来通过干法和湿法蚀刻到沟道区域118下面来选择性地去除部分GaN合金阻挡层114和/或GaN缓冲层112。得到的腔体124可以被填充有由ALD（原子层沉积）或者LPCVD沉积的低k介电材料126，例如氧化硅，氮化硅，金刚石等。得到的绝缘区域122通过除了复合半导体材料106以外的其他材料减小了在源极和漏极之间的阻塞距离。绝缘区域122的厚度或者高度（h）可以被调整到器件的电压等级。相比于在没有绝缘区域122的情况下GaN缓冲层112的阻塞能力，在沟道区域118下面的蚀刻不足的最大深度取决于最大器件电压。另外，绝缘区域122的深度被保持在绝缘区域122下面的材料的稳定性限制。绝缘区域122减小了器件的源极到漏极电容和栅极到漏极电容并且因此改善了器件性能。
图7示出复合半导体器件的另一实施例的截面图，其中腔体124没有被完全地填充有绝缘材料126。根据这个实施例，在用来形成腔体124的器件有源区域100中的沟槽130并不是宽得足以确保腔体124被完全地填充有绝缘材料126（例如在ALD或者LPCVD期间）。而是，腔体用绝缘材料126加衬里并且腔体124上方的沟槽130填有绝缘材料126以封闭腔体124。腔体124的其余部分是中空的并且被填充有例如SF6的气体以完成绝缘区域122。根据该实施例，具有中空区域127的绝缘区域122具有甚至更低的介电常数k，进一步降低了衬底接触的寄生电容。如果形成电弧不是问题，可以使用空气而不是SF6来填充中空区域127。具有中空区域127的腔体124可以被部分地形成在复合半导体材料106中并且被部分地形成在衬底108中（如在图7中示出的），或者被完全地形成在复合半导体材料106下面的衬底108中。
对于被完全填充和被部分填充的腔体124两者，低k缓冲结构的实现可以使用在任何高温工艺（例如注入的Si活化和栅极氧化物致密化）之后加工和执行的标准硅技术。如果注入被用来在损伤注入物之后降低热预算，可以在任何缓冲隔离之前执行在腔体124中的绝缘材料126的沉积。
图8A至8E示出根据实施例的在不同工艺步骤期间的半导体本体104的截面图。图8A示出在沟槽200沿垂直于半导体本体104的第一主表面107的垂直方向被蚀刻到半导体本体104中之后的半导体本体104。根据该实施例，沟槽200通过复合半导体材料106延伸到衬底108。
图8B示出在沟槽侧壁的上部例如通过局部侧壁钝化202被保护起来之后的半导体本体106。局部侧壁钝化202在随后的蚀刻期间保护GaN缓冲层112的上部。可以通过氧化预沉积的硅层形成局部侧壁钝化202。可以在氧化工艺之前通过利用SiN填充沟槽200的下部来防止沟槽侧壁的下部氧化，SiN在氧化之后被去除。
图8C示出在蚀刻剂被设置在沟槽200中以在与半导体本体104的第一主表面107平行的横向方向上将腔体124的上部204蚀刻到半导体本体104中之后的半导体本体104。保护沟槽侧壁的上面钝化部分不受蚀刻剂影响，使得腔体124的上部204被形成在GaN缓冲层112中的沟槽侧壁的被保护部分和任何可能存在的过渡层110的下面。在使用热磷酸来蚀刻III族氮化物层的情况下，横向蚀刻速率比垂直蚀刻速率快得多，其将侵蚀层112。热磷酸不会侵蚀GaN缓冲层112的（垂直）c平面，允许III族氮化物缓冲蚀刻的精确控制。
图8D示出在腔体124的下部206被形成在衬底108中之后的半导体本体104。腔体124的下部206可以通过选择性地蚀刻衬底108被形成。复合半导体材料106可以由例如氧化硅或者氮化硅的稳定的钝化层保护。该步骤之后，衬底108可以被湿法化学蚀刻以实现最终的绝缘区域厚度或者高度（h）。该步骤也可以在没有上部GaN叠层112的先前选择性蚀刻的情况下被实现。根据该实施例，腔体124被部分地形成在复合半导体材料106中并且被部分地形成在衬底108中。
可替代地，如在图6中示出的，腔体124可以被完全地形成在衬底108中。在一个实施例中，腔体124可以通过形成穿过复合半导体材料106延伸到衬底108的沟槽200来被完全地形成在衬底108中。然后在沟槽200中设置蚀刻剂，蚀刻剂被选择成仅侵蚀衬底108，使得腔体124被完全地形成在衬底108中。在这种情况下，如果蚀刻溶液被选择成不侵蚀复合半导体材料106，则不需要沟槽侧壁的局部钝化。
图8E示出在腔体124被填充有绝缘材料126（例如氧化硅，氮化硅，金刚石等）之后的半导体本体104。绝缘材料126可以通过ALD或者LPCVD被沉积。可替代地，腔体124可以通过CVD金刚石处理被填充，其产生从GaN缓冲层112的更好的热传导和更高的击穿强度。在每种情况下，如本文前面描述的，为了使用绝缘材料126填充腔体124，在器件的无源区域102和/或在器件的有源区域100中形成沟槽200。例如，沟槽200在平行于源极和漏极延伸的绝缘区域122的长度上垂直于源极和漏极延伸。
如本文先前描述的，较小沟槽200替代地可被用来形成腔体124，其在整个腔体124被填充有绝缘材料126之前在绝缘材料126的沉积期间封闭。根据该替代实施例，腔体124用绝缘材料126加衬里并且中空区域127保持，其填充有气体，例如空气或者SF6，如本文前面描述的和在图7中示出的。在每种情况下，通过干法蚀刻和/或CMP（化学机械抛光）从钝化层116（如果存在的话）或半导体本体104的顶侧107去除绝缘材料126。
图9示出根据另一实施例的在不同工艺期间的半导体本体104的截面图。根据该实施例，从衬底108的背离复合半导体材料106的一侧109将用来在半导体本体104中形成腔体124的沟槽300蚀刻到衬底108中。形成在衬底108中的沟槽300的侧壁被钝化302，用以防御被设置在沟槽300中的蚀刻剂。蚀刻剂去除部分衬底108以完全地在衬底108中形成腔体124。如本文前面描述的，腔体124然后被部分地或者完全地填充有绝缘材料126，以在器件的源极或者漏极侧的衬底108和复合半导体材料106之间形成绝缘区域122。
空间相对术语例如“之下”，“下面”，“下部”，“上方”，“上部”等等，被用于方便描述以解释一个元件相对于第二元件的定位。除了与在附图中描述的那些取向不同的取向之外，这些术语旨在包括器件的不同取向。进一步地，例如“第一”，“第二”等等的术语也被用来描述不同的元件、区域、部分等并且也不旨在是限制性的。贯穿整个描述，相似术语指代相似元件。
如本文使用的，术语“具有”，“含有”，“包括”，“包含”等等是开放性的术语，其表明声称的元件或者特征的存在，但不排除另外的元件或者特征。冠词“一”，“一个”和“该”旨在包括复数以及单数，除非上下文明确地另外表明。
在记住上面的变化和应用范围的情况下，应该理解本发明不被前述描述限制，也不被附图限制。而是，本发明仅被下面的权利要求和其法律等价物限制。

Claims (26)

1.一种半导体器件，包括：
半导体本体，其包括在衬底上的复合半导体材料，所述复合半导体材料具有沟道区域；
源极区域，其延伸到所述复合半导体材料；
漏极区域，其延伸到所述复合半导体材料并且通过所述沟道区域与所述源极区域间隔开；和
绝缘区域，其掩埋在所述半导体器件的有源区域中的衬底和所述复合半导体材料之间的半导体本体中，所述有源区域包括所述源极，所述漏极和所述沟道区域，所述绝缘区域在所述源极区域和所述漏极区域之间的沟道区域的长度上是不连续的。
2.权利要求1的半导体器件，其中所述绝缘区域包括用绝缘材料加衬里的中空腔体。
3.权利要求2的半导体器件，其中所述中空腔体部分地形成在所述复合半导体材料中并且部分地形成在所述衬底中。
4.权利要求2的半导体器件，其中所述中空腔体完全形成在所述复合半导体材料下面的所述衬底中。
5.权利要求2的半导体器件，其中所述中空腔体被填充有气体。
6.权利要求1的半导体器件，其中所述绝缘区域包括被填充有绝缘材料的腔体。
7.权利要求6的半导体器件，其中所述腔体被部分地形成在所述复合半导体材料中并且被部分地形成在所述衬底中。
8.权利要求6的半导体器件，其中所述腔体被完全地形成在所述复合半导体材料下面的所述衬底中。
9.权利要求1的半导体器件，其中所述复合半导体材料包括在GaN层上的GaN合金层，所述沟道区域是设置在GaN层中接近与所述GaN合金层的界面的二维电子气，并且所述绝缘区域被设置在所述GaN合金层和所述二维电子气下面。
10.权利要求1的半导体器件，进一步包括：
从所述复合半导体材料的主表面延伸到所述有源区域外部的半导体本体的区域中的绝缘区域的沟槽；和
设置在所述沟槽中的绝缘材料。
11.权利要求10的半导体器件，其中所述沟槽在所述绝缘区域的长度上垂直于所述源极和所述漏极延伸。
12.权利要求1的半导体器件，进一步包括从所述漏极或者源极区域穿过所述复合半导体材料延伸到所述衬底的背离所述复合半导体材料的一侧的导电插塞。
13.一种半导体器件，包括：
半导体衬底；
复合半导体外延材料，其生长在所述半导体衬底上，所述复合半导体外延材料具有沟道区域和比所述半导体衬底更高的能量带隙；
第一掺杂区域，其延伸到所述复合半导体外延材料；
第二掺杂区域，其延伸到所述复合半导体外延材料并且通过所述沟道区域与所述第一掺杂区域间隔开；和
绝缘区域，其设置在所述复合半导体外延材料和所述衬底之间的沟道区域的下面，并且在与所述复合半导体外延材料的主表面平行的方向上横向延伸，所述绝缘区域在所述第一和第二掺杂区域之间的沟道区域的长度上是不连续的。
14.一种制作半导体器件的方法，包括：
在衬底上形成包括复合半导体材料的半导体本体，所述复合半导体材料具有沟道区域；
形成延伸到所述复合半导体材料的源极区域；
形成延伸到所述复合半导体材料并且通过所述沟道区域与所述源极区域间隔开的漏极区域；以及
形成掩埋在半导体器件的有源区域中的所述衬底和所述复合半导体材料之间的所述半导体本体中的绝缘区域，所述有源区域包括所述源极，所述漏极和所述沟道区域，所述绝缘区域在所述源极区域和所述漏极区域之间的沟道区域的长度上是不连续的。
15.权利要求14的方法，其中形成所述绝缘区域包括：
在所述沟道区域下面的半导体本体中形成腔体；并且
用绝缘材料给所述腔体加衬里，使得所述腔体具有中空区域。
16.权利要求15的方法，进一步包括用气体填充所述腔体的中空区域。
17.权利要求15的方法，其中在所述半导体本体中形成腔体并且用绝缘材料给所述腔体加衬里使得所述腔体具有中空区域包括：
将在垂直于所述半导体本体的第一主表面的垂直方向上延伸的沟槽蚀刻到所述半导体本体中，所述沟槽具有侧壁和底部；
在所述沟槽中设置蚀刻剂，以在平行于所述半导体本体的第一主表面的横向方向上蚀刻所述腔体到所述半导体本体中；以及
在所述腔体被完全填充有所述绝缘材料之前，用绝缘材料给所述腔体加衬里，其封闭所述沟槽。
18.权利要求15的方法，其中所述沟槽穿过所述复合半导体材料延伸到所述衬底，所述方法进一步包括保护沟槽侧壁的上部不受蚀刻剂影响，使得所述腔体在所述沟槽侧壁的被保护的上部下面被部分地形成在所述复合半导体材料中并且被部分地形成在所述衬底中。
19.权利要求15的方法，其中所述沟槽穿过所述复合半导体材料延伸到所述衬底并且所述蚀刻剂被选择成仅侵蚀所述衬底，使得所述腔体被完全地形成在所述复合半导体材料下面的衬底中。
20.权利要求14的方法，其中形成所述绝缘区域包括：
在所述沟道区域下面的半导体本体中形成腔体；以及
用绝缘材料填充所述腔体。
21.权利要求20的方法，其中在半导体本体中形成腔体和用绝缘材料填充所述腔体包括：
将在垂直于所述半导体本体的第一主表面的垂直方向上延伸的沟槽蚀刻到所述半导体本体中，所述沟槽具有侧壁和底部；
在所述沟槽中设置所述蚀刻剂，以在平行于所述半导体本体的第一主表面的横向方向上蚀刻所述腔体到所述半导体本体中；以及
在所述沟槽被所述绝缘材料封闭之前，用所述绝缘材料填充整个腔体。
22.权利要求21的方法，其中所述沟槽穿过所述复合半导体材料延伸到所述衬底，所述方法进一步包括保护沟槽侧壁的上部不受蚀刻剂影响，使得所述腔体在所述沟槽侧壁的被保护的上部下面被部分地形成在所述复合半导体材料中并且被部分地形成在所述衬底中。
23.权利要求21的方法，其中所述沟槽穿过所述复合半导体材料延伸到所述衬底并且所述蚀刻剂被选择成仅侵蚀所述衬底，使得所述腔体被完全地形成在所述复合半导体材料下面的衬底中。
24.权利要求14的方法，进一步包括：
形成从所述半导体本体的第一主表面延伸到所述有源区域外部的所述半导体本体的区域中的半导体本体中的沟槽；以及
用绝缘材料填充所述沟槽。
25.权利要求24的方法，其中形成所述沟槽包括在所述半导体本体中蚀刻所述沟槽，使得所述沟槽在所述绝缘区域的长度上垂直于所述源极和所述漏极延伸，所述绝缘区域的长度平行于所述源极和所述漏极延伸。
26.权利要求24的方法，其中所述沟槽从所述衬底的背离所述复合半导体材料的一侧被蚀刻到所述衬底中。
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