CN103579109A - Manufacturing method for photoelectric integrated circuit - Google Patents

Manufacturing method for photoelectric integrated circuit Download PDF

Info

Publication number
CN103579109A
CN103579109A CN201310534726.9A CN201310534726A CN103579109A CN 103579109 A CN103579109 A CN 103579109A CN 201310534726 A CN201310534726 A CN 201310534726A CN 103579109 A CN103579109 A CN 103579109A
Authority
CN
China
Prior art keywords
oxide layer
silicon chip
optoelectronic
manufacture method
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310534726.9A
Other languages
Chinese (zh)
Other versions
CN103579109B (en
Inventor
张有润
董梁
刘影
张飞翔
孙成春
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201310534726.9A priority Critical patent/CN103579109B/en
Publication of CN103579109A publication Critical patent/CN103579109A/en
Application granted granted Critical
Publication of CN103579109B publication Critical patent/CN103579109B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to the technology of semiconductors, in particular to a manufacturing method for a photoelectric integrated circuit. The manufacturing method mainly comprises the steps that a silicon wafer is processed, and a part of the silicon wafer is made to be provided with an oxide layer; the part, with the oxide layer, of the silicon wafer and the part, without the oxide layer, of the silicon wafer are isolated; photoelectric devices are manufactured on the part, without the oxide layer, of the silicon wafer, and electronic devices are manufactured on the oxide layer, wherein a longitudinal structure is adopted in the photoelectric devices, and an SOI technology is adopted by the electronic devices. The manufacturing method for the photoelectric integrated circuit has the advantages that a photoelectric diode and an integrated circuit module are integrated on the same chip, encapsulating difficulty and cost are reduced effectively, the parasitic effect is reduced, and reliability is improved. The manufacturing method for the photoelectric integrated circuit is especially suitable for the manufacturing of photoelectric integrated circuit.

Description

A kind of manufacture method of optoelectronic IC
Technical field
The present invention relates to semiconductor technology, relate to specifically a kind of manufacture method of optoelectronic IC.
Background technology
Optoelectronic IC (optoelectronic integrated circuit, OEIC), is that photoelectric device and electronic device are integrated, to realize the integrated circuit of certain specific function in optical communication system or optical information processing system.
Common optoelectronic IC is in the past all to adopt that to carry out monolithic integrated with the manufacture method of the silica-based process compatible of traditional standard, and such integration mode has reduced the assembling link in hybrid circuit, and its reliability and speed have also obtained obvious optimization.But, photoelectric device and the electric isolating effect between electronic device in this integration mode are poor, the photo-generated carrier that photoelectric device produces and the mutual interference of the meeting of the charge carrier in electronic device phase, in addition, common process also needs to consider the compatibling problem between photoelectric device and electronic device technique.And optoelectronic IC in this paper adopts single chip integrated local SOI technique to make, by techniques such as SIMOX or SDB, chip is isolated into SOI basic mode piece and conventional silicon substrate area, its integrated circuit modules utilizes standard SOI technique to be produced on SOI basic mode piece, and photoelectric device adopts vertical structure to be produced on conventional silicon substrate area, two modules are undertaken interconnected by metal.Adopt the optoelectronic IC of integration mode herein, the advantage separately of comprehensive photoelectric device and integrated circuit modules has reduced process compatible problem simultaneously effectively, realizes the optimization of performance.
Summary of the invention
To be solved by this invention, be exactly the technique integration problem for existing optoelectronic IC, the longitudinal photodetector and the integrated circuit modules that have proposed in a kind of optoelectronic IC adopt SOI technique to carry out single chip integrated method.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of manufacture method of optoelectronic IC, it is characterized in that, and comprise the following steps:
A. silicon chip is processed, made a part for silicon chip possess oxide layer;
B. silicon chip there are the part of oxide layer and the part of non-oxidation layer to isolate;
C. on silicon chip, the part of non-oxidation layer is manufactured photoelectric device, manufactures electronic device in oxide layer, and described photoelectric device is for adopting vertical structure, and electronic device adopts SOI technique.
Concrete, the concrete grammar of step a is:
A1. using silicon chip as Semiconductor substrate 301, on the epitaxial loayer 302 of Semiconductor substrate 301, mask plate 303 is set, carries out O +ion implanted, on surface, in the epitaxial loayer 302 of mask film covering version 303, do not form oxide layer 304;
A2. by heat treatment, oxide layer 304 is formed to insulating barrier 305;
A3. remove mask plate 303.
Further, the concrete grammar of step b is:
Adopt groove etchedly, etch a plurality of separators 306 on insulating barrier 305, described separator 306 is isolated into a plurality of parts by the epitaxial loayer on insulating barrier 305 302.
Concrete, the concrete grammar of step a is:
A1. will there be the silicon chip 401 of oxide layer and the silicon chip of non-oxidation layer 402 through being bonded to soi structure;
A2. by wet etching, remove a part for soi structure synthetic in step a1, be specially and remove the silicon chip 402 of part non-oxidation layer and the silicon chip that has oxide layer 401 being connected with this part, the removed part that has a silicon chip 401 of oxide layer comprises the oxide layer of this part;
A3. the structure growing epitaxial layers 403 obtaining in step a2;
A4. adopt glossing to be worked into required thickness the structure obtaining in step a3.
Further, the concrete grammar of step b is:
In the oxide layer of silicon chip 401 that has oxide layer, a plurality of separators are set, the silicon chip in oxide layer is isolated into a plurality of parts.
Further, describedly a plurality of separators are set for adopting to form trench isolations or to form the mode that V-type groove isolates by etching, isolate.
Beneficial effect of the present invention is, photodiode and integrated circuit modules are integrated on same chip, effectively reduced encapsulation difficulty and cost, reduced ghost effect, improved reliability.
Accompanying drawing explanation
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the schematic cross-section of embodiment 1;
Fig. 3 is mask film covering version 303 carry out the schematic diagram of O +ion implanted in the manufacturing process flow of embodiment 1;
Fig. 4 forms the schematic diagram of oxide layer 304 in the manufacturing process flow of embodiment 1;
Fig. 5 forms the schematic diagram of insulating barrier 305 in the manufacturing process flow of embodiment 1;
Fig. 6 removes the rear schematic diagram of mask plate 303 in the manufacturing process flow of embodiment 1;
Fig. 7 is etching separator 306 schematic diagrames in the manufacturing process flow of embodiment 1;
Fig. 8 is the silicon chip 401(N+ doping that will have oxide layer in the manufacturing process flow of embodiment 2) with the silicon chip 402 of non-oxidation layer through being bonded to the schematic diagram of soi structure;
Fig. 9 is that in the manufacturing process flow of embodiment 2, wet etching is removed the schematic diagram after the part of soi structure;
Figure 10 is schematic diagram after grown epitaxial layer in the manufacturing process flow of embodiment 2;
Figure 11 adopts glossing to be worked into the schematic diagram after required thickness in the manufacturing process flow of embodiment 2;
Figure 12 is by schematic diagram after trench isolations in the manufacturing process flow of embodiment 2;
Figure 13 is by schematic diagram after the isolation of V-type groove in the manufacturing process flow of embodiment 2.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The present invention, on the technique basis of general optoelectronic IC, has improved manufacture method, and photodiode and integrated circuit modules are integrated on same chip, has effectively reduced encapsulation difficulty and cost, has reduced ghost effect, has improved reliability.Compare with mainstream technology, the present invention has the following advantages: the integrated electro integrated circuit of employing, can effectively reduce encapsulation difficulty and cost, and reduce ghost effect, and improve reliability; The photodiode adopting is made into vertical structure, has effectively promoted the response speed of photodiode; The integrated circuit modules adopting is that SOI technique is made, and its parasitic capacitance is little, without latch-up, and can reduce the power consumption of circuit; The integration mode of the optoelectronic IC adopting, can realize optimization by the performance of photodiode and integrated circuit modules effectively.
Embodiment 1:
As shown in Figure 1, this example is optoelectronic IC, comprises two parts: photodiode and follow-up CMOS amplifying circuit.Wherein photodiode is a PIN pipe longitudinally, by the CMOS technique with SOI compatibility, is made, and follow-up CMOS amplifying circuit, is made and formed by SOI technique through specifically connecting to form by several NMOS pipes, PMOS pipe, resistance and electric capacity.
Wherein, photodiode 101, comprises the anode 102 of PIN pipe, be used for receiving illumination, metal connecting line 103, for connecing the metal connecting line of anode, is coated with one deck anti-reflecting layer 104 on anode 102, for promoting the quantum efficiency of diode, negative electrode is done overleaf, does not give demonstration in Fig. 1; In Fig. 1, CMOS amplifying circuit only shows two kinds of basic device architectures, wherein NMOS pipe 105 comprises source class 108, grid 109 and drains 110, PMOS manages 106 and comprises source class 111, grid 112 and drain 113, and all metal-oxide-semiconductors are all separated by SiO2107, and are made on one deck SiO2 insulating barrier.
As shown in Figure 2, cross-sectional illustration figure for this routine part of devices, wherein A-A ' section be in Fig. 1 photodiode along the cross-sectional view of A-A ', N+ substrate 201 is as the negative electrode of PIN pipe, N-epitaxial loayer 202 is the I layer in PIN pipe, P+ doped layer 204 is as the anode of PIN pipe, and metal electrode 203 and 206 is connected on respectively front and back; B-B ' section be along the cross-sectional view of CMOS amplifying circuit B-B ' section in Fig. 1, whole circuit is made on SiO2 insulating barrier 214, each device is isolated by one deck SiO2 shallow slot 207, NMOS pipe comprises that grid 209, source electrode 208 and 207, the PMOS pipe that drains comprise grid 212, source 211 and drain 213.
As shown in Fig. 3-Fig. 7, be this routine manufacturing process:
This example adopts SIMOX technique to make, and concrete steps are as follows:
1, the region that need to make photodiode at the epitaxial loayer 302 of masks 303 of Semiconductor substrate 301 covers, and carries out O +ion implanted, as shown in Figure 3;
2, after O +ion implanted, formed initial oxide layer 304, as shown in Figure 4;
3, after Overheating Treatment, form needed insulating barrier 305, as shown in Figure 5;
4, mask 303 is got rid of, as shown in Figure 6;
5, utilize groove etchedly, produce one deck separator 306 cmos circuit part and photodiode part are kept apart completely, also the device isolation in cmos circuit is come, as shown in Figure 7 simultaneously.
After local SOI technological process completes, just can carry out conventional longitudinal photodiode making and the making of cmos circuit.Concrete longitudinal photodiode is made, and has mentioned at publication number in the Chinese patent that is CN101069288A.
Embodiment 2:
As shown in Fig. 8-Figure 13, this example adopts Direct Bonding (SDB) fabrication techniques silicon chip substrate, and concrete steps are:
1. one side is had to the silicon chip 401(N+ doping of oxide layer) be bonded to soi structure with silicon chip 402 processes of non-oxidation layer, as shown in Figure 8;
2. by wet etching, remove silicon layer and the oxide layer in the region that need to make photodiode, as shown in Figure 9;
3. grown epitaxial layer 403, as shown in figure 10;
4. epitaxial loayer is adopted glossing to required thickness, as shown in figure 11;
5. adopt the mode of lateral isolation, photoelectric device region and integrated circuit zone isolation are left, the mode that can adopt has trench isolations (as shown in figure 12) and V-type groove isolation (as shown in figure 13).
Above manufacture craft and material should determine according to actual process environment.

Claims (6)

1. a manufacture method for optoelectronic IC, is characterized in that, comprises the following steps:
A. silicon chip is processed, made a part for silicon chip possess oxide layer;
B. silicon chip there are the part of oxide layer and the part of non-oxidation layer to isolate;
C. on silicon chip, the part of non-oxidation layer is manufactured photoelectric device, manufactures electronic device in oxide layer.
2. the manufacture method of a kind of optoelectronic IC according to claim 1, is characterized in that, the concrete grammar of step a is:
A1. using silicon chip as Semiconductor substrate (301), on the epitaxial loayer (302) of Semiconductor substrate (301), mask plate (303) is set, carry out O +ion implanted, on surface, in the epitaxial loayer (302) of mask film covering version (303), do not form oxide layer (304);
A2. by heat treatment, oxide layer (304) is formed to insulating barrier (305);
A3. remove mask plate (303).
3. the manufacture method of a kind of optoelectronic IC according to claim 2, is characterized in that, the concrete grammar of step b is:
Adopt groove etchedly, etch a plurality of separators (306) on insulating barrier (305), described separator (306) is isolated into a plurality of parts by the epitaxial loayer (302) on insulating barrier (305).
4. the manufacture method of a kind of optoelectronic IC according to claim 1, is characterized in that, the concrete grammar of step a is:
A1. will there be the silicon chip (401) of oxide layer and the silicon chip (402) of non-oxidation layer through being bonded to soi structure;
A2. by wet etching, remove a part for soi structure synthetic in step a1, be specially and remove the silicon chip (402) of part non-oxidation layer and the silicon chip that has oxide layer (401) being connected with this part, the removed part that has a silicon chip (401) of oxide layer comprises the oxide layer of this part;
A3. the structure growing epitaxial layers (403) obtaining in step a2;
A4. adopt glossing to be worked into required thickness the structure obtaining in step a3.
5. the manufacture method of a kind of optoelectronic IC according to claim 4, is characterized in that, the concrete grammar of step b is:
A plurality of separators are set in the oxide layer that has the silicon chip of oxide layer (401), the silicon chip in oxide layer is isolated into a plurality of parts.
6. the manufacture method of a kind of optoelectronic IC according to claim 5, is characterized in that, describedly a plurality of separators are set for adopting to be formed trench isolations or to be formed the mode that V-type groove isolates by etching, isolate.
CN201310534726.9A 2013-11-01 2013-11-01 A kind of manufacture method of integrated optoelectronic circuit Expired - Fee Related CN103579109B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310534726.9A CN103579109B (en) 2013-11-01 2013-11-01 A kind of manufacture method of integrated optoelectronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310534726.9A CN103579109B (en) 2013-11-01 2013-11-01 A kind of manufacture method of integrated optoelectronic circuit

Publications (2)

Publication Number Publication Date
CN103579109A true CN103579109A (en) 2014-02-12
CN103579109B CN103579109B (en) 2016-06-08

Family

ID=50050588

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310534726.9A Expired - Fee Related CN103579109B (en) 2013-11-01 2013-11-01 A kind of manufacture method of integrated optoelectronic circuit

Country Status (1)

Country Link
CN (1) CN103579109B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112510058A (en) * 2020-12-16 2021-03-16 中山大学 Integrated photoelectric sensor and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1564308A (en) * 2004-03-19 2005-01-12 中国科学院上海微系统与信息技术研究所 Upper silicon structure of insulation layer and its prepn. method
CN1748312A (en) * 2003-02-19 2006-03-15 信越半导体股份有限公司 Method for manufacturing soi wafer and soi wafer
US7338848B1 (en) * 2004-10-20 2008-03-04 Newport Fab, Llc Method for opto-electronic integration on a SOI substrate and related structure
CN101566705A (en) * 2009-06-12 2009-10-28 Nano科技(北京)有限公司 Optoelectronic integrated circuit and substrate preparation method
CN101996947A (en) * 2009-08-19 2011-03-30 中国科学院半导体研究所 Method for integrating silicon-based photoelectric device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1748312A (en) * 2003-02-19 2006-03-15 信越半导体股份有限公司 Method for manufacturing soi wafer and soi wafer
CN1564308A (en) * 2004-03-19 2005-01-12 中国科学院上海微系统与信息技术研究所 Upper silicon structure of insulation layer and its prepn. method
US7338848B1 (en) * 2004-10-20 2008-03-04 Newport Fab, Llc Method for opto-electronic integration on a SOI substrate and related structure
CN101566705A (en) * 2009-06-12 2009-10-28 Nano科技(北京)有限公司 Optoelectronic integrated circuit and substrate preparation method
CN101996947A (en) * 2009-08-19 2011-03-30 中国科学院半导体研究所 Method for integrating silicon-based photoelectric device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112510058A (en) * 2020-12-16 2021-03-16 中山大学 Integrated photoelectric sensor and preparation method thereof

Also Published As

Publication number Publication date
CN103579109B (en) 2016-06-08

Similar Documents

Publication Publication Date Title
US8906779B2 (en) Solar-powered energy-autonomous silicon-on-insulator device
TWI740769B (en) Optical sensor
US10153315B2 (en) Photosensitive imaging apparatus and method of forming same
US7622342B2 (en) Method of fabricating back-illuminated imaging sensors
US20130240962A1 (en) Photosensitive Imaging Device and Method for Forming Semiconductor Device
JP2016532319A (en) Alignment for metallization
CN102237377A (en) Monolithic integration of bypass diodes with a thin film solar module
US20180342543A1 (en) Backside illuminated cmos image sensor and method of fabricating the same
CN105261623A (en) Chip and preparation method thereof and image sensor including chip
CN106783903B (en) CMOS image sensor structure for preventing scribing from causing short circuit and manufacturing method
US20140048900A1 (en) Integrated circuit combination of a target integrated circuit, photovoltaic cells and light sensitive diodes connected to enable a self-sufficient light detector device
CN103489820B (en) A kind of method of device isolation
CN103779361B (en) Photodetector of spatial modulation structure and preparation method thereof
KR20100076511A (en) Method for manufacturing back side illumination image sensor
CN108666382B (en) SOI-based LSAMBM avalanche photodiode and preparation method thereof
CN105609513A (en) Double-surface CMOS image sensor chip and manufacture method thereof
CN111129053B (en) Pixel unit structure of CMOS image sensor and forming method
CN103579109B (en) A kind of manufacture method of integrated optoelectronic circuit
CN105633084A (en) CMOS device structure based on silicon-on-insulator substrate and preparation method thereof
CN103441132A (en) Method for preparing back-illuminated CMOS image sensor through low-temperature silicon wafer breaking
CN105895514A (en) Method of forming image sensor chip
CN109411496A (en) Semiconductor devices and forming method thereof
CN109524355A (en) A kind of structure and forming method of semiconductor devices
JPH01175775A (en) Photo-driven mos semiconductor device
WO2015067101A1 (en) Vertically configured photosensitive semiconductor device and method for fabrication thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160608

Termination date: 20181101

CF01 Termination of patent right due to non-payment of annual fee