CN103546408A - Modulating signal source - Google Patents

Modulating signal source Download PDF

Info

Publication number
CN103546408A
CN103546408A CN201310535574.4A CN201310535574A CN103546408A CN 103546408 A CN103546408 A CN 103546408A CN 201310535574 A CN201310535574 A CN 201310535574A CN 103546408 A CN103546408 A CN 103546408A
Authority
CN
China
Prior art keywords
dds
signal
source
frequency
output
Prior art date
Application number
CN201310535574.4A
Other languages
Chinese (zh)
Other versions
CN103546408B (en
Inventor
杨杰
孙敏
杨光
Original Assignee
四川九洲电器集团有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 四川九洲电器集团有限责任公司 filed Critical 四川九洲电器集团有限责任公司
Priority to CN201310535574.4A priority Critical patent/CN103546408B/en
Publication of CN103546408A publication Critical patent/CN103546408A/en
Application granted granted Critical
Publication of CN103546408B publication Critical patent/CN103546408B/en

Links

Abstract

The invention relates to the technical field of digital communication, and discloses a modulating signal source. The modulating signal source comprises two dot frequency sources, a DDS, two frequency mixers and an FPGA control circuit, wherein the output of the first dot frequency source is coupled to the DDS and the first frequency mixer, and serves as a reference clock signal of the DDS and a local oscillator signal of the first frequency mixer, and the output of the second dot frequency source is coupled to the second frequency mixer, and serves as a local oscillator signal of the second frequency mixer. The DDS and the FPGA control circuit carry out interaction, and an output signal inside the DDS serve as a clock signal of the FPGA control circuit. The first frequency mixer and the second frequency mixer are connected to the output end of the DDS in series, and are used for carrying out secondary frequency mixing on the output signal of the DDS. Compared with the prior art, according to the technical scheme, due to the fact that signals generated by the same device can be applied to a plurality of positions at the same time, the system structure can become simple, the module size is reduced, module cost is reduced, and quality of modulating signals is improved.

Description

Modulating signal source

Technical field

The present invention relates to digital communication technology field, particularly a kind of modulating signal source.

Background technology

MSK(Minimum Shift Keying, minimum shift keying) signal due to have constant-envelope, phase place continuously, frequency power density concentrates, reliability high, be widely used in microwave, shortwave and satellite communication.For MSK modulation signal, its bit rate is higher, and antijamming capability is also stronger, and the confidentiality of communication is better, and data throughput energy is also larger.

Traditional mode that realizes MSK modulation signal as shown in Figure 1, its signal source is to obtain after utilizing two paths of signals mixing stack, if realize by this way msk signal, a plurality of discrete Digital and analog devices will be used, this will certainly increase the volume of system, the debugging difficulty of raising system, and increase the development cost of system.And the scheme in Fig. 1 has adopted four mixting circuits to realize, and for mixting circuit, its local oscillator leakage and image frequency signal are very large on the impact of radiofrequency signal, this impact can be passed through filter filtering sometimes, sometimes it is very difficult that very difficult filtering, so this scheme implements.

Although also have now two kinds of other modes to realize msk signal: a kind of is the feature of utilizing DDS, with FPGA(or single-chip microcomputer) control DDS and directly produce msk signal; The second is the partial function that utilizes FPGA analog D DS, after signal is exported by FPGA, through D/A conversion, produces msk signal.But these two kinds of modes still exist a lot of shortcomings, such as output frequency is generally below 100MHz, can not realize L-band and with the radio frequency output of upper frequency; And according to disclosed document, record, the MSK modulation signal of realizing in these two kinds of modes, its bit rate is lower, all below 1Mb/s.

Summary of the invention

For the above-mentioned defect of prior art, technical problem to be solved by this invention is as the MSK modulation signal of the simple high bit rate of constitution realization, high signal quality how.

For solving the problems of the technologies described above, the invention provides a kind of modulating signal source, described modulating signal source comprises: two points are source, DDS, two frequency mixers and FPGA control circuit frequently, wherein,

First output in source frequently couples described DDS and the first frequency mixer simultaneously, simultaneously as the reference clock signal of described DDS and the local oscillation signal of described the first frequency mixer;

The second point frequently output in source couples the second frequency mixer, as the local oscillation signal of described the second frequency mixer;

Described DDS and described FPGA control circuit are mutual, using the output signal of described DDS inside as the clock signal of described FPGA control circuit;

Described the first frequency mixer and described the second frequency mixer are serially connected with the output of described DDS, and the output signal of described DDS is carried out to secondary mixing.

Preferably, the output signal of described DDS is MSK modulation signal.

Preferably, described two frequency mixers also carry out filtering to the output signal of described DDS simultaneously.

Preferably, initialize signal end and the same crystal oscillator in source couple described two points frequently.

Preferably, the output frequency in described two somes frequency source is specified by described FPGA control circuit.

Preferably, described FPGA control circuit provides msk signal control code for described DDS.

Preferably, described first output in source frequently couples described DDS and described the first frequency mixer by a power splitter simultaneously.

Preferably, the clock signal of described FPGA control circuit is to be exported by 4 frequency dividers of described DDS inside.

Preferably, after described secondary mixing, signal frequency is more than L-band.

Preferably, after described secondary mixing, the bit rate of signal is 16Mb/s.

Compared with prior art, the signal that technical scheme of the present invention produces same device is applied to many places simultaneously, System Construction is become simply, thereby reduce module volume, has lowered module cost, and has improved modulation signal quality.

Accompanying drawing explanation

Fig. 1 is the structural representation of MSK modulating signal source in prior art;

Fig. 2 is the structural representation of the modulating signal source described in one embodiment of the present of invention;

Fig. 3 exports a comparatively spectrogram for the MSK modulation signal of standard in the preferred embodiments of the present invention;

Fig. 4 is the signal quality schematic diagram of the MSK modulation signal in Fig. 3.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is for implementing better embodiment of the present invention, and described description is to illustrate that rule of the present invention is object, not in order to limit scope of the present invention.Protection scope of the present invention should with claim the person of being defined be as the criterion, the embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work, belongs to the scope of protection of the invention.

Traditional MSK modulating signal source is because the device adopting is too much, and the signal between each device influences each other, and is difficult to obtain bit rate and the higher MSK modulation signal of quality.This situation is more obviously when signal frequency is higher, and will suppress spuious, and system and hardware cost are had again to higher requirement.In embodiments of the invention, in order to realize better spuious inhibition index, reduce the design difficulty of radio-frequency (RF) output end filter, adopt secondary mixing scheme, the signal that same device is produced is applied to many places simultaneously, when having reduced number of devices, reduce disturbing mutually between unlike signal as far as possible, thereby realized the MSK modulation signal of high bit rate, high signal quality.

In one embodiment of the invention, as shown in Figure 2, modulating signal source comprises two somes sources, DDS, two frequency mixers and FPGA control circuit frequently, wherein, first output in source frequently couples DDS and the first frequency mixer simultaneously, simultaneously as the reference clock signal of DDS and the local oscillation signal of the first frequency mixer; The second point frequently output in source couples the second frequency mixer, as the local oscillation signal of the second frequency mixer; DDS and FPGA control circuit are mutual, using the output signal of DDS inside as the clock signal of FPGA control circuit; The first frequency mixer and the second frequency mixer are serially connected with the output of DDS, and the output signal of DDS is carried out to secondary mixing.Preferably, two frequency mixers also carry out filtering to the output signal of DDS simultaneously.

In the embodiment shown in Figure 2, preferably, the initialize signal in two some frequency sources is provided by same crystal oscillator, thereby further reduces the impact between number of devices and signal.In addition, the output frequency in two some frequency sources also can be specified by FPGA control circuit; FPGA control circuit is also simultaneously for DDS provides msk signal control code.More preferably, first output in source frequently couples DDS and the first frequency mixer by a power splitter simultaneously.In addition, the clock signal of FPGA control circuit is to be exported by 4 frequency dividers of DDS inside.

Rational source output frequency frequently only need be set, and embodiments of the invention can be realized L-band with the MSK modulation signal output of upper frequency, can significantly promote the bit rate of output signal.With further reference to Fig. 3,4, in Fig. 3, can see and in the preferred embodiments of the present invention, export a comparatively spectrogram for the MSK modulation signal of standard, its centre frequency is 1090MHz, and the spike on both sides is respectively 1086MHz and 1094MHz, has realized the bit rate of 16Mb/s.In Fig. 4, can see the signal quality of this MSK modulation signal, the root-mean-square value of its EVM is 2.3%, and frequency error is 345Hz.From Fig. 3 and Fig. 4, can find out, utilize the MSK modulating signal source of technical scheme realization of the present invention, realize the high-quality MSK modulation signal of L-band, its bit rate has reached 16Mb/s.

Compared with prior art, the signal that technical scheme of the present invention produces same device is applied to many places simultaneously, makes System Construction become simple, thereby reduce module volume, lower module cost, and realized the synchronous of DDS and FPGA system clock, improved modulation signal quality.Technical scheme of the present invention can effectively realize L-band with the output of upper frequency, and bit rate reached 16Mb/s, is applicable to applying in various radar systems and communication system, and can be effective to secure communication.

Above-mentioned explanation illustrates and has described some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to disclosed form herein, should not regard the eliminating to other embodiment as, and can be used for various other combinations, modification and environment, and can, in invention contemplated scope described herein, by technology or the knowledge of above-mentioned instruction or association area, change.And the change that those skilled in the art carry out and variation do not depart from the spirit and scope of the present invention, all should be in the protection range of claims of the present invention.

Claims (10)

1. a modulating signal source, is characterized in that, described modulating signal source comprises: two points are source, DDS, two frequency mixers and FPGA control circuit frequently, wherein,
First output in source frequently couples described DDS and the first frequency mixer simultaneously, simultaneously as the reference clock signal of described DDS and the local oscillation signal of described the first frequency mixer;
The second point frequently output in source couples the second frequency mixer, as the local oscillation signal of described the second frequency mixer;
Described DDS and described FPGA control circuit are mutual, using the output signal of described DDS inside as the clock signal of described FPGA control circuit;
Described the first frequency mixer and described the second frequency mixer are serially connected with the output of described DDS, and the output signal of described DDS is carried out to secondary mixing.
2. modulating signal source as claimed in claim 1, is characterized in that, the output signal of described DDS is MSK modulation signal.
3. modulating signal source as claimed in claim 1, is characterized in that, described two frequency mixers also carry out filtering to the output signal of described DDS simultaneously.
4. modulating signal source as claimed in claim 1, is characterized in that, described two points frequently initialize signal end and the same crystal oscillator in source couple.
5. modulating signal source as claimed in claim 1, is characterized in that, described two points frequently output frequency in source are specified by described FPGA control circuit.
6. modulating signal source as claimed in claim 2, is characterized in that, described FPGA control circuit provides msk signal control code for described DDS.
7. modulating signal source as claimed in claim 1, is characterized in that, described first output in source frequently couples described DDS and described the first frequency mixer by a power splitter simultaneously.
8. modulating signal source as claimed in claim 1, is characterized in that, the clock signal of described FPGA control circuit is to be exported by 4 frequency dividers of described DDS inside.
9. modulating signal source as claimed in claim 2, is characterized in that, after described secondary mixing, signal frequency is more than L-band.
10. modulating signal source as claimed in claim 2, is characterized in that, after described secondary mixing, the bit rate of signal is 16Mb/s.
CN201310535574.4A 2013-11-01 2013-11-01 Modulating signal source CN103546408B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310535574.4A CN103546408B (en) 2013-11-01 2013-11-01 Modulating signal source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310535574.4A CN103546408B (en) 2013-11-01 2013-11-01 Modulating signal source

Publications (2)

Publication Number Publication Date
CN103546408A true CN103546408A (en) 2014-01-29
CN103546408B CN103546408B (en) 2017-01-11

Family

ID=49969469

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310535574.4A CN103546408B (en) 2013-11-01 2013-11-01 Modulating signal source

Country Status (1)

Country Link
CN (1) CN103546408B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104300978A (en) * 2014-10-13 2015-01-21 西安电子工程研究所 Linearity controllable chirp signal generating method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060020865A1 (en) * 2004-07-22 2006-01-26 Fa Dai Automatic analog test & compensation with built-in pattern generator & analyzer
CN101089653A (en) * 2007-07-20 2007-12-19 西安理工大学 Short-range frequency-modulation continuous wave FMCW radar anti-interference method
US20100054357A1 (en) * 2007-03-06 2010-03-04 Mitsubishi Electric Corporation Radio communication system
CN102386894A (en) * 2011-09-28 2012-03-21 中国人民解放军63963部队 Vector signal source plug-in card-type structural module based on PCI extension for instrumentation (PXI) bus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060020865A1 (en) * 2004-07-22 2006-01-26 Fa Dai Automatic analog test & compensation with built-in pattern generator & analyzer
US20100054357A1 (en) * 2007-03-06 2010-03-04 Mitsubishi Electric Corporation Radio communication system
CN101089653A (en) * 2007-07-20 2007-12-19 西安理工大学 Short-range frequency-modulation continuous wave FMCW radar anti-interference method
CN102386894A (en) * 2011-09-28 2012-03-21 中国人民解放军63963部队 Vector signal source plug-in card-type structural module based on PCI extension for instrumentation (PXI) bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104300978A (en) * 2014-10-13 2015-01-21 西安电子工程研究所 Linearity controllable chirp signal generating method

Also Published As

Publication number Publication date
CN103546408B (en) 2017-01-11

Similar Documents

Publication Publication Date Title
US8891681B2 (en) Transmitters and methods
Razavi RF transmitter architectures and circuits
US9692443B2 (en) Circuit and method
US6915117B2 (en) Multistage modulation architecture and method in a radio
US6985701B2 (en) Frequency synthesizer and multi-band radio apparatus using said frequency synthesizer
KR100954707B1 (en) Transceiver using a harmonic rejection mixer
CN101268622B (en) Method and apparatus for frequency synthesis in direct-conversion transmitters
CN101331678B (en) Switching circuit, and a modulator, demodulator or mixer including such a circuit, its operation method
ES2528820T3 (en) Method and apparatus for modulation
JP6591611B2 (en) Radio frequency receiver and reception method
Razavi A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications
CN102710316B (en) All-digital satellite signal simulated source
CN104734787A (en) Waveform calibration using built in self test mechanism
CN104604124A (en) Receiver and transceiver architectures and methods for demodulating and transmitting phase shift keying signals
KR101392323B1 (en) Ook modulator and wireless communication transceiver including the same
CN102780483B (en) With the radio frequency digital to analog converter of configurable digital to analog converter mixer interface and configurable mixer
US8385475B2 (en) Calibration-free local oscillator signal generation for a harmonic-rejection mixer
JP2004088784A (en) Differential cmos latch and digital quadrature lo generator using latch
CN1819471A (en) Emission/acceptance device of polarization modulator with alterable predistortion
US8260279B2 (en) System, method and apparatus for providing communications that conform to a cellular communication standard and a non-cellular communication standard
CN105141560B (en) A kind of multi-standard signal imitation device and method
US20080003954A1 (en) Signal Generator, and Transmitter, Receiver and Transceiver Using Same
CN102754332B (en) Down-conversion using square wave local oscillator signals
CN102724162B (en) Multi-channel nuclear magnetic resonance radio frequency signal transmitter
US20120007638A1 (en) System and method for multiple-phase clock generation

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant