CN103545306A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN103545306A CN103545306A CN201210241828.7A CN201210241828A CN103545306A CN 103545306 A CN103545306 A CN 103545306A CN 201210241828 A CN201210241828 A CN 201210241828A CN 103545306 A CN103545306 A CN 103545306A
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- nmos pass
- pass transistor
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Abstract
An electrostatic discharge protection circuit comprises an electrostatic discharge input terminal, a ground terminal and a plurality of electrostatic discharge protection units. The electrostatic discharge protection units are located between the electrostatic discharge input terminal and the ground terminal. The electrostatic discharge protection units are arranged in parallel, each electrostatic discharge protection unit comprises an NMOS (N-channel metal oxide semiconductor) transistor, a capacitor, a first resistor and a second resistor, one end of the capacitor is connected with the electrostatic discharge input terminal, a second end of the capacitor is connected with a first end of the second resistor and a gate of the NMOS transistor, a first end of the first resistor is connected with the electrostatic discharge input terminal, a second end of the second resistor is connected with a second end of the first resistor and a drain electrode of the NMOS transistor, and a source electrode and a substrate of the NMOS transistor are connected with the ground terminal. By utilizing of the capacitor and the second resistor, a gate voltage of the NMOS resistor is enabled to be more than 0V, a trigger voltage of the NMOS transistor is beneficially lowered, and conduction uniformity of the electrostatic discharge protection circuit can be improved.
Description
Technical field
The present invention relates to integrated circuit ESD Circuits Design for High field, relate in particular to preferably ESD protection circuit of a kind of conducting homogeneity.
Background technology
Along with the utilization of semiconductor chip is more and more extensive, the involved electrostatic damage of semiconductor chip is also more and more extensive.Conventionally the static electricity on human body who wears nylon products may reach the high pressure of 21000V; the static discharge of 750V left and right can produce spark; and only the electrostatic potential of 10V left and right just may be damaged the chip that there is no static discharge (electrostatic discharge, ESD) protection.There are now design and the application of a variety of ESD protection circuits; generally include: the n type field effect transistor of grid ground connection (Gate Grounded NMOS; GGNMOS) protective circuit, protective circuit of diode, controllable silicon (Silicon Controlled Rectifier, SCR) protective circuit etc.
Wherein, the n type field effect transistor of grid ground connection (Gate Grounded NMOS, GGNMOS) circuit diagram of protective circuit as shown in Figure 1, the n type field effect transistor 10 of described a plurality of grid ground connection between external circuit 11 and chip internal circuit 12 and the drain region of the n type field effect transistor 10 of described grid ground connection be connected with chip internal circuit 12 with external circuit 11 respectively, the electrostatic induced current that external circuit 11 produces flows to ground by the n type field effect transistor 10 of described grid ground connection, the electrostatic potential of external circuit 11 is lower, the voltage that can not make described chip internal circuit 12 be subject to is too high, described chip internal circuit 12 can not damaged by high voltage.
The structure of the n type field effect transistor of described grid ground connection as shown in Figure 2, because described transistor is n type field effect transistor, the 22, drain region, source region 21 of the n type field effect transistor of described grid ground connection is N-type, described substrate 20 is P type, described drain region 21, substrate 20, source region 22 form a parasitic NPN triode 24, described source region 22 is the emitter of parasitic triode 24, described drain region 21 is the collector electrode of parasitic triode 24, described substrate 20 is the base of parasitic triode 24, wherein, described source region 22, substrate 20, grid 23 ground connection.Because the electrostatic potential of external circuit constantly rises the drain voltage of the n type field effect transistor of described grid ground connection, when described drain voltage is during higher than the puncture voltage of drain region 21, substrate 20 PN junction between the two, from drain region, 21 will produce a larger breakdown current to substrate 20.Due to described substrate 20 ground connection, described breakdown current also will flow to ground, but because the substrate from edge, drain region has part dead resistance 25 to the substrate of ground connection, described breakdown current flows through and can produce electrical potential difference in this dead resistance 25, make source region 22 and substrate 20 have electrical potential difference near the part of source-drain area, thereby the formed NPN triode 24 in source region 22, substrate 20, drain region 21 is opened, formed drain current, the electrostatic charge of the accumulation in drain region 21 22 is flowed away from source region.And triode has electric current amplification, can improve the relieving capacity of drain current, thereby drain voltage can be declined soon, protection chip internal circuit is not damaged by electrostatic potential.More physical circuits about anti-electrostatic protecting structure please refer to the american documentation literature that the patent No. is US7288820B2.
Because electrostatic induced current is conventionally very large, in prior art, conventionally a plurality of ggnmos transistors are connected in parallel as ESD protection circuit to improve electrostatic discharge capacity.But in existing ESD protection circuit, the conducting homogeneity of a plurality of ggnmos transistors is poor; conventionally all ggnmos transistors conducting simultaneously; after part conducting wherein; other be just not easy conducting; can have a strong impact on the ability of ESD protection circuit; if only have part ggnmos transistor to be switched on, conducting ggnmos transistor just cannot not play a protective role so, has lowered the ability of electrostatic protection.
Summary of the invention
The problem that the present invention solves is to provide a kind of ESD protection circuit, can effectively improve the conducting homogeneity of each MOS transistor of ESD protection circuit.
For addressing the above problem, technical solution of the present invention provides a kind of ESD protection circuit, comprise: static discharge input, earth terminal, be positioned at described static discharge input, some electrostatic discharge (ESD) protections unit between earth terminal, described electrostatic discharge (ESD) protection unit is arranged in parallel, and described electrostatic discharge (ESD) protection unit comprises nmos pass transistor, electric capacity, the first resistance, the second resistance, the first end of described electric capacity is connected with static discharge input, the second end of described electric capacity and the first end of the second resistance, the grid of nmos pass transistor is connected, the first end of described the first resistance is connected with static discharge input, the second end of described the second resistance and the second end of described the first resistance, the drain electrode of nmos pass transistor is connected, the source electrode of described nmos pass transistor is connected with earth terminal with substrate.
Optionally, the voltage that is applied to the grid of described nmos pass transistor is greater than 0V, is less than the threshold voltage of nmos pass transistor.
Optionally, the scope of voltage that is applied to the grid of described nmos pass transistor is 0V ~ 0.5V.
Optionally, the trigger voltage of described nmos pass transistor is less than the second puncture voltage.
Optionally, described the first resistance is the interconnection line dead resistance between nmos pass transistor and static discharge input.
Optionally, described each electrostatic discharge (ESD) protection unit is identical.
Optionally, described ESD protection circuit, between input/output interface and chip internal circuit, is connected with input/output interface, chip internal circuit by described static discharge input.
Optionally, the scope of the resistance value of described the second resistance is 1 ohm ~ 100 ohm.
Optionally, the substrate of described nmos pass transistor has dead resistance, and the dead resistance of the substrate of different N MOS transistor is different.
Compared with prior art, the present invention has the following advantages:
In the described ESD protection circuit of the embodiment of the present invention; the drain electrode of nmos pass transistor is connected with static discharge input with the RC circuit that the second resistance forms by the electric capacity of series connection, and is connected between the grid of described nmos pass transistor and electric capacity, the second resistance.When static discharge input is subject to static discharge, described electrostatic potential can trigger RC oscillating circuit, the voltage that coupling produces is to the grid of described nmos pass transistor, make the grid voltage of described nmos pass transistor be greater than 0V, and the grid voltage ground connection of ggnmos transistor of the prior art, be conducive to reduce the trigger voltage of described nmos pass transistor, described NMOS is more easily switched on, improved the conducting homogeneity of described NMOS.Simultaneously by controlling the size of the first resistance and the second resistance; make the grid voltage of described nmos pass transistor be less than the threshold voltage of described nmos pass transistor; make described nmos pass transistor successfully to carry out electrostatic discharge (ESD) protection, can improve again the conducting homogeneity of ESD protection circuit.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of n type field effect transistor protective circuit of the grid ground connection of prior art;
Fig. 2 is the structural representation of ggnmos transistor of the prior art;
Fig. 3 is the drain current of ggnmos transistor of the prior art and the I/V performance plot of drain voltage;
Fig. 4 is the structural representation of the ESD protection circuit of the embodiment of the present invention;
Fig. 5 is that grid voltage is the drain voltage of nmos pass transistor and the I/V performance plot of drain current of 0.5V and 0V.
Embodiment
Please refer to Fig. 3, is the drain current of existing ggnmos transistor and the I/V performance plot of drain voltage.When electrostatic potential that electrostatic pulse produces is applied in the drain electrode of described ggnmos transistor, described electrostatic potential is mainly added on PN junction anti-inclined to one side between the drain electrode of ggnmos transistor and substrate, form depletion region, because described depletion region is high resistance area, when drain voltage continues to become large, drain current is substantially constant; Until drain voltage reaches trigger voltage V
1, described trigger voltage is the anti-puncture voltage partially of PN junction between drain electrode and substrate, and drain current reaches I
1time, the drain voltage being applied on described depletion region is enough large, makes depletion region that avalanche multiplication effect occur, inspire hole-electron pair, the hole producing drifts about to substrate, and the electric current of the substrate that makes to flow through becomes large, and the voltage being applied in the dead resistance of substrate becomes large, make the PN junction positively biased between source electrode and substrate, parasitic triode is opened, source-drain electrode conducting, and electrostatic induced current discharges by ggnmos transistor, drain current increases, and drain voltage is dragged down very soon keeps voltage V
2, drain current reaches I
2; When the continuation along with static discharge, drain voltage continues to increase, when drain current continues to increase, until drain voltage reaches the second puncture voltage V
3, described the second puncture voltage is the voltage of ggnmos transistor generation thermal breakdown, drain current reaches I
3time, the heat that the electric current of static discharge produces can cause thermal breakdown, and ggnmos transistor can enter second breakdown region, and drain current continues to increase, and drain voltage is dragged down, until static has been released.In existing ggnmos transistor, described V
3often be less than V
1.
When described drain voltage rises to V
1time, static discharge is carried out in described a plurality of ggnmos transistor parallel connection, difference due to the dead resistance of different ggnmos transistor substrates, the voltage being applied in the dead resistance of substrate also can be different, make the voltage that the PN junction between source electrode and substrate applies also can be different, may cause the first conducting of part ggnmos transistor, the not yet conducting of part ggnmos transistor.Because the ggnmos transistor of partial electrostatic electric charge by conducting discharges, electrostatic potential reduces, and electrostatic potential again rises less than V
1even if drain voltage reaches the second puncture voltage V
3, due to described V
3often be less than V
1the not conducting again of ggnmos transistor of conducting of part; electrostatic pulse can only discharge by the ggnmos transistor of a few conducting; the discharging current of single ggnmos transistor is excessive; easily burn ggnmos transistor, thereby it is good effectively to carry out electrostatic discharge (ESD) protection conducting homogeneity.
Inventor finds through research, if described trigger voltage V
1be less than the second puncture voltage V
3even the difference of the dead resistance of different ggnmos transistor substrates, in the time of may causing the first conducting of part ggnmos transistor, the not yet conducting of part ggnmos transistor, but the drain voltage of the ggnmos transistor of described conducting finally still can rise in the process of static discharge, until rise to the second puncture voltage V
3, electrostatic potential rises to V
3, due to V
3be greater than V
1in the process that described electrostatic potential rises; all the other are the part ggnmos transistor conducting of conducting not; make all ggnmos transistors release electrostatic simultaneously; also there is not second breakdown in the part ggnmos transistor of the first conducting of part simultaneously, both avoided protective circuit premature failure, also increased the quantity of the ggnmos transistor of conducting; the electrostatic discharge capacity that has improved described ESD protection circuit, has improved conducting homogeneity.
For this reason; inventor is through research; a kind of ESD protection circuit has been proposed; in described ESD protection circuit, the drain electrode of nmos pass transistor is connected with static discharge input with the RC circuit that the second resistance forms by the electric capacity of series connection, and is connected between the grid of described nmos pass transistor and electric capacity, the second resistance.Due to when static discharge input has higher electrostatic potential because of static discharge; described electrostatic potential can pass through capacitive coupling part voltage to the grid of nmos pass transistor; make the grid voltage of nmos pass transistor be greater than 0V; be conducive to reduce the trigger voltage of nmos pass transistor; simultaneously by controlling the size of the first resistance and the second resistance; make the grid voltage of nmos pass transistor be less than the threshold voltage of nmos pass transistor; make nmos pass transistor successfully to carry out electrostatic discharge (ESD) protection, can improve again the conducting homogeneity of ESD protection circuit.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The embodiment of the present invention provides a kind of ESD protection circuit, please refer to Fig. 4, and the structural representation for the ESD protection circuit of the embodiment of the present invention, specifically comprises:
Static discharge input ESD, earth terminal GND, some identical electrostatic discharge (ESD) protection unit 100 between described static discharge input ESD, earth terminal GND, described electrostatic discharge (ESD) protection unit 100 is arranged in parallel, one end of described electrostatic discharge (ESD) protection unit 100 is connected with static discharge input ESD, and the other end is connected with earth terminal GND;
Described electrostatic discharge (ESD) protection unit 100 comprises nmos pass transistor 110, electric capacity 120, the first resistance 130, the second resistance 140, the first end of described electric capacity 120 is connected with static discharge input ESD, the second end of described electric capacity 120 and the first end of the second resistance 140, the grid of nmos pass transistor 110 is connected, the electric capacity 120 of described series connection and the second resistance 140 form RC circuit, the first end of described the first resistance 130 is connected with static discharge input ESD, the second end of the second end of described the second resistance 140 and described the first resistance 130, the drain electrode of nmos pass transistor 110 is connected, the source electrode of described nmos pass transistor 110 is connected with earth terminal GND with substrate.
Described ESD protection circuit is positioned between input/output interface (not shown) and chip internal circuit (not shown), by described static discharge input ESD, is connected with described input/output interface, chip internal circuit.When described input/output interface produces static discharge current; because described ESD protection circuit is between input/output interface and chip internal circuit; described static discharge current discharges by ESD protection circuit; make chip internal circuit can not bear very large static discharge current, avoid it to flow into chip internal circuit and cause damage.
Described several electrostatic discharge (ESD) protection unit 100 are identical; the specification that is nmos pass transistor 110 in described electrostatic discharge (ESD) protection unit 100, electric capacity 120, the first resistance 130, the second resistance 140 is identical; make in theory described nmos pass transistor 110, electric capacity 120, the first resistance 130, the second resistance 140 identical; even the dead resistance of the substrate of different N MOS transistor is different in reality; difference is also little, is conducive to improve the conducting homogeneity of each nmos pass transistor.
When nmos pass transistor is not during conducting, static discharge input is subject to static discharge, described electrostatic potential can trigger RC circuit, the voltage that coupling produces is applied to the grid of described nmos pass transistor, make the grid voltage of described nmos pass transistor be greater than 0V, and resistance during conducting is very not large due to described nmos pass transistor, static discharge input is because the higher electrostatic potential that static discharge has is applied to drain electrode and the substrate two ends of described nmos pass transistor substantially, the voltage at the RC circuit two ends that electric capacity 120 and the second resistance 140 form is very little, by adjusting the resistance value of described the second resistance 140, make the magnitude of voltage between described electric capacity 120 and the second resistance 140 be greater than 0V, be less than the threshold voltage of nmos pass transistor.In the present embodiment, the scope of the resistance value of described the second resistance 140 is 1 ohm ~ 100 ohm.Because the magnitude of voltage between described electric capacity 120 and the second resistance 140 is greater than 0V, the part electric field of the depletion region between drain electrode and substrate can become large, strong internal field can make the puncture voltage between drain electrode and substrate diminish, can reduce the trigger voltage of nmos pass transistor, and by adjusting the size of grid voltage, make the trigger voltage V of nmos pass transistor
1be less than the second puncture voltage V
3.The drain voltage producing when static discharge is more than or equal to the trigger voltage V of nmos pass transistor
1after, between drain electrode and substrate, PN junction punctures, and the parasitic triode of nmos pass transistor is opened, source-drain electrode conducting, electrostatic induced current discharges by ggnmos transistor, and drain current increases, and drain voltage is dragged down very soon keeps voltage V
2; And when the continuation along with static discharge, drain voltage continues to increase, when drain current continues to increase, until drain voltage reaches the second puncture voltage V
3.
Due to described trigger voltage V
1be less than the second puncture voltage V
3even the difference of the dead resistance of nmos pass transistor 110 substrates in different electrostatic discharge (ESD) protections unit 100; in the time of may causing the first conducting of part NMOS crystal; the not yet conducting of part NMOS crystal, but the drain voltage of the NMOS crystal of described conducting can rise to the second puncture voltage V in the process of static discharge
3, due to V
3be greater than V
1in the process that described electrostatic potential rises; all the other are the part NMOS crystal conducting of conducting not; make all NMOS crystal release electrostatic simultaneously; also there is not second breakdown in the part NMOS crystal of the first conducting of part simultaneously, both avoided protective circuit premature failure, also increased the quantity of the NMOS crystal of conducting; the electrostatic discharge capacity that has improved described ESD protection circuit, has improved conducting homogeneity.And because described grid voltage is less than the threshold voltage of nmos pass transistor, described nmos pass transistor can not form channel region, so can not affect the electrostatic protection ability of this NMOS.
In embodiments of the present invention, the scope of described grid voltage is 0V ~ 0.5V, such as 0.1V, 0.2V, 0.3V, 0.4V etc.Please refer to Fig. 5, for grid voltage is the drain voltage of nmos pass transistor and the I/V performance plot of drain current of 0.5V and 0V.The trigger voltage V of nmos pass transistor when grid voltage is 0.5V
1be less than the second puncture voltage V
3, and the trigger voltage V of grid voltage nmos pass transistor while being 0V
1be greater than the second puncture voltage V
3.
In embodiments of the present invention, described the first resistance 130 is the interconnection line dead resistance between nmos pass transistor 110 and static discharge input ESD.In other embodiments, described the first resistance 130 is polysilicon resistance or metallic resistance.
To sum up; in the described ESD protection circuit of the embodiment of the present invention; the drain electrode of nmos pass transistor is connected with static discharge input with the RC circuit that the second resistance forms by the electric capacity of series connection, and is connected between the grid of described nmos pass transistor and electric capacity, the second resistance.When static discharge input is subject to static discharge, described electrostatic potential can trigger RC oscillating circuit, the voltage that coupling produces is to the grid of described nmos pass transistor, make the grid voltage of described nmos pass transistor be greater than 0V, and the grid voltage ground connection of ggnmos transistor of the prior art, be conducive to reduce the trigger voltage of described nmos pass transistor, described NMOS is more easily switched on, improved the conducting homogeneity of described NMOS.Simultaneously by controlling the size of the first resistance and the second resistance; make the grid voltage of described nmos pass transistor be less than the threshold voltage of described nmos pass transistor; make described nmos pass transistor successfully to carry out electrostatic discharge (ESD) protection, can improve again the conducting homogeneity of ESD protection circuit.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (9)
1. an ESD protection circuit, it is characterized in that, comprise: static discharge input, earth terminal, be positioned at described static discharge input, some electrostatic discharge (ESD) protections unit between earth terminal, described electrostatic discharge (ESD) protection unit is arranged in parallel, and described electrostatic discharge (ESD) protection unit comprises nmos pass transistor, electric capacity, the first resistance, the second resistance, the first end of described electric capacity is connected with static discharge input, the second end of described electric capacity and the first end of the second resistance, the grid of nmos pass transistor is connected, the first end of described the first resistance is connected with static discharge input, the second end of described the second resistance and the second end of described the first resistance, the drain electrode of nmos pass transistor is connected, the source electrode of described nmos pass transistor is connected with earth terminal with substrate.
2. ESD protection circuit as claimed in claim 1, is characterized in that, the voltage that is applied to the grid of described nmos pass transistor is greater than 0V, is less than the threshold voltage of nmos pass transistor.
3. ESD protection circuit as claimed in claim 2, is characterized in that, the scope of voltage that is applied to the grid of described nmos pass transistor is 0V ~ 0.5V.
4. ESD protection circuit as claimed in claim 1 or 2, is characterized in that, the trigger voltage of described nmos pass transistor is less than the second puncture voltage.
5. ESD protection circuit as claimed in claim 1, is characterized in that, described the first resistance is the interconnection line dead resistance between nmos pass transistor and static discharge input.
6. ESD protection circuit as claimed in claim 1, is characterized in that, described each electrostatic discharge (ESD) protection unit is identical.
7. ESD protection circuit as claimed in claim 1; it is characterized in that; described ESD protection circuit, between input/output interface and chip internal circuit, is connected with input/output interface, chip internal circuit by described static discharge input.
8. ESD protection circuit as claimed in claim 1, is characterized in that, the scope of the resistance value of described the second resistance is 1 ohm ~ 100 ohm.
9. ESD protection circuit as claimed in claim 1, is characterized in that, the substrate of described nmos pass transistor has dead resistance, and the dead resistance of the substrate of different N MOS transistor is different.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241828.7A CN103545306B (en) | 2012-07-12 | 2012-07-12 | ESD protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241828.7A CN103545306B (en) | 2012-07-12 | 2012-07-12 | ESD protection circuit |
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| CN103545306A true CN103545306A (en) | 2014-01-29 |
| CN103545306B CN103545306B (en) | 2016-03-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106410773A (en) * | 2016-09-23 | 2017-02-15 | 中国科学院上海微系统与信息技术研究所 | Enhancement type stacked ESD circuit and mixed voltage input-output interface circuit |
| CN108847836A (en) * | 2018-08-10 | 2018-11-20 | 深圳南云微电子有限公司 | Electrostatic discharge self-protection circuit and self-protection method |
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|---|---|---|---|---|
| US5959488A (en) * | 1998-01-24 | 1999-09-28 | Winbond Electronics Corp. | Dual-node capacitor coupled MOSFET for improving ESD performance |
| US20030076639A1 (en) * | 2001-10-19 | 2003-04-24 | Wei-Fan Chen | High ESD stress sustaining ESD protection circuit |
| TW200529405A (en) * | 2004-02-18 | 2005-09-01 | Fujitsu Ltd | Electrostatic discharge protection circuit |
| US20110051298A1 (en) * | 2009-08-27 | 2011-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Esd improvement with dynamic substrate resistance |
-
2012
- 2012-07-12 CN CN201210241828.7A patent/CN103545306B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959488A (en) * | 1998-01-24 | 1999-09-28 | Winbond Electronics Corp. | Dual-node capacitor coupled MOSFET for improving ESD performance |
| US20030076639A1 (en) * | 2001-10-19 | 2003-04-24 | Wei-Fan Chen | High ESD stress sustaining ESD protection circuit |
| TW200529405A (en) * | 2004-02-18 | 2005-09-01 | Fujitsu Ltd | Electrostatic discharge protection circuit |
| US20110051298A1 (en) * | 2009-08-27 | 2011-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Esd improvement with dynamic substrate resistance |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106410773A (en) * | 2016-09-23 | 2017-02-15 | 中国科学院上海微系统与信息技术研究所 | Enhancement type stacked ESD circuit and mixed voltage input-output interface circuit |
| CN106410773B (en) * | 2016-09-23 | 2018-09-25 | 中国科学院上海微系统与信息技术研究所 | Enhanced stack ESD circuit and mixed-voltage input/output interface circuit |
| CN108847836A (en) * | 2018-08-10 | 2018-11-20 | 深圳南云微电子有限公司 | Electrostatic discharge self-protection circuit and self-protection method |
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| CN103545306B (en) | 2016-03-16 |
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