CN103531239B

CN103531239B - Internal memory erasing method and its drive circuit

Info

Publication number: CN103531239B
Application number: CN201210229773.8A
Authority: CN
Inventors: 卢孝华; 郭志明; 王宇淳
Original assignee: Eon Silicon Solutions Inc
Current assignee: Eon Silicon Solutions Inc
Priority date: 2012-07-04
Filing date: 2012-07-04
Publication date: 2016-07-20
Anticipated expiration: 2032-07-04
Also published as: CN103531239A

Abstract

The invention provides a kind of internal memory erasing method and drive circuit thereof, main technical schemes includes: when memory element is chosen and erases, be set to floating by the drain electrode of all memory element in the grid of the multiple memory element being erased in selected memory block, selected memory heap and the grid of non-selected multiple memory element；There is provided positive voltage to all of source electrode of selected memory heap and the p type wells shared thereof and N-type well；There is provided negative voltage to the grid of the multiple memory element to erase selected in memory block.Thereby, utilize grid floating can receive to from the coupled voltages of p type wells positive electricity, reach the suppression of erasing of non-selected multiple memory block so that decoding more becomes to simplifying and easy extension and the segmentation of storage compartments in memory block reaching more memory block or memory heap with less layout area.

Description

Internal memory erasing method and its drive circuit

Technical field

The invention relates to a kind of or/no type flash memory (NORFLASHMEMORY), and particularly a kind of internal memory erasing method suitable in or/no type flash memory, and for carrying out the drive circuit of internal memory erasing method.

Background technology

Along with the progress of semiconductor technology, the capacity of internal memory is also increasing, and its speed is also more and more faster.Or/no type flash memory is widely used in electronic product by people at present, or/no type internal memory can have multiple memory heap (BANK), and each memory heap has multiple memory block (BLOCK), each memory block has the multiple memory element being arranged in several rows with ordered series of numbers.In general, multiple memory element can be had in each memory block to share a p type wells (PWELL) and a N-type well (NWELL).When multiple memory element on certain string in some memory block of erasing, voltage of p type wells applying being erased traditionally (is generally bigger positive voltage, it is such as 8V), and a negative voltage can be applied (be generally bigger negative voltage, it is such as-9V) the so far grid of multiple memory element on row, erase thereby reaching the data in memory element.But, in same memory block, the grid of multiple memory element of all the other row owing to being not intended to be erased must be applied in a system power source voltage or (be generally relatively low positive voltage lower than the positive voltage of voltage of erasing, such as VCC or 3V), namely operation so can cause the disturbance of erasing (ERASEDISTURB) in the process of erasing.

In general, disturbance of erasing can be had preferably rejection ability by less memory block, but it is relative, it is more many that memory block is distinguished, chip size is more big on the contrary, therefore, or/no type flash memory be limited in most application at present 4K position of such as once erasing (that is, one section (SECTOR)) or 64K position (that is, a block).In addition, for disturbance of erasing, still it is suggested without optimized design at present.Therefore, for the internal memory of the row that must configure a fixed number, to reduce disturbance of erasing, it is necessary to multiple row to be divided into more memory block or storage compartments.Furthermore, more memory block or storage compartments to be divided into, just need more power supply exchange decoding circuit and drive circuit, to produce the voltage signal of correspondence, so namely cause the increase of chip size.

Refer to the configuration schematic diagram between the memory heap that Fig. 1 and Fig. 2, Fig. 1 are flash memories；And Fig. 2 is that the drive circuit of traditional or/no type flash memory is in the circuit block diagram in Figure 1A region.Traditional or/no type flash memory has multiple drive circuit, each drive circuit 10 be configured at adjacent two memory heaps (such as BANK_0, BANK_1) adjacent two corresponding memory block (as: between BLOCK_n).Drive circuit 10 includes a wordline driving circuit WL_DRIVER, two block p type wells voltage supply circuit BGPW1 and BGPW2,16 negative voltage supply circuit VNNI_X16 and one bit line drive circuit YDSL_DRIVER.Generally speaking, each storage compartments have 4K position (that is, one storage compartments has 4K memory element), each memory block (such as BLOCK_0, BLOCK_1) has 16 storage compartments (that is, a memory block has 64K memory element).This wordline driving circuit WL_DRIVER generally has multiple character line pre-driver WL_pre_Driver, each character line pre-driver WL_pre_Driver is used for driving 16 left character line LWL_X16 and 16 right character line RWL_X16 of correspondence, to drive adjacent two memory block (such as such memory element corresponding in BLOCK_n) respectively.

Two blocks p type wells voltage supply circuit BGPW1, BGPW2 receive system power supply Y_POWER provides the positive voltage p type wells to two corresponding adjacent memory block BLOCK_n and N-type well respectively.Wordline driving circuit WL_DRIVER receives 16 the power source X_POWER_X16 exchanging decoding circuit (not shown) from power supply, and produces 16 character lines driving signals accordingly to the grid of multiple memory element of multiple row.Bit line drive circuit YDSL_DRIVER receives system power supply Y_POWER, and in order to drive multiple bit line YBL of two corresponding adjacent memory block BLOCK_n.The each of 16 negative voltage supply circuit VNNI_X16 receives negative voltage VNNG, and produce 16 negative voltages to wordline driving circuit WL_DRIVER according to negative voltage VNNG, so that character line selected in the 16 of two memory block BLOCK_n storage compartments to be erased.

When multiple memory element of certain string in some storage compartments of erasing, wordline driving circuit WL_DRIVER can supply negative voltage to the character line of these row, and wherein, the character line of these row connects the grid of the multiple memory element so far arranged.Meanwhile, in the memory block belonging to these memory element to be erased, not needing the multiple character lines belonging to the memory element being erased is then be supplied system power source voltage.If it addition, memory block does not have the memory element needing to be erased, then the character line of this memory block then all can be applied in the ground voltage (0V) supplied by wordline driving circuit WL_DRIVER.

Traditional or/no type flash memory is configuration one drive circuit 10 in the space between two memory block that the correspondence in adjacent two memory heaps is adjacent, configure the space of this drive circuit 10 and namely show in Fig. 1 the clearance space of the strip between BLOCK_0 and BLOCK_1 and BLOCK_2 and BLOCK_3, therefore, erasing based on minimizing under the premise of disturbance, or/no type flash memory can have more memory block or storage compartments.The too much potential circuit that suppresses will make wordline driving circuit excessively complicated plus the segmentation of storage compartments, to extend more memory block or memory heap, be necessary for repeating the drive circuit of the traditional or/no type flash memory of configuration, so namely can increase the area taken.

Summary of the invention

One purpose of the present invention is to make internal memory erasing method and drive circuit decoding thereof more become to simplifying, and is easier to reach the extension of more memory block or memory heap with less layout area, and increases the segmentation of storage compartments in memory block.

For reaching above-mentioned purpose and other purpose, the present invention provides a kind of internal memory erasing method, when multiple memory element of the string of a memory block of a memory heap are chosen and erase, this internal memory erasing method includes: by the grid of each memory element of the non-selected memory block under the drain electrode of all memory element under the grid of the memory element to be erased not selected under this memory block selected, this memory heap selected and this memory heap selected, be set to floating；There is provided a positive voltage to the source electrode of all memory element under this memory heap selected, the p type wells shared and a N-type well；And provide a negative voltage to the grid of these memory element described in being intended under these row of this memory block selected to erase.

For reaching above-mentioned purpose and other purpose, drive circuit provided by the invention includes the many groups of memory heaps being adjacent to, configuration one main drive circuit in adjacent two corresponding memory block of one group of memory heap, adjacent two corresponding memory block in the memory heap of all the other groups are then respectively configured a secondary drive circuit, this main drive circuit includes: a universe novel word-line driver design for pseudo two-port, in order to receive the power source exchanging decoding circuit from a power supply, and produce multiple universe character line signal universe character line signal reverse with it accordingly；Two extended first area novel word-line driver design for pseudo two-port, in order to receive such universe character line signal universe character line signal reverse with it, and receive another power source exchanging decoding circuit from this power supply, and produce accordingly and the voltage of these character lines described that these two memory block adjacent are provided；One universe negative voltage supply circuit, in order to receive one with reference to negative voltage, and provides a negative voltage to such extended first area novel word-line driver design for pseudo two-port；And one first bit line drive circuit, in order to drive these bit lines described in these two memory block adjacent.This pair drive circuit then includes: an extended second area novel word-line driver design for pseudo two-port, in order to receive such universe character line signal universe character line signal reverse with it, and receive another power source exchanging decoding circuit from this power supply, and produce accordingly and the voltage of these character lines described that adjacent storage zones block is provided；And a second line drive circuit, in order to drive these bit lines described in the block of adjacent storage zones.

In sum, the invention provides a kind of internal memory erasing method and the drive circuit implementing this internal memory method, the driving method of the application of the invention can simplify circuit complexity and disturbance of erasing is had preferably rejection ability.The drive circuit of the present invention and the secondary drive circuit of collocation, the expansion utilizing secondary drive circuit can increase multiple row of or/no type flash memory and multiple row, all must be the same without the area shared by the drive circuit made between adjacent two memory block of adjacent two memory heaps, can significantly simplify circuit complexity and then reduce the area that circuit takies.

Accompanying drawing explanation

Fig. 1 is the configuration schematic diagram between the memory heap of flash memory.

Fig. 2 is that the drive circuit of traditional or/no type flash memory is in the circuit block diagram in Figure 1A region.

Fig. 3 is the flow chart of the internal memory erasing method that the embodiment of the present invention provides.

Fig. 4 is the configuration schematic diagram of the memory heap of flash memory in one embodiment of the invention.

Fig. 5 is in order to realize the circuit block diagram of the drive circuit of Fig. 3 erasing method in one embodiment of the invention.

Fig. 6 is in order to realize the circuit block diagram of the drive circuit of the flow and method of Fig. 3 in another embodiment of the present invention.

Fig. 7 A, Fig. 7 B, Fig. 7 C are the operation charts in one embodiment of the invention under extended area characters line drive different conditions in the process of erasing.

Drawing reference numeral:

10 drive circuits

30 main drive circuits

40 secondary drive circuits

A, A' region

B, B ' region

BANK_0 ~ 3 memory heap

BLOCK_1～3 memory block

WL_DRIVER wordline driving circuit

WL_pre_Driver character line pre-driver

The left character line of LWL_X16

The right character line of RWL_X16

X_POWER_X16 power supply

BGPW1, BGPW2 block p type wells voltage supply circuit

VNNI_X16 negative voltage supply circuit

YDSL_DRIVER bit line drive circuit

Y_POWER system power supply

YBL bit line

VNNG negative voltage

S20, S22, S24 step

The extended area characters line drive of L_WL_DRIVER

GBGVNN universe negative voltage supply circuit

GBGVNNC negative voltage

GWL universe character line signal

The reverse universe character line signal of GWLB

G_WL_DRIVER universe novel word-line driver design for pseudo two-port

XDC16 area characters line driver element

GWL_UNIT universe character line driver element

BKVNN memory heap negative pressure signal

N1 ~ N3 transistor

Detailed description of the invention

For being fully understood by the purpose of the present invention, feature and effect, hereby by following specific embodiment, and coordinate appended accompanying drawing, the present invention be described in detail, illustrate as rear:

In order to extend multiple row of or/no type flash memory and multiple row more easily, to promote the capacity of or/no type flash memory, it is not desired to again exceedingly increase chip size, the invention provides a kind of internal memory erasing method and the drive circuit implementing this internal memory method, the drive circuit of the application of the invention, multiple row of or/no type flash memory and multiple row can be increased, without increasing chip size in large quantities.

First, refer to the flow chart that Fig. 3, Fig. 3 are the internal memory erasing methods that the embodiment of the present invention provides.Or/no type flash memory has multiple memory heap, each memory heap has multiple memory block, each memory block has multiple memory element, these memory element are arranged in multiple row and multiple row, each character line is connected to the grid of multiple memory element of respective column, each region bit line is connected to the drain electrode of multiple memory element of corresponding row, and the source electrode of multiple memory element of every several rows is connected to a global bit line by multiple selection transistors.

Wherein, when multiple memory element of row in a memory block of a memory heap are chosen and erase, or/no type flash memory can be performed internal memory erasing method.In step S20, it is that following (A), (B), (C) described part are set to floating, wherein, under (A), selected memory block, is not selected for the grid in the multiple memory element erased；(B), under selected memory heap, the drain electrode of all memory element；(C), under selected memory heap, the grid of each memory element in all non-selected memory block.

Then step S22 is carried out, it is provided that positive voltage (such as: 8V) is to the source electrode of all memory element in all memory block under selected memory heap, and provides positive voltage (such as: 8V) to the p type wells shared and N-type well.Step S24 is then: provide negative voltage (such as :-9V) to, under these row of selected memory block, being intended to the grid of the multiple memory element erased.In a general case, in selected memory block, the floated grid of multiple memory element of non-selected multiple row, its voltage is less than the positive voltage of p type wells (voltage of such as, floated grid is about 4V).It should be strongly noted that the execution sequence of above-mentioned steps S20, S22 and S24 is not limited to the present invention, step S22 and S24 is preferably and implements simultaneously, additionally, step S22 and S24 also can before step S20, or three steps are implemented simultaneously.

It addition, the erasing method of Fig. 3 further comprises other step, this step performed before step S20 and S22.This step provides drive circuit between adjacent two memory block of adjacent two memory heaps, this drive circuit is in order to provide negative voltage, and is responsible for being set to floating by the grid of the multiple not selected multiple memory element to be erased under selected memory block.

Then, refer to Fig. 4, it it is the configuration schematic diagram of the memory heap of flash memory in one embodiment of the invention, it is in the both sides of main drive circuit (that is: take up room be similar to existing drive circuit), replace the existing universe novel word-line driver design for pseudo two-port constantly repeating configuration taking the less secondary drive circuit of circuit area (A' region), to reduce in existing flash memory the configuration space needed for drive circuit.In other words, the drive circuit in the embodiment of the present invention includes the many groups of memory heaps being adjacent to, for instance: BANK_0 and BANK_1 one group, BANK_1 and BANK_2 one group, BANK_2 and BANK_3 one group.Configuration one main drive circuit (having a universe novel word-line driver design for pseudo two-port and two extended area characters line drives) in adjacent two corresponding memory block of one group of memory heap (BANK_1, BANK_2), in the memory heap of all the other groups, (BANK_0 and BANK_1, BANK_1 and BANK_2) is then respectively configured a secondary drive circuit (only having an extended area characters line drive).That is, the embodiment of the present invention is with 1 several secondary drive circuit of main drive circuit collocation.Each memory heap need to configure 1 extended area characters line drive, and the universe novel word-line driver design for pseudo two-port in 1 main drive circuit of configuration pushes away all of extended area characters line drive simultaneously.Such as: if there being 4 memory heaps, then need 1 main drive circuit (there is 1 universe novel word-line driver design for pseudo two-port), and 4 extended area characters line drives of collocation (comprise: 2 extended area characters line drives in main drive circuit, and other extended area characters line drive in 2 secondary drive circuits)；If there being 8 memory heaps, then it is still and only needs 1 main drive circuit (there is 1 universe novel word-line driver design for pseudo two-port), and 8 extended area characters line drives (2 extended area characters line drives in main drive circuit, and other extended area characters line drive in 6 secondary drive circuits) of collocation.

Fig. 5 is in order to realize the circuit block diagram of the drive circuit of Fig. 3 erasing method in one embodiment of the invention, meanwhile, its be representative graph 4 B ' region under the circuit block diagram of the present invention.Or/no type flash memory includes multiple memory heap and multiple drivers.Each memory heap has multiple memory block, and each memory block has multiple memory element, and these memory element are arranged in multiple row and multiple row.Each character line is connected to the grid of multiple memory element of respective column, and each region bit line is connected to the drain electrode of multiple memory element of corresponding row, and the source electrode of multiple memory element of every several rows is connected to a global bit line by multiple selection transistors.The drive circuit of the present invention comprises main drive circuit 30 and a secondary drive circuit 40.

As shown in Figure 5, each main drive circuit 30 be configured at the correspondence of adjacent two memory heaps (BANK_1, BANK_2 as shown in Figure 4) adjacent between two memory block BLOCK_n, BLOCK_n (such as: the BLOCK_1 of BLOCK_1 and the BANK_2 of BANK_1), main drive circuit 30 includes a universe novel word-line driver design for pseudo two-port G_WL_DRIVER, two extended area characters line drive L_WL_DRIVER, universe negative voltage supply circuit GBGVNN and one bit line drive circuit YDSL_DRIVER.Two extended area characters line drive L_WL_DRIVER are in order to receive universe character line signal GWL and reverse universe character line signal GWLB, and receive two the power source X_POWER_X16 exchanging decoding circuit (not shown) from power supply, and produce accordingly and voltage a plurality of character line LWLX_16, RWLX_16 to adjacent two memory block is provided.Universe negative voltage supply circuit GBGVNN is in order to receive with reference to negative voltage VNNG, and provides negative voltage GBGVNNC to such extended area characters line drive L_WL_DRIVER and this universe novel word-line driver design for pseudo two-port G_WL_DRIVER.Bit line drive circuit YDSL_DRIVER receives system voltage Y_POWER, and in order to drive multiple bit line YBL of adjacent two memory block BLOCK_1, BLOCK_2.

Universe novel word-line driver design for pseudo two-port G_WL_DRIVER exchanges another power source X_PLUS_POWER of decoding circuit in order to receive from power supply, and produces universe character line signal GWL and reverse universe character line signal GWLB accordingly to two extended area characters line drive L_WL_DRIVER.Embodiments of the invention are to make or/no type flash memory increase more memory block under same memory heap, its practice is for replicating extended area characters line drive L_WL_DRIVER, and adjacent in each two adjacent memory heap BANK_0, BANK_1 configures the secondary drive circuit 40 (referring to Fig. 6) without universe novel word-line driver design for pseudo two-port G_WL_DRIVER between two memory block BLOCK_n, BLOCK_n.

Fig. 6 is in order to realize the circuit block diagram of the drive circuit of the flow and method of Fig. 3 in another embodiment of the present invention, meanwhile, Fig. 6 be representative graph 4 B ' region under the circuit block diagram of the present invention.By the present invention in the framework of embodiment illustrated in fig. 5, when or/no type flash memory to increase memory heap, also only need to replicate above-mentioned secondary drive circuit 40 between adjacent two correspondences memory block BLOCK_n, BLOCK_n (such as: the BLOCK_1 of BLOCK_1 and the BANK_0 of BANK_1) of two adjacent memory heap BANK_0, BANK_1 (referring to Fig. 4).It is that universe negative voltage supply GBGVNN negative voltage GBGVNNC, the universe novel word-line driver design for pseudo two-port G_WL_DRIVER the provided universe character line signal GWL exported and reverse universe character line signal GWLB thereof is provided in the adjacent extended area characters line drive L_WL_DRIVER between two memory block BLOCK_n, BLOCK_n of adjacent two memory heaps BANK_0, BANK_1.Each memory heap reception have a memory heap negative pressure signal BKVNN (not shown), in order to supply the operation of 0 or negative voltage.Compare with the driver of tradition or non-flash, main drive circuit 30 and secondary drive circuit 40 are merely with single universe negative voltage supply GBGVNN, less universe novel word-line driver design for pseudo two-port G_WL_DRIVER and extended area characters line drive L_WL_DRIVER, therefore, overall drive circuit size can be largely reduced.So, if the framework using the embodiment of the present invention to provide, then it is easier to reach the extension of more memory block or memory heap with less layout area.How many extended area characters line drive L_WL_DRIVER can be coupled as a main drive circuit 30 and then depend on the factors such as the driving force of universe novel word-line driver design for pseudo two-port G_WL_DRIVER, load, speed of operation, it is to belong to prior art, and those skilled in the art can adopt applicable universe novel word-line driver design for pseudo two-port G_WL_DRIVER easily.

Please continue to refer to Fig. 6, each extended area characters line drive L_WL_DRIVER can have 64 area characters line driver element XDC16, each area characters line driver element XDC16 receives power supply X_POWER_X16, negative voltage GBGVNNC, universe character line signal GWL universe reverse with it character line signal GWLB, and produces the voltage of 16 character lines accordingly.Similarly, universe novel word-line driver design for pseudo two-port G_WL_DRIVER includes 64 universe character line driver element GWL_UNIT, corresponding two the area characters line driver element XDC16 of each universe character line driver element GWL_UNIT, and produce corresponding universe character line signal GWL and its reverse universe character line signal GWLB to two corresponding area characters line driver element XDC16.Area characters line driver element XDC16 can have the transistor of three series connection in time implementing, but, when the breakdown voltage of first transistor is enough high, area characters line driver element XDC16 can only have the transistors of two series connection, even can directly use one-transistor.

nullAs adjacent two memory heap BANK_0、One of them multiple memory element of one of memory block row of BANK_1 are selected when erasing，Corresponding extended area characters line drive L_WL_DRIVER applies negative electricity and is pressed under these row of selected memory block to be intended to the character line corresponding to grid of the multiple memory element erased，And the extended area characters line drive L_WL_DRIVER of this correspondence is by the grid floating of the multiple memory element to be erased not selected under selected memory block，The wherein source electrode of all memory element under selected memory heap、The p type wells shared and N-type well are all applied in positive voltage，And the grid of the drain electrode of all memory element under selected memory heap and multiple memory element of all non-selected memory block under selected memory heap is set as floating.

Above-mentioned universe novel word-line driver design for pseudo two-port G_WL_DRIVER produces according to the power source X_PLUS_POWER coming from power supply exchange decoding circuit and provides universe character line signal GWL and reverse universe character line signal GWLB to each extended area characters line drive L_WL_DRIVER, and reaches the target of character line universe decoding.In addition, the p type wells of each memory heap above-mentioned is connected to positive voltage jointly, it is possible to reduce must produce the complexity of positive voltage respectively for the p type wells of each storage compartments.

Then refer to Fig. 7 A, Fig. 7 B, Fig. 7 C, be the operation chart in one embodiment of the invention under extended area characters line drive different conditions in the process of erasing.It is that the memory element of one of memory block row of a memory heap is chosen situation when erasing.

Fig. 7 A shows in the row of selected memory block, the character line of these memory element described in being intended to erase is executed alive situation by extended area characters line drive, voltage is supplied to selected extended area characters line drive L_WL_DRIVER, with the character line of these memory element described in determining to be intended to erase by power supply X_POWER_X16.In this situation, this universe character line signal GWL is operating as a negative voltage (-HV), for instance :-9V；Reverse universe character line signal GWLB and memory heap negative pressure signal BKVNN is operating as ground voltage (no-voltage), and universe negative voltage supply circuit GBGVNN is operating as that to make output voltage be a negative voltage GBGVNNC.It is then that confession should positive voltage as prior art as p type wells (not shown).Thereby, for the character line of these memory element described in being intended to erase, corresponding extended area characters line drive L_WL_DRIVER can export negative voltage and give the grid in the character line of these memory element described being intended to erase.

Fig. 7 B shows that the character line of these memory element described in not erasing under selected memory block is executed alive situation by extended area characters line drive, voltage is supplied to selected extended area characters line drive L_WL_DRIVER, with the character line of these memory element described in determining not erase by power supply X_POWER_X16.In this situation, this universe character line signal GWL is operating as a negative voltage (-HV), for instance :-9V；Reverse universe character line signal GWLB and memory heap negative pressure signal BKVNN is operating as ground voltage (no-voltage), and universe negative voltage supply circuit GBGVNN is operating as that to make output voltage be a negative voltage GBGVNNC.It is then that confession should positive voltage as prior art as p type wells (not shown).Thereby, character line for these memory element described in not erasing, corresponding extended area characters line drive L_WL_DRIVER can export the grid in a character line being given these memory element described do not erased by voltage limit (inhibitvoltage), makes the grid in this situation be set to floating.

Fig. 7 C shows that these memory block non-selected described under selected memory heap are executed alive situation by extended area characters line drive, voltage is supplied to selected extended area characters line drive L_WL_DRIVER, to determine the character line of these memory element described in non-selected these memory block described by power supply X_POWER_X16.In this situation, this universe character line signal GWL, reverse universe character line signal GWLB, BKVNN and universe negative voltage supply circuit GBGVNN are operating as ground voltage (no-voltage).It is then that confession should positive voltage as prior art as p type wells (not shown).Thereby, character line for these memory element described in these memory block non-selected described under selected memory heap, corresponding extended area characters line drive L_WL_DRIVER can export the grid in a character line being given these memory element described do not erased by voltage limit (inhibitvoltage), makes the grid in this situation be set to floating.Similarly, in the case, the drain electrode of these memory element all described under this memory heap selected, also in the way of Fig. 7 C, apply voltage, make the drain electrode in this situation also be set to floating.

Extended area characters line drive L_WL_DRIVER in earlier figures 7A, Fig. 7 B, Fig. 7 C is with three transistors N1, N2, N3 exemplarily, such as: n-type transistor, it will be recognized by one of ordinary skill in the art that such transistor is only a kind of example, other circuit arrangement that can reach aforesaid signal operation also can complete the present invention, all without departing from scope of the invention.

In sum, the present invention provides a kind of internal memory erasing method and implements the drive circuit of this internal memory method, utilize and receive to from the coupled voltages of p type wells positive electricity during grid floating, reach the suppression of erasing of non-selected multiple memory block so that decoding more becomes to simplifying and easy extension and the segmentation of storage compartments in memory block reaching more memory block or memory heap with less layout area.The main drive circuit of the present invention and the secondary drive circuit of collocation, the expansion utilizing extended area characters line drive L_WL_DRIVER can increase multiple row of or/no type flash memory and multiple row, without being repeated continuously configuration universe novel word-line driver design for pseudo two-port G_WL_DRIVER, can significantly simplify circuit complexity and then reduce circuit and take the area of chip, and also disturbance of erasing can be had preferably rejection ability.

The present invention discloses with preferred embodiment hereinbefore, so those skilled in the art will appreciate that this embodiment is only for describing the present invention, and is not construed as restriction the scope of the present invention.It should be noted that such as equivalent with this embodiment change and displacement, all should be set to be covered by scope of the invention.Therefore, protection scope of the present invention is when being as the criterion with claim institute confining spectrum.

Claims

1. an internal memory erasing method, it is characterised in that when multiple memory element of the string of a memory block of a memory heap are chosen and erase, described internal memory erasing method includes:

By the grid of each memory element of the non-selected memory block under the drain electrode of all memory element under the grid of the memory element to be erased not selected under selected described memory block, selected described memory heap and selected described memory heap, it is set to floating；

There is provided a positive voltage to the source electrode of all memory element under selected described memory heap, the p type wells shared and a N-type well；And

The grid of the one negative voltage the plurality of memory element to being intended to erase under the described row of selected described memory block is provided,

Described internal memory erasing method is used on one drive circuit and carries out, described drive circuit is applied to an or/no type flash memory, described drive circuit includes the many groups of memory heaps being adjacent to, adjacent two corresponding memory block of one group of memory heap configure a main drive circuit, adjacent two corresponding memory block in the memory heap of all the other groups are then respectively configured a secondary drive circuit, and described secondary drive circuit includes:

One extended second area novel word-line driver design for pseudo two-port, in order to receive multiple universe character line signals universe character line signal reverse with it that described main drive circuit produces, and in order to produce the offer voltage to the character line of the said two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port；And

One second line drive circuit, in order to drive the bit line of the said two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port.

2. internal memory erasing method as claimed in claim 1, it is characterised in that the described main drive circuit in described drive circuit includes:

One universe novel word-line driver design for pseudo two-port, in order to produce the plurality of universe character line signal universe character line signal reverse with it；

Two extended first area novel word-line driver design for pseudo two-port, in order to receive the plurality of universe character line signal universe character line signal reverse with it, and in order to produce the offer voltage to the character line of the said two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port；

One universe negative voltage supply circuit, in order to receive one with reference to negative voltage, and provides a negative voltage to said two extended first area novel word-line driver design for pseudo two-port；And

One first bit line drive circuit, in order to drive the bit line of the said two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port.

null3. a drive circuit，It is characterized in that，It is applied to an or/no type flash memory，Described or/no type flash memory has multiple memory heap，Each memory heap has multiple memory block，Each memory block has multiple memory element，Two adjacent memory heaps are one group，The plurality of memory element is arranged in multiple row and multiple row，Each character line is connected to the grid of the plurality of memory element of the described row of correspondence，Each region bit line is connected to the drain electrode of the plurality of memory element of the described row of correspondence，The source electrode of the plurality of memory element of every several rows is connected to a global bit line by multiple selection transistors，Described drive circuit includes the main drive circuit being configured in adjacent two memory block of adjacent two memory heaps of a group，Adjacent two memory block of the adjacent said two memory heap of all the other groups are then respectively configured a secondary drive circuit，Described secondary drive circuit includes:

4. drive circuit as claimed in claim 3, it is characterised in that described main drive circuit includes:

5. the drive circuit being used for carrying out an internal memory erasing method, it is characterized in that, it is applied to an or/no type flash memory, described drive circuit includes the many groups of memory heaps being adjacent to, adjacent two corresponding memory block of one group of memory heap configure a main drive circuit, adjacent two corresponding memory block in the memory heap of all the other groups are then respectively configured a secondary drive circuit, and described secondary drive circuit includes:

One second line drive circuit, in order to drive the bit line of the said two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port,

It is characterized in that, described internal memory erasing method is for multiple memory element of the string of a memory block of the memory heap that selects to erase, and described internal memory erasing method includes:

The grid of the one negative voltage the plurality of memory element to being intended to erase under the described row of selected described memory block is provided.