CN103515257A - High-density semiconductor packaging structure packaging method - Google Patents
High-density semiconductor packaging structure packaging method Download PDFInfo
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- CN103515257A CN103515257A CN201210199943.2A CN201210199943A CN103515257A CN 103515257 A CN103515257 A CN 103515257A CN 201210199943 A CN201210199943 A CN 201210199943A CN 103515257 A CN103515257 A CN 103515257A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
Abstract
The invention relates to a high-density semiconductor packaging structure packaging method. The method comprises the following steps: S1, providing a substrate having a bonding pad; S2, providing at least one bare die having an electrode bonding pad, wherein the at least one bare die is bonded onto the substrate; S3, forming an ink trace which is led out from the electrode bonding pad of the bare die provided in the S2 step and extended downwards to the bonding pad; S4, providing at least one bare die again, wherein the at least one bare die has an electrode bonding pad, and the at least one bare die is boned onto the bare die which is bonded and located on the top layer above the substrate; S5, and forming an ink trace again, wherein the ink trace is led out from the electrode bonding pad of the bare die provided in the S4 step and extended downwards to the formed ink trace or the bonding pad which is adjacent to the bare die provided in the S4 step and located on the lower layer. According to the invention, the packaged high-density semiconductor packaging structure has advantages of small size, thin thickness, high density and multiple pins, and advantages of simple process, short period, environmental protection and easy realization can be realized at the same time.
Description
Technical field
The present invention relates to semiconductor packages field, relate in particular to a kind of method for packing of high-density semiconductor encapsulating structure.
Background technology
Along with the development of lightening, miniaturization, multifunction and the high power capacity of electronic product, require that packaging body thickness is thinner, size is less, pin is more, density is higher, therefore encapsulating structure and encapsulation technology have been proposed to challenge.Traditional encapsulation technology has been not suitable for the development of the packaging body of high density and many pins, current most typical packaging technology is to be used as line connection with routing bonding, there is following problem: 1. the electrode pad of chip can only be arranged at chip surrounding matrix, has limited the quantity of electrode pad; 2. the electrode pad of the stacking Shi， of multilayer chiop upper strata chip will guarantee certain distance apart from edge, and when chip below distance chip edge above also will guarantee that certain distance prevents routing, porcelain mouth is encountered chip above, has increased the size of packaging body; 3. the bank of routing technique is higher, and the integral thickness of packaging body is relatively thick; 4. electrode pad bottom needs special design, must can bear the power that routing technique applies; 5. routing technique more complicated, the factor of impact is many.
In view of this, be necessary the method for packing of existing high-density semiconductor encapsulating structure to be improved to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of method for packing of high-density semiconductor encapsulating structure, its size is little, thin thickness, high density, many pins be conducive to reduce manufacturing cost and cycle.
For realizing aforementioned object, the present invention adopts following technical scheme: a kind of method for packing of high-density semiconductor encapsulating structure, comprises the steps:
S1, provide substrate, there is sticking veneer and Self-adhesive towards the pad of outer exposure;
S2, provide at least one nude film, described nude film has upper surface and the side surface of lower surface, connection upper surface and lower surface and the electrode pad outwards exposing from lower surface being oppositely arranged, described at least one nude film is affixed on described substrate, and the lower surface of described nude film adheres on described sticking veneer;
S3, formation ink cabling, the pad of described substrate is drawn and extended downward in side surface outside to the electrode pad of the nude film that described ink cabling provides from S2 step;
S4, again provide at least one nude film, this nude film also has the side surface of the upper surface that is oppositely arranged and lower surface, connection upper surface and lower surface and the electrode pad outwards exposing from lower surface, and the lower surface of this at least one nude film is affixed to the upper surface of nude film that is stuck and is positioned at the top layer of substrate top;
S5, again form ink cabling, it is adjacent and be positioned on the pad of the established ink cabling of lower floor or described substrate that this ink cabling draws and extend downward from the electrode pad of the nude film providing with S4 step the nude film providing with S4 step.
As a further improvement on the present invention, repeat S4 step and S5 step with form multilayer nude film with every layer of ink cabling that nude film is corresponding.
As a further improvement on the present invention, the side surface of the nude film that described S2 step provides is compared sticking veneer and is the angle extension that is greater than 90 degree and is less than 180 degree, and the side surface of the nude film that described S4 step provides is compared sticking veneer and is the angle extension that is greater than 90 degree and is less than 180 degree.
As a further improvement on the present invention, the nude film on described upper strata covers the electrode pad of the nude film of the lower floor being adjacent along the orthographic projection of the thickness direction of described nude film.
As a further improvement on the present invention, the ink cabling that described S3 step forms is attached at the side surface of the nude film that S2 step provides, and the ink cabling that described S5 step forms is attached at the side surface of the nude film that S4 step provides.
As a further improvement on the present invention, in S2 step, S5 step, the described nude film providing is all fixed on the sticking veneer of the substrate that is positioned at its downside and is adjacent or the upper surface of nude film as adhesive by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin, to form adhesive layer at each nude film with between its downside the substrate being adjacent or nude film.
As a further improvement on the present invention, described S2 step also comprises S21 after the nude film providing is provided in stickup, and the outside of the side surface of the nude film providing in S2 step forms has the insulating medium layer that is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree compared to the sticking veneer of described substrate; The ink cabling that described S3 step forms is attached on the outer surface of the insulating medium layer that described S21 step forms; Described S4 step also comprises S41 after the nude film again providing is provided in stickup, forms and have the insulating medium layer that is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree compared to the sticking veneer of described substrate on the side surface of the nude film providing in S4 step; The ink cabling that described S5 step forms is attached on the outer surface of the insulating medium layer that described S41 step forms.
As a further improvement on the present invention, described insulating medium layer is by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin method moulding with ink-jet or printing as material.
As a further improvement on the present invention, in described S2 step, the described at least one nude film providing and the bonding of substrate realize in the following way: on the sticking veneer of substrate, adhesive is set, the lower surface of described nude film is placed in adhesive and nude film is pressed and caused adhesive and from the lower surface of sticking veneer and nude film, overflow and be coated the side surface of nude film towards orientation substrate, to form to have, compare the tack coat that sticking veneer is the outer surface that the angle that is greater than 90 degree and is less than 180 degree extends, in described S4 step, the nude film that described S4 step provides is realized in the following way with the bonding of upper surface being stuck and be positioned at the top layer nude film of substrate top: in being stuck and being positioned on the upper surface of top layer nude film of substrate top, adhesive is set, the lower surface of the nude film that S4 step is provided is placed in adhesive and it is pressed and cause adhesive from being stuck and being positioned at the side surface that the upper surface of top layer nude film of substrate top and the lower surface of the nude film that S4 step provides overflow and be coated the nude film that S4 step provides towards orientation substrate, to form to have, compare the tack coat that sticking veneer is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree.
As a further improvement on the present invention, the ink cabling that described S3 step forms is attached on the outer surface of the tack coat that described S2 step forms; The ink cabling that described S5 step forms is attached on the outer surface of the tack coat that described S4 step forms.
The side surface of the nude film that as a further improvement on the present invention, described S2 step provides is compared sticking veneer and is the angle extension that is greater than 0 degree and is less than or equal to 90 degree.
As a further improvement on the present invention, described tack coat is: polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
As a further improvement on the present invention, the nude film on described upper strata or tack coat cover the electrode pad of the nude film of the lower floor being adjacent along the orthographic projection of the thickness direction of described nude film.
As a further improvement on the present invention, described S2 step also comprises after the nude film providing is provided in stickup: on the part upper surface of the nude film providing in S2 step, form insulating medium layer, between the upper end and electrode pad of the side surface of the nude film that described insulating medium layer provides in S2 step; Described S4 step also comprises after the nude film providing is provided in stickup: on the part upper surface of the nude film providing in S4 step, form insulating medium layer, between the upper end and electrode pad of the side surface of the nude film that described insulating medium layer provides in S4 step.
As a further improvement on the present invention, described ink cabling has head end and the connection pad of connecting electrode weld pad or is positioned at the tail end of the ink cabling of its lower floor, and described upper strata ink cabling tail end is along the outside that is positioned at coupled lower floor's ink cabling head end in the horizontal direction of nude film.
As a further improvement on the present invention, the nude film that is positioned at described substrate top is tapered stacked setting.
As a further improvement on the present invention, the nude film that is positioned at described substrate top is stacked setting, and every layer of nude film comprises the sub-nude film that several are set up in parallel, and between the some sub-nude film in same layer, is provided with interconnective tack coat.
As a further improvement on the present invention, described ink cabling by metal or alloy ink or conduction inorganic matter or conduction organic oil ink material with ink-jet or mode of printing moulding.
As a further improvement on the present invention, in described S3 or S5 step, the multilayer that described ink cabling is stacked setting, and be provided with insulating medium layer between the ink cabling Yu lower floor on this multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting.
By high-density semiconductor encapsulating structure method for packing of the present invention, can form have that size is little, the high-density semiconductor encapsulating structure of thin thickness, high density, many pins advantage, compared with prior art technique is simple, the cycle is short, environmental protection and easily realizing for this method for packing simultaneously.
Accompanying drawing explanation
Fig. 1 is the cutaway view of the embodiment of the present invention one middle-high density semiconductor package.
Fig. 2 is the structural representation of the nude film in Fig. 1 middle-high density semiconductor package.
Fig. 3 is the vertical view of Fig. 1 middle-high density semiconductor package.
Fig. 4 to Figure 10 is the implementation step schematic diagram of the method for packing of Fig. 1 middle-high density semiconductor package.
Figure 11 is the cutaway view of the embodiment of the present invention two middle-high density semiconductor packages.
Figure 12 is the cutaway view of the embodiment of the present invention three middle-high density semiconductor packages.
Figure 13 is the structural representation of the nude film in Figure 12 middle-high density semiconductor package.
Figure 14 to Figure 18 is the implementation step schematic diagram of the method for packing of Figure 12 middle-high density semiconductor package.
Figure 19 is the cutaway view of the embodiment of the present invention four middle-high density semiconductor packages.
Embodiment
Refer to Fig. 1 to 3, the high-density semiconductor encapsulating structure in the embodiment of the present invention one comprises substrate 1 and is arranged on the nude film module on substrate 1.The nude film 21 that nude film module comprises some stacked settings be formed on every layer of nude film 21 to be connected levels nude film 21 or to connect some ink cablings 22 of nude film 21 and pad 14, the structure of every nude film 21 is identical, and the electrode pad 216 of every nude film 21 can be arranged on arbitrarily on the upper surface 213 of every nude film 21 and the nude film 21 on upper strata covers the electrode pad 216 of the lower floor's nude film 21 being adjacent along the orthographic projection of the thickness direction of nude film 21.Below in conjunction with the present embodiment, the each several part of high-density semiconductor encapsulating structure is specifically described:
In the present embodiment, nude film 21 comprises two of tapered stacked setting, can be divided into basic unit's nude film 211 and top layer nude film 212.Basic unit's nude film 211 is identical with top layer nude film 212 structures, and size is different, and the size of basic unit's nude film 211 is greater than top layer nude film 212.Basic unit's nude film 211 and top layer nude film 212 all have the upper surface 213 that is oppositely arranged with lower surface 214, be connected the side surface 215 of upper surface 213 and lower surface 214 and the electrode pad 216 outwards exposing from upper surface 213.The lower surface 214 of basic unit's nude film 211 sticks on the sticking veneer 11 of substrate 1.The lower surface 214 of top layer nude film 212 is bonded on the upper surface 213 of basic unit's nude film 211.The side surface 215 of basic unit's nude film 211 and top layer nude film 212 is compared sticking veneer 11 and is all the angle extension that is greater than 90 degree and is less than 180 degree.Top layer nude film 212 covers the electrode pad of basic unit's nude film 211 216 along the orthographic projection of the thickness direction of nude film 21.
Between the lower surface 214 of basic unit's nude film 211 and sticking veneer 11, be provided with tack coat 23, between the upper surface 215 of the lower surface 214Yu basic unit nude film 211 of top layer nude film 212, be provided with too tack coat 23.By tack coat 23Jiang basic unit nude film 211 and sticking veneer 11, top layer nude film 212He basic unit nude film 211, fix respectively.Tack coat 23 can be formed by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.Certainly, also can not adopt tack coat 23, and adopt other modes that basic unit's nude film 211 and sticking veneer 14, top layer nude film 212He basic unit nude film 211 are fixed respectively.
In the present embodiment, basic unit's ink cabling 221 and top layer ink cabling 222 are individual layer setting.Really, the ink cabling being formed on every layer of nude film also can be the multilayer (not shown) of stacked setting, and is provided with insulating medium layer between the ink cabling of this multilayer ink cabling Zhong upper strata ink cabling Yu lower floor and adjacent setting.
In the present embodiment, nude film module also comprises and is arranged between basic unit's nude film 211 side surface 215He basic unit ink cablings 221, is arranged on the side surface 215 of top layer nude film 212 and the insulating medium layer 24 between top layer ink cabling 222.Insulating medium layer 24 has compares the outer surface 241 that sticking veneer is the angle extension that is greater than 90 degree and is less than 180 degree.In the present embodiment, the side surface 215 of basic unit's nude film 211 and top layer nude film 212 is parallel with the outer surface 241 of insulating medium layer 24 corresponding thereto respectively.Insulating medium layer 24 is molded on corresponding side surface 215 by ink-jet or printing.Because being all compared to sticking veneer 11 angle that is greater than 90 degree and is less than 180 degree, extends outer surface 241, so, the outer surface 241 of drawing and be attached at corresponding insulating medium layer 24 from the electrode pad 216 of basic unit's nude film 211 and top layer nude film 222 respectively at moulding Shi， basic unit ink cabling 221 and top layer ink cabling 222 extends to form downwards.Basic unit's ink cabling 221 and top layer ink cabling 222 are molded on the outer surface 241 of corresponding insulating medium layer 24 by ink-jet or printing respectively.Except the present embodiment, also insulating medium layer 24 can be set, but directly basic unit's ink cabling 221 and top layer ink cabling 222 be molded over respectively on the side surface 215 of basic unit's nude film 211 and top layer nude film 212 by ink-jet or printing.In such cases, basic unit's ink cabling 221 and 222 of top layer ink cablings are from the electrode pad 216 of basic unit's nude film 211 and top layer nude film 222, to draw and attach side surface 215 respectively to extend to form downwards.
Owing to adopting, ink cabling connects, electrode pad 216 can outwards expose from nude film 21 upper surface 213 optional positions, thereby the nude film on upper strata 21 covers the electrode pad of the nude film of the lower floor being adjacent 21 216 along the orthographic projection of the thickness direction of nude film 21, and then make the high-density semiconductor encapsulating structure in the present embodiment there is the advantages such as size is little, thin thickness, high density, many pins.
The tapered stacked setting of nude film module in the present embodiment, but except this structure, nude film module can also adopt irregular setting.Nude film module also can be arranged to two-layer more than, i.e. the stacked nude film that arranges some layers again on top layer nude film in the present embodiment one.And every layer of nude film in nude film module can comprise the sub-nude film that several are set up in parallel, between every sub-nude film, by tack coat, connect again.This tack coat can be identical with the tack coat in the present embodiment.High-density semiconductor encapsulating structure in enforcement two shown in Figure 12, in this embodiment, nude film 21 is irregular setting and in the nude film 21 of the bottom, includes two sub-nude films (not label).
Below incorporated by reference to seeing that the implementation step schematic diagram shown in Fig. 4 to Figure 10 is described in detail the method for packing of the high-density semiconductor encapsulating structure in embodiment mono-.
Incorporated by reference to Fig. 4, provide substrate 1(step S1), substrate 1 have the first surface 11 that is oppositely arranged with second surface 12, be connected the 3rd surface 13 of first surface 11 and second surface 12 and the pad 14 outwards exposing from first surface 11, owing to nude film 21 need being set on first surface 11 in subsequent step, so this first surface 11 is as sticking veneer.
Incorporated by reference to Fig. 5, a nude film 211 is provided and this nude film 211 is adhered to (step S2) on substrate 1.Nude film 211 have the upper surface 213 that is oppositely arranged with lower surface 214, be connected the side surface 215 of upper surface 213 and lower surface 214 and the electrode pad 216 outwards exposing from upper surface 213.Because this nude film 211 adheres on substrate 1, so using this nude film 211 as basic unit's nude film.Basic unit's nude film 211 adheres on the sticking veneer 11 of substrate 1 by lower surface 213.At this, basic unit's nude film 211 is fixed on the adhesive surface 11 of the substrate 1 that is positioned at its downside and is adjacent as adhesive by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin, thereby is also formed with the tack coat 23 forming by above-mentioned adhesive between basic unit's nude film 211 and the adhesive surface 11 of substrate 1.The side surface 215 of basic unit's nude film 211 is compared sticking veneer 11 and is the angle extension that is greater than 90 degree and is less than 180 degree.The electrode pad 216 of basic unit's nude film 211 can be arranged on the upper surface 213 optional position of this basic unit's nude film 211.
Incorporated by reference to Fig. 6, S2 step is after the nude film 211 providing is provided in stickup, and the side surface 215 of the nude film 211 providing in S2 step forms insulating medium layer 24(step S21).Formed insulating medium layer 24 first by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin as material with method moulding such as ink-jet or printings, and then accelerates processing through technology such as overbaking (temperature: 100 to 400 degrees Celsius) or ultraviolet illuminations.Its thickness is between several microns to tens microns.Insulating medium layer 24 has the sticking veneer 11 of comparing substrate 1 and is the outer surface 241 that the angle that is greater than 90 degree and is less than 180 degree is extended.In the present embodiment, this insulating medium layer 24 is also formed at part upper surface 213 simultaneously, and this part upper surface 213 is the part that in upper surface 213, electrode pad 216 is arrived in side surface 214 upper ends.The side surface 215 of outer surface 241Yu basic unit nude film 211 is parallel.
Incorporated by reference to Fig. 7, forming ink cabling 221(step S3), the pad 14 of substrate 1 is drawn and extended downward in side surface 215 outsides to the electrode pad 216 of the nude film 211 that this ink cabling 221 provides from S2 step.Ink cabling 221 is attached to the outer surface 241 of the insulating medium layer 24 of S21 step formation.In the present embodiment, the nude film 21Wei basic unit nude film 211 providing due to S2 step, so be called basic unit's ink cabling by the ink cabling 221 forming in this step.By foregoing description, can find out, basic unit's ink cabling 221 has the head end 223 of connecting electrode weld pad 216 and the tail end 224 that connects pad 14.Formed basic unit ink cabling 221 with mode moulding such as ink-jet or printings, and then accelerates processing by technology such as baking (temperature: 50 to 500 degrees Celsius) or ultraviolet illuminations by metal or alloy ink or conduction inorganic matter or conductive organic matter ink material.Basic unit's ink cabling 221 thickness between the hundreds of micron of several microns, width at several microns between hundreds of micron.In the present embodiment, basic unit's ink cabling 221 is individual layer setting.Really, the ink cabling forming in this step also can be the multilayer of stacked setting, and between the ink cabling Yu lower floor on multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting, be provided with insulating medium layer, and the pad 14 that the insulating medium layer that is positioned at lower floor and adjacent setting extends downward substrate 1 is drawn and attached to the electrode pad that is positioned at the nude film 211 that the ink cabling on upper strata provides from S2 step.
Incorporated by reference to Fig. 8, one nude film 212 is provided again, this nude film 212 have the upper surface 213 that is oppositely arranged with lower surface 214, be connected the side surface 215 of upper surface 213 and lower surface 214 and the electrode pad 216 outwards exposing from upper surface 213, and the lower surface of this nude film 212 214 is affixed to the upper surface 213(step S4 of nude film 211 that is stuck and is positioned at the top layer of substrate 1 top).The side surface 215 of nude film 212 is compared sticking veneer 11 and is the angle extension that is greater than 90 degree and is less than 180 degree.And the nude film 212 that is positioned at upper strata covers the electrode pad 216 of the lower floor's nude film 211 being adjacent along the orthographic projection of the thickness direction of nude film 21.In the present embodiment, the basic unit's nude film 211 being stuck in S2 step is the nude film 211 that was positioned at the top layer above substrate 1 in the present embodiment before this step S4, and after this step S4 completes, S4 step provides and the nude film 212 pasted becomes the nude film of top layer, in being the present embodiment of two-layer setting, being about to this nude film 212 and being called top layer nude film.So, the lower surface 213 of this top layer nude film 212 sticks on the upper surface 213 of basic unit's nude film 211, the side surface 215 of top layer nude film 212 is compared sticking veneer 11 and is the angle extension that is greater than 90 degree and is less than 180 degree, and top layer nude film 212 covers the electrode pad of basic unit's nude film 216 along the orthographic projection of the thickness direction of nude film 21.Owing to arranging on the upper surface 213 optional position of the electrode pad 216Ke basic unit nude film 211 of basic unit's nude film 211 and the electrode pad 216 of basic unit's nude film 211 is covered by top layer nude film 212 again, thereby make that high-density semiconductor encapsulating structure in the present embodiment has that size is little, the advantage such as thin thickness, high density and many pins.The electrode pad 216 of top layer nude film 212 can be arranged on the upper surface 213 optional position of this top layer nude film 212.Top layer nude film 212 is fixed on the upper surface 213 of basic unit's nude film 211 by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin as adhesive, thereby is provided with the tack coat 23 forming by above-mentioned adhesive between the upper surface 213 of basic unit's nude film 211 and the lower surface 214 of top layer nude film 212.The nude film 211 tapered stacked settings of top layer nude film 212Yu basic unit.
Incorporated by reference to Fig. 9, S4 step, after the nude film 212 again providing is provided in stickup, forms insulating medium layer 24(step S41 on the side surface 215 of the nude film 212 providing at step S4).Insulating medium layer 24 has the sticking veneer 11 of comparing substrate 1 and is the outer surface 241 that the angle that is greater than 90 degree and is less than 180 degree is extended.Formed insulating medium layer 24 first by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin as material with method moulding such as ink-jet or printings, and then accelerates processing through technology such as overbaking (temperature: 100 to 400 degrees Celsius) or ultraviolet illuminations.Its thickness is between several microns to tens microns.In the present embodiment, the insulating medium layer 24 forming in this step is also formed on the part upper surface 213 of top layer nude film 212 simultaneously, and this part upper surface 213 is the part that in upper surface 213, electrode pad 216 is arrived in side surface 215 upper ends.Outer surface 241 is parallel with the side surface 213 of top layer nude film 212.
Incorporated by reference to Figure 10, again form ink cabling 222, it is adjacent and be positioned on the established ink cabling 221 of lower floor or pad 14 (step S5) that nude film 212 that S4 step provides is drawn and extended downward to the electrode pad 216 of the nude film 212 that this ink cabling 222 provides from S4 step.The ink cabling 222 forming in this step is attached on the outer surface 241 of the insulating medium layer 24 that S41 step forms.In the present embodiment, the nude film 212 providing due to S4 step is top layer nude film, so, the ink cabling 222 forming in this step is called to top layer ink cabling.By foregoing description, can find out, top layer ink cabling 222 has the head end 223 of connecting electrode weld pad 216 and the tail end 224 that connects pad 14.The head end 223 of top layer ink cabling 222 is connected in the electrode pad 216 of top layer nude film 212, and 224 of its tail ends are connected in basic unit's ink cabling 221.Along in the horizontal direction of nude film 21, the tail end 224 of top layer ink cabling 222 is positioned at the outside of basic unit's ink cabling 221 head ends 223.Except the present embodiment, this top layer ink cabling 222 also can be connected directly to pad 14.Formed top layer ink cabling 222 with mode moulding such as ink-jet or printings, and then accelerates processing by technology such as baking (temperature: 50 to 500 degrees Celsius) or ultraviolet illuminations by metal or alloy ink or conduction inorganic matter or conductive organic matter ink material.Top layer ink cabling 222 thickness between the hundreds of micron of several microns, width at several microns between hundreds of micron.
In the present embodiment, this top layer ink cabling 222 is individual layer setting.Really, the multilayer that the ink cabling again forming is stacked setting, and between the ink cabling Yu lower floor on this multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting, be provided with insulating medium layer, the electrode pad that is positioned at the nude film that the ink cabling on upper strata provides from S5 step is drawn and is attached the insulating medium layer that is positioned at lower floor and adjacent setting and extends downward ink cabling that S3 step forms or the pad of substrate.
At this, it should be noted that: also can Bu basic unit nude film 211 in of the present invention and top layer nude film 212 on form insulating medium layer 24, but basic unit's ink cabling 221 and top layer ink cabling 222 are formed directly on basic unit's nude film 211 and top layer nude film 212.In such cases, basic unit's ink cabling 221 and top layer ink cabling 222 are directly attached at respectively the side surface 215 of basic unit's nude film 211 and top layer nude film 212.And its generation type and the present embodiment are basic identical, therefore no longer describe at this.
Basic unit's ink cabling 221 of above-mentioned basic unit nude film 211, top layer nude film 212,Yu basic unit nude film 211 and the 212 corresponding settings of top layer nude film and top layer ink cabling 222 and tack coat 23 and insulating medium layer 24 compositions are arranged on the nude film module on substrate 1.In the present embodiment, the stacked setting of tapered two-layer that nude film module Jin You basic unit nude film 211 and top layer nude film 212 form.But except this structure, can also adopt irregular setting.Nude film in nude film module also can be for more than two-layer, that is, and and the stacked nude film that arranges some layers again on top layer nude film 212 in the present embodiment.And every layer of nude film 21 in nude film module can comprise the sub-nude film that several are set up in parallel, between every sub-nude film, by tack coat, connect, this tack coat can be identical with the tack coat 23 in embodiment mono-.High-density semiconductor encapsulating structure in enforcement two shown in Figure 11, in this embodiment, nude film 21 is irregular setting and in the nude film of the bottom, includes two sub-nude films (not label).
Form two-layer above method for packing basic identical to S5 step with the S4 step in embodiment mono-, that is: repeat S4 step to S5 step with form multilayer nude film with every layer of ink cabling that nude film is corresponding.
Method for packing by above-specified high density semiconductor package has advantages of that technique is simple, the cycle is short, environmental protection and easily realizing.
Refer to Figure 12,13, the high-density semiconductor encapsulating structure in the embodiment of the present invention three comprises substrate 1 and is arranged on the nude film module on substrate 1.The nude film 21 ' that nude film module comprises two stacked settings be formed on every layer of nude film 21 ' to be connected levels nude film 21 ' or to connect some ink cablings of nude film 21 ' and pad 14 and be arranged on the tack coat 23 ' on every layer of nude film 21 '.Because part-structure in the present embodiment is identical with embodiment mono-, therefore same section is no longer described in detail.
Basic unit's nude film 211 ' that nude film 21 ' comprises tapered stacked setting is identical with top layer nude film 212 ' structure with top layer nude film 212’， basic unit nude film 211 ', and size is different.The size of basic unit's nude film 211 ' is greater than top layer nude film 212 '.Basic unit's nude film 211 ' and top layer nude film 212 ' all have the upper surface 213 ' that is oppositely arranged with lower surface 214 ', be connected the side surface 215 ' of upper surface 213 ' and lower surface 214 ' and the electrode pad 216 ' outwards exposing from upper surface 213 '.In this enforcement, this side surface 215 ' is compared the angle extension that sticking veneer 11 is all 90 degree.Except the present embodiment, this side surface 215 ' also can be compared sticking veneer 11 and is the angle extension that is greater than 0 degree and is less than 90 degree.
Tack coat 23 ' is formed by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.It is coated on the lower surface 214 ' and side surface 215 ' of nude film 21 '.One of its object is basic unit's nude film 211 ' to be fixed on substrate 1, top layer nude film 212 ' is fixed on basic unit's nude film 211 '.Two of object is to form on the outside of the lateral surface 215 ' of nude film 21 ' compares the outer surface 231 ' that sticking veneer 11 is the angle extension that is greater than 90 degree and is less than 180 degree, thereby is beneficial to the moulding of ink cabling.In the present embodiment, along the thickness direction of nude film 21 ', the electrode pad of basic unit's nude film 211 ' 216 ' is covered in the orthographic projection of tack coat 23 '.Certainly, except basic unit's nude film 211 ' electrode pad 216 ' is covered in the orthographic projection by tack coat 23 ', also can be by electrode pad 216 ' by inner setting, i.e. basic unit's nude film 211 ' electrode pad 216 ' is covered in the orthographic projection of top layer nude film 222 '.Because electrode pad 216 ' can distribute arbitrarily at upper surface 213 ', so that the overall dimensions of the high-density semiconductor encapsulating structure of the present embodiment is little, thin thickness, high density and many pins.
Ink cabling comprises basic unit's ink cabling 221 and top layer ink cabling 222, the outside that the electrode pad 216 ' of ink cabling 221Zi basic unit of basic unit nude film 211 ' is drawn the side surface 215 ' of Bing basic unit nude film 211 ' extends downward the pad 14 of substrate 1, and top layer ink cabling 222 is drawn and extends downward basic unit's ink cabling 222 in the outside of the side surface 215 ' of top layer nude film 212 ' from the electrode pad 216 ' of top layer nude film 212 '.The present embodiment Zhong basic unit ink cabling 221 and top layer ink cabling 222 are attached at respectively on the outer surface 231 ' with the tack coat 23 ' of the nude film 21 ' of its respective layer.With embodiment Yi， basic unit ink cabling 221 and top layer ink cabling 222, there is respectively head end 223 and tail end 224.And along the horizontal direction of nude film 21, the tail end 224 of top layer ink cabling 222 is positioned at the outside of basic unit's ink cabling 221 head ends 223.Same same embodiment mono-, the tail end 224 of this top layer ink cabling 222 also can directly be connected with pad 14.
In the present embodiment, with embodiment mono-, basic unit's ink cabling 221 and top layer ink cabling 222 basic unit's ink cablings 221 and top layer ink cabling 222 are individual layer setting, really, the ink cabling being formed on every layer of nude film also can be the multilayer of stacked setting, and is provided with insulating medium layer between the ink cabling of this multilayer ink cabling Zhong upper strata ink cabling Yu lower floor and adjacent setting.
The tapered stacked setting of nude film module in the present embodiment, but except this structure, nude film module also can adopt irregular setting.Nude film module also can be arranged to two-layer more than, that is, top layer nude film in the present embodiment 212 ' is upper at the stacked nude film 21 ' that arranges some layers.And every layer of nude film 21 ' in nude film module can comprise the sub-nude film that several are set up in parallel, between every sub-nude film, by tack coat, connect, this tack coat can be identical with the tack coat 23 ' in embodiment tri-.High-density semiconductor encapsulating structure in enforcement four shown in Figure 19, in this embodiment, nude film 21 ' is irregular setting and in the nude film of the bottom, includes two sub-nude films.
The optional position of upper surface that ink cabling connects owing to adopting, the electrode pad of every layer of nude film is arranged on every layer of nude film and the nude film on upper strata or tack coat cover the electrode pad of the nude film of the lower floor being adjacent along the orthographic projection of the thickness direction of nude film, so the high-density semiconductor encapsulating structure in the present embodiment has advantages such as size is little, thin thickness, high density, many pins.
Below incorporated by reference to seeing that the implementation step schematic diagram shown in Figure 14 to Figure 18 is described in detail the method for packing of the high-density semiconductor encapsulating structure in embodiment tri-.
Incorporated by reference to Figure 14, provide substrate 1(step S1), substrate 1 have the first surface that is oppositely arranged with second surface 12, be connected the 3rd surface 13 of first surface and second surface 12 and the pad 14 outwards exposing from first surface, owing to nude film 21 need being set on first surface in subsequent step, so this first surface is as sticking veneer 11.
Incorporated by reference to Figure 15, a nude film 211 ' is provided and this nude film 211 ' is adhered to (step S2) on substrate 1.Nude film 211 ' have the upper surface 213 ' that is oppositely arranged with lower surface 214 ', be connected the side surface 215 ' of upper surface 213 ' and lower surface 214 ' and the electrode pad 216 ' outwards exposing from upper surface 213 '.This electrode pad 216 ' can be arranged on the upper surface 213’ optional position of this nude film 211 ', in this enforcement, and the outer setting of this electrode pad 216 '.Nude film 211 ' adheres on the sticking veneer 11 of substrate 1 by lower surface 213 '.Because this nude film 211 ' adheres on substrate 1, so using this nude film 211 ' as basic unit's nude film.
In above-mentioned S2 step, basic unit's nude film 211 ' is realized in the following way with the bonding of substrate 1: on the sticking veneer 11 of substrate 1, adhesive is set, the lower surface of basic unit's nude film 211 ' 214 ' is placed on to adhesive Shang Bingjiang basic unit nude film 211 ' and towards substrate 1 direction, presses and cause adhesive and overflow and the side surface 215 ' of coated basic unit nude film 211 ' from the lower surface 214 ' of sticking veneer 11He basic unit nude film 211 ', thereby form to have, compare the tack coat 23 ' that sticking veneer 11 is the outer surface 231 ' that the angle that is greater than 90 degree and is less than 180 degree extends.The lower surface 214 ' that is self-adhesion veneer 11He basic unit nude film 211 ' due to tack coat 23 ' overflows and is coated on the outer surface 231 ' of basic unit's nude film 211 ', so comparing sticking veneer 11, this side surface 215 ' is the angle extension that is greater than 0 degree and is less than or equal to 90 degree, in the present embodiment, this side surface 215 ' is compared the angle extension that sticking veneer 11 is 90 degree.This tack coat 23 ' is polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
In the present embodiment, S2 step completes in stickup the nude film 221 ' providing and also comprises afterwards: on the part upper surface 213 of the nude film 221 ' providing in S2 step, form insulating medium layer 24 ', insulating medium layer 24 ' is positioned between the side surface 215’ upper end and electrode pad 216 ' of the nude film 221 ' that S2 step provides.
Refer to Figure 16, form ink cabling 221, the pad 14(step S3 of substrate 1 is drawn and extended downward in edge surface 215 outsides to the electrode pad 216 ' of the nude film 211 ' that this ink cabling 221 provides from S2 step).This ink cabling 221 is attached on the outer surface 231 ' of the tack coat 23 ' forming in S2 step.The nude film 21’Wei basic unit nude film 211 ' providing due to S2 step, so be called basic unit's ink cabling by the ink cabling 221 forming in this step.By foregoing description, can find out, basic unit's ink cabling 221 has the head end 223 of connecting electrode weld pad 216 and the tail end 224 that connects pad 14.Formed basic unit ink cabling 221 with mode moulding such as ink-jet or printings, and then accelerates processing by technology such as baking (temperature: 50 to 500 degrees Celsius) or ultraviolet illuminations by metal or alloy ink or conduction inorganic matter or conductive organic matter ink material.Basic unit's ink cabling 221 thickness between the hundreds of micron of several microns, width at several microns between hundreds of micron.
In the present embodiment, basic unit's ink cabling 221 is individual layer setting.Really, the ink cabling forming in this step also can be the multilayer of stacked setting, between the ink cabling Yu lower floor on this multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting, be provided with insulating medium layer, and the pad 14 that the insulating medium layer that is positioned at lower floor and adjacent setting extends downward substrate 1 is drawn and attached to the electrode pad that is positioned at the nude film 211 ' that the ink cabling on upper strata provides from S2 step.
Incorporated by reference to Figure 17, one nude film 212 ' is provided again, this nude film 212 ' also have the upper surface 213 ' that is oppositely arranged with lower surface 214 ', be connected the side surface 215 ' of upper surface 213 ' and lower surface 214 ' and the electrode pad 216 ' outwards exposing from upper surface 213 ', and the lower surface of this nude film 212 ' is affixed to the upper surface 213 ' (step S4) of nude film 211 ' that is stuck and is positioned at the top layer of substrate 1 ' top.And the nude film 212 ' or the tack coat 23 ' that are positioned at upper strata cover the electrode pad of the nude film 211 ' of the lower floor being adjacent 216 ' along the orthographic projection of the thickness direction of nude film 21 '.In the present embodiment, be stuck and be arranged in basic unit's nude film 211 ' that the nude film of the top layer of substrate 1 top provides for S2 step, and after this step S4 completes, S4 step provides and the nude film 212 ' pasted becomes the nude film of top layer, in being the present embodiment of two-layer setting, being about to this nude film 212 ' and being called top layer nude film.So the lower surface 213 ' of this top layer nude film 212 ' sticks on the upper surface 213 ' of basic unit's nude film 211 ', and the electrode pad of basic unit's nude film 211 ' 216 ' is covered along the orthographic projection of the thickness direction of nude film 21 ' by tack coat 23 '.
In the present embodiment, S4 step completes in stickup the nude film 222 ' providing and also comprises afterwards: on the part upper surface of the nude film 222 ' providing in S4 step, form insulating medium layer 24 ', insulating medium layer 24 ' is positioned between the side surface 215 ' and electrode pad 216 ' of the nude film 222 ' that S4 step provides
In above-mentioned S4 step, the stickup of top layer nude film 212’Yu basic unit nude film 211 ' realizes in the following way: on the upper surface 214 ' of basic unit's nude film 211 ', adhesive is set, the lower surface of top layer nude film 212 ' 214 ' is placed in adhesive and top layer nude film 212 ' is pressed and caused adhesive from the upper surface 214 ' of basic unit's nude film 211 ' and the lower surface 214 ' of top layer nude film 212 ' overflows and the side surface 215 ' of coated top layer nude film 212 ' towards substrate 1 direction, thereby form to have and compare the tack coat 23 ' that sticking veneer 11 is the outer surface 231 ' of the angle extension that is greater than 90 degree and is less than 180 degree.Because the upper surface 214 ' of tack coat 23’Shi Zi basic unit nude film 211 ' and the lower surface 214 ' of top layer nude film 222 ' overflow and are coated on the side surface 215 ' of top layer nude film 222 ', so comparing sticking veneer 11, the side surface 215 ' of this top layer nude film 222 ' is the angle extension that is greater than 0 degree and is less than or equal to 90 degree, in the present embodiment, this side surface 215 ' is compared the angle extension that sticking veneer 11 is 90 degree.This tack coat 23 ' is polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
Incorporated by reference to Figure 18, again form ink cabling 222, it is adjacent and be positioned on the pad 14 of the established ink cabling 221 of lower floor or substrate 1 (step S5) that this ink cabling 222 draws and extend downward from the electrode pad 216 ' of the nude film 212 ' providing with S4 step nude film 212 ' that S4 step provides.The ink cabling 221 forming in this step is attached on the outer surface 231 ' of the tack coat 23 ' that S4 step forms.In the present embodiment, the nude film 212 ' providing due to S4 step is called top layer nude film, so, the ink cabling 222 forming in this step is called to top layer ink cabling.By foregoing description, can find out, top layer ink cabling 222 has the head end 223 of connecting electrode weld pad 216 ' and the tail end 224 that connects pad 14.The head end 223 of top layer ink cabling 222 is connected in the electrode pad 216 ' of top layer nude film 212, and 224 of its tail ends are connected in basic unit's ink cabling 221.Along in the horizontal direction of nude film 21, the tail end 224 of top layer ink cabling 222 is positioned at the outside of basic unit's ink cabling 221 head ends 223.Except the present embodiment, it is not shown that this top layer ink cabling 222 also can be connected directly to pad 14().Formed top layer ink cabling 222 with mode moulding such as ink-jet or printings, and then accelerates processing by technology such as baking (temperature: 50 to 500 degrees Celsius) or ultraviolet illuminations by metal or alloy ink or conduction inorganic matter or conductive organic matter ink material.Basic unit's ink cabling 221 thickness between the hundreds of micron of several microns, width at several microns between hundreds of micron.
Basic unit's ink cabling 221 of above-mentioned basic unit nude film 211 ', top layer nude film 212’,Yu basic unit nude film 211 ' and the 212 ' the corresponding setting of top layer nude film and top layer ink cabling 222 and tack coat 23 ' composition are arranged on the nude film module on substrate 1.In the present embodiment, the tapered stacked setting of nude film module Jin You basic unit nude film 211 ' and the 212 ' formation of top layer nude film is two-layer.But except this structure, can also adopt irregular setting.Nude film module also can be for more than two-layer, i.e. the stacked nude film that arranges some layers again on top layer nude film 212 ' in the present embodiment.And every layer of nude film in nude film module can comprise the sub-nude film that several are set up in parallel, between every sub-nude film, by tack coat 23 ', connect, this tack coat can be identical with the tack coat in the present embodiment.High-density semiconductor encapsulating structure in enforcement four shown in Figure 19, in this embodiment, nude film 21 ' is irregular setting and in the nude film of the bottom, includes two sub-nude films.
In the present embodiment, this top layer ink cabling 222 is individual layer setting.Really, in above-mentioned steps, the multilayer that the ink cabling again forming is stacked setting, and between the ink cabling Yu lower floor on this multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting, be provided with insulating medium layer, the electrode pad that is positioned at the nude film that the ink cabling on upper strata provides from S5 step is drawn and is attached the insulating medium layer that is positioned at lower floor and adjacent setting and extends downward ink cabling that S3 step forms or the pad of substrate.
Form two-layer above method for packing basic identical to S5 step with the S4 step in embodiment mono-, that is: repeat S4 step to S5 step with form multilayer nude film with every layer of ink cabling that nude film is corresponding.
In sum, by adopting the method for packing of high-density semiconductor encapsulating structure of the present invention successively to encapsulate nude film 21 and its corresponding ink cabling 221,222, can make thus the electrode pad 216 on nude film 21 arbitrarily arrange, can be positioned at the lateral margin of nude film 21, also reliable centre position arranges; The ink cabling 221,222 being simultaneously arranged on same nude film 21 also can carry out stacked setting according to the closeness of electrode pad 216, thereby form have that size is little, the high-density semiconductor encapsulating structure of thin thickness, high density, many pins advantage, and this kind method for packing technique is simple, the cycle is short, environmental protection and easily realizing.
Although be example object, the preferred embodiment of the present invention is disclosed, but those of ordinary skill in the art will recognize, in the situation that not departing from by the disclosed scope and spirit of the present invention of appending claims, various improvement, increase and replacement are possible.
Claims (19)
1. a method for packing for high-density semiconductor encapsulating structure, is characterized in that: described method for packing comprises the steps:
S1, provide substrate, there is sticking veneer and Self-adhesive towards the pad of outer exposure;
S2, provide at least one nude film, described nude film has upper surface and the side surface of lower surface, connection upper surface and lower surface and the electrode pad outwards exposing from lower surface being oppositely arranged, described at least one nude film is affixed on described substrate, and the lower surface of described nude film adheres on described sticking veneer;
S3, formation ink cabling, the pad of described substrate is drawn and extended downward in side surface outside to the electrode pad of the nude film that described ink cabling provides from S2 step;
S4, again provide at least one nude film, this nude film also has the side surface of the upper surface that is oppositely arranged and lower surface, connection upper surface and lower surface and the electrode pad outwards exposing from lower surface, and the lower surface of this at least one nude film is affixed to the upper surface of nude film that is stuck and is positioned at the top layer of substrate top;
S5, again form ink cabling, it is adjacent and be positioned on the pad of the established ink cabling of lower floor or described substrate that this ink cabling draws and extend downward from the electrode pad of the nude film providing with S4 step the nude film providing with S4 step.
2. the method for packing of high-density semiconductor encapsulating structure according to claim 1, is characterized in that: repeat S4 step and S5 step with form multilayer nude film with every layer of ink cabling that nude film is corresponding.
3. the method for packing of high-density semiconductor encapsulating structure according to claim 1 and 2, it is characterized in that: the side surface of the nude film that described S2 step provides is compared sticking veneer and is the angle extension that is greater than 90 degree and is less than 180 degree, the side surface of the nude film that described S4 step provides is compared sticking veneer and is the angle extension that is greater than 90 degree and is less than 180 degree.
4. the method for packing of high-density semiconductor encapsulating structure according to claim 3, is characterized in that: the nude film on described upper strata covers the electrode pad of the nude film of the lower floor being adjacent along the orthographic projection of the thickness direction of described nude film.
5. the method for packing of high-density semiconductor encapsulating structure according to claim 3, it is characterized in that: the ink cabling that described S3 step forms is attached at the side surface of the nude film that S2 step provides, the ink cabling that described S5 step forms is attached at the side surface of the nude film that S4 step provides.
6. the method for packing of high-density semiconductor encapsulating structure according to claim 3, it is characterized in that: in S2 step, S5 step, the described nude film providing is all fixed on the sticking veneer of the substrate that is positioned at its downside and is adjacent or the upper surface of nude film as adhesive by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin, to form adhesive layer at each nude film with between its downside the substrate being adjacent or nude film.
7. the method for packing of high-density semiconductor encapsulating structure according to claim 6, it is characterized in that: described S2 step also comprises S21 after the nude film providing is provided in stickup, the outside of the side surface of the nude film providing in S2 step forms has the insulating medium layer that is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree compared to the sticking veneer of described substrate; The ink cabling that described S3 step forms is attached on the outer surface of the insulating medium layer that described S21 step forms; Described S4 step also comprises S41 after the nude film again providing is provided in stickup, forms and have the insulating medium layer that is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree compared to the sticking veneer of described substrate on the side surface of the nude film providing in S4 step; The ink cabling that described S5 step forms is attached on the outer surface of the insulating medium layer that described S41 step forms.
8. the method for packing of high-density semiconductor encapsulating structure according to claim 7, is characterized in that: described insulating medium layer is by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin method moulding with ink-jet or printing as material.
9. the method for packing of high-density semiconductor encapsulating structure according to claim 1 and 2, it is characterized in that: in described S2 step, the described at least one nude film providing and the bonding of substrate realize in the following way: on the sticking veneer of substrate, adhesive is set, the lower surface of described nude film is placed in adhesive and nude film is pressed and caused adhesive and from the lower surface of sticking veneer and nude film, overflow and be coated the side surface of nude film towards orientation substrate, to form to have, compare the tack coat that sticking veneer is the outer surface that the angle that is greater than 90 degree and is less than 180 degree extends, in described S4 step, the nude film that described S4 step provides is realized in the following way with the bonding of upper surface being stuck and be positioned at the top layer nude film of substrate top: in being stuck and being positioned on the upper surface of top layer nude film of substrate top, adhesive is set, the lower surface of the nude film that S4 step is provided is placed in adhesive and it is pressed and cause adhesive from being stuck and being positioned at the side surface that the upper surface of top layer nude film of substrate top and the lower surface of the nude film that S4 step provides overflow and be coated the nude film that S4 step provides towards orientation substrate, to form to have, compare the tack coat that sticking veneer is the outer surface of the angle extension that is greater than 90 degree and is less than 180 degree.
10. the method for packing of high-density semiconductor encapsulating structure according to claim 9, is characterized in that: the ink cabling that described S3 step forms is attached on the outer surface of the tack coat that described S2 step forms; The ink cabling that described S5 step forms is attached on the outer surface of the tack coat that described S4 step forms.
The method for packing of 11. high-density semiconductor encapsulating structures according to claim 9, is characterized in that: the side surface of the nude film that described S2 step provides is compared sticking veneer and is the angle extension that is greater than 0 degree and is less than or equal to 90 degree.
The method for packing of 12. high-density semiconductor encapsulating structures according to claim 9, is characterized in that: described tack coat is: polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
The method for packing of 13. high-density semiconductor encapsulating structures according to claim 9, is characterized in that: the nude film on described upper strata or tack coat cover the electrode pad of the nude film of the lower floor being adjacent along the orthographic projection of the thickness direction of described nude film.
The method for packing of 14. high-density semiconductor encapsulating structures according to claim 9, it is characterized in that: described S2 step also comprises after the nude film providing is provided in stickup: on the part upper surface of the nude film providing in S2 step, form insulating medium layer, between the upper end and electrode pad of the side surface of the nude film that described insulating medium layer provides in S2 step; Described S4 step also comprises after the nude film providing is provided in stickup: on the part upper surface of the nude film providing in S4 step, form insulating medium layer, between the upper end and electrode pad of the side surface of the nude film that described insulating medium layer provides in S4 step.
The method for packing of 15. high-density semiconductor encapsulating structures according to claim 1, it is characterized in that: described ink cabling has head end and the connection pad of connecting electrode weld pad or is positioned at the tail end of the ink cabling of its lower floor, and described upper strata ink cabling tail end is along the outside that is positioned at coupled lower floor's ink cabling head end in the horizontal direction of nude film.
The method for packing of 16. high-density semiconductor encapsulating structures according to claim 1, is characterized in that: the nude film that is positioned at described substrate top is tapered stacked setting.
The method for packing of 17. high-density semiconductor encapsulating structures according to claim 1, it is characterized in that: the nude film that is positioned at described substrate top is stacked setting, every layer of nude film comprises the sub-nude film that several are set up in parallel, and between the some sub-nude film in same layer, is provided with interconnective tack coat.
The method for packing of 18. high-density semiconductor encapsulating structures according to claim 1, is characterized in that: described ink cabling is by metal or alloy ink or conduction inorganic matter or conduct electricity organic oil ink material with ink-jet or mode of printing moulding.
The method for packing of 19. high-density semiconductor encapsulating structures according to claim 1, it is characterized in that: in described S3 or S5 step, the multilayer that described ink cabling is stacked setting, and be provided with insulating medium layer between the ink cabling Yu lower floor on multilayer ink cabling Zhong upper strata and the ink cabling of adjacent setting.
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| CN107444614A (en) * | 2017-09-08 | 2017-12-08 | 中国民航大学 | Suitable for the aerofoil flexibility plasma drag reduction paster of small-sized Fixed Wing AirVehicle |
| CN110376768A (en) * | 2019-07-26 | 2019-10-25 | 中国科学院半导体研究所 | The encapsulating structure of lithium niobate modulator and application, opto-electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104485291B (en) * | 2014-12-23 | 2018-06-05 | 通富微电子股份有限公司 | A kind of semiconductor laminated method for packing |
| CN107444614A (en) * | 2017-09-08 | 2017-12-08 | 中国民航大学 | Suitable for the aerofoil flexibility plasma drag reduction paster of small-sized Fixed Wing AirVehicle |
| CN110376768A (en) * | 2019-07-26 | 2019-10-25 | 中国科学院半导体研究所 | The encapsulating structure of lithium niobate modulator and application, opto-electronic device |
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