CN103501190B - Electric line carrier communication circuit - Google Patents
Electric line carrier communication circuit Download PDFInfo
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- CN103501190B CN103501190B CN201310480619.2A CN201310480619A CN103501190B CN 103501190 B CN103501190 B CN 103501190B CN 201310480619 A CN201310480619 A CN 201310480619A CN 103501190 B CN103501190 B CN 103501190B
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Abstract
The present invention relates to electric line carrier communication circuit, for power line communication, it discloses by central control circuit (1), synchronization signal processing circuit (2), signal receiving circuit (3), signal transmission circuit (4), power supply processing circuit (5), External Functionality Interface circuit (6), full bridge rectifier (7) forms.Advantage of the present invention is rational in infrastructure, and antijamming capability is strong, and the initial sum position of rest utilizing the rise and fall of carrier wave interval to formulate transfer of data makes message transmission rate improve and stablizes.
Description
Technical field
The present invention relates to power line communication, specifically a kind of electric line carrier communication circuit utilizing the rising of just profound carrier wave and last transition all to transmit data.
Background technology
Power line carrier communication is a kind of technological means of being carried out simulation or digital information transmission by existing power line, due to the stability of communication, make full use of the advantages such as existing power line road network to be used widely, as Smart Home, remote power table is checked meter, light fixture controls etc., power line carrier communication product generally designs and all includes central control module, synchronizing signal processing module, signal receiving module, signal emission module, power module, external interface module etc., as the record at China Patent Publication No. CN102006101A, wherein open by voltage doubling unit and respectively unit respectively to the double amplification of amplitude that the data-signal loaded from power line carries out successively, voltage division processing, thus most interference signal is removed, thus improve the reliability and stability of communication, but the stationarity of its antijamming capability and message transmission rate all has much room for improvement.
Summary of the invention
The object of this invention is to provide a kind of electric line carrier communication circuit, it is compared in existing like product higher antijamming capability, utilizes the rise and fall of carrier wave interval to formulate transfer of data initial sum position of rest and message transmission rate is improved and stablizes.
Technical solution of the present invention is in central control circuit (1), synchronization signal processing circuit (2), signal receiving circuit (3), signal transmission circuit (4), power supply processing circuit (5), on External Functionality Interface circuit (6) basis, be characterized in full bridge rectifier (7), full bridge rectifier (7) is by four diode D1, D2, D3, the bridge rectifier of D4 composition, the carrier signal incoming end of full bridge rectifier (7) is connected with AC power line interface CN2, the carrier signal output of full bridge rectifier (7) respectively with the input of synchronization signal processing circuit (2), the input of power supply processing circuit (5), the output of signal transmission circuit (4) is connected, carrier signal outputs to synchronization signal processing circuit (2) by after full bridge rectifier (7) full-bridge rectification, synchronization signal processing circuit (2) to after carrier signal process from SI hold output amplitude to meet carrier signal that central control circuit (1) requires to central control circuit (1), central control circuit (1) is transmission data start bit and decline stage according to carrier signal ascent stage is the PPM that transmission data position of rest formulates transfer of data, then central control circuit (1) exports and transmits data to signal transmission circuit (4), power line is uploaded to through full bridge rectifier (7) to CN2 interface again after signal transmission circuit (4) process.
Above-described central control circuit (1) by resistance R11, R12, crystal oscillator CY1, electric capacity C9, C10, integrated circuit (IC) 3 form, a termination 5V power supply of resistance R11,4 pin of another termination IC3; Crystal oscillator CY1 and resistance R12 is connected in parallel between 18 pin of IC3 and 17 pin; 18 pin of the one termination IC3 of electric capacity C9, other end ground connection; 17 pin of one termination IC3 of electric capacity 10, other end ground connection; 20 pin of IC3 are that data signal input is connected with the data output end DI of signal receiving circuit (3); 7 pin of IC3 are that data transmit output and are connected with the data input pin DO of signal transmission circuit (4); 19 pin of IC3 are carrier signal input and are connected with synchronization signal processing circuit (2) carrier signal output SI.
Synchronization signal processing circuit of the present invention (2) is made up of resistance R1, R2, R3, R4, R5, the negative pole of a termination full bridge rectifier (7) middle diode D3, D4 after resistance R1, R2, R3, R4 series connection, 19 pin of one end of other end connecting resistance R5 and the middle IC3 of central control circuit (1), the other end ground connection of resistance R5.
Signal receiving circuit of the present invention (3) by diode D7, D8, resistance R8, R13, R14, electric capacity C11, C12, C13, BAV99 pipe B1, inductance L 3, L4 form, the positive pole of diode D7, D8 is connected with the bipod of AC connectivity port CN2 respectively; After electric capacity C11 connects with inductance L 3, one end of electric capacity C11 is connected with one end of resistance R13 with the negative pole of diode D7, D8, and one end of inductance L 3 is connected with 3 pin of BAV99 pipe B1, the other end ground connection of resistance R13; Resistance R8 is in parallel with electric capacity C11; After electric capacity C12 is in parallel with inductance L 4, one end is connected with 3 pin of BAV99 pipe B1, other end ground connection; 1 pin and 2 of a termination BAV99 pipe B1 after resistance R14 and electric capacity C13 parallel connection, and be connected with 20 pin of IC3 in central control circuit (1), other end ground connection.
Signal transmission circuit of the present invention (4) is by diode D6, inductance L 2, electric capacity C6, C14, resistance R9, R10, field effect transistor Q1 forms, diode D6 positive pole is connected with the negative pole of diode D3, D4 of full bridge rectifier (7), and its negative pole is connected with one end of inductance L 2, and the other end of inductance L 2 is connected with the drain electrode of field effect transistor Q1; Electric capacity C6 is connected in parallel between the drain electrode of field effect transistor Q1 and source electrode; The source ground of field effect transistor Q1; Resistance R9 is connected in parallel between the grid of field effect transistor Q1 and source electrode; The grid of a termination field effect transistor Q1 after resistance R10 is in parallel with electric capacity C14, the other end is connected with 7 pin of IC3 in central control circuit (1).
Operation principle of the present invention obtains just profound carrier signal by full bridge rectifier (7) to be then input to central control circuit (1), central control circuit (1) according to zero point of just profound carrier wave half cycle and peak at carrier signal energy ascent stage as transmission data start bit, its decline stage is as the poor absolute time pulse position modulation (PPM) formulating transfer of data of absolute time of transmission data position of rest, thus formulation data transfer mode, and the data formulated are outputted to signal transmission circuit (4), upload to power line through full bridge rectifier (7) again after being processed by signal transmission circuit (4) and complete transfer of data, this mode improves transmission rate effectively, four diodes added in full bridge rectifier (7) circuit are ultrahigh speed diodes, full-bridge rectification of its composition also makes signal transmission circuit (4) can carry out accessiblely transmitting data to power line simultaneously, BAV99 pipe B1 is set in signal receiving circuit (3), the signal too low to signal amplitude limits, improve the antijamming capability of circuit.
Advantage of the present invention is rational in infrastructure, and antijamming capability is strong, and the initial sum position of rest utilizing the rise and fall of carrier wave interval to formulate transfer of data makes message transmission rate improve and stablizes.
Accompanying drawing explanation
Fig. 1 is frame structure schematic diagram of the present invention;
Fig. 2 is circuit theory diagrams of the present invention.
Embodiment
According to Fig. 1, shown in Fig. 2, central control circuit of the present invention (1), synchronization signal processing circuit (2), signal receiving circuit (3), signal transmission circuit (4), power supply processing circuit (5), External Functionality Interface circuit (6) is interconnected according to block diagram, be characterized in full bridge rectifier (7), at AC power line interface CN2 and synchronization signal processing circuit (2) input, signal transmission circuit (4) output, access full bridge rectifier (7) is added between power supply processing circuit (5) input, full bridge rectifier (7) is the ultrahigh speed diode D1 of (FR106) by four models, D2, D3, the bridge rectifier of D4 composition, it (is namely the L line that the negative pole of the D1 of diode and the positive pole of D3 connect the AC power line of CN2 interface that the carrier signal incoming end of full bridge rectifier (7) is connected with AC power line interface CN2, the negative pole of the D2 of diode and the positive pole of D4 connect the N line of the AC power line of CN2 interface), carrier signal output (the i.e. diode D3 of full bridge rectifier (7), the negative pole of D4) simultaneously with the input (being namely one end of resistance R1) of synchronization signal processing circuit (2), the input (being namely the positive pole of diode D5) of power supply processing circuit (5), the output (being namely the positive pole of diode D6) of signal transmission circuit (4) is connected, carrier signal outputs to synchronization signal processing circuit (2) by after full bridge rectifier (7) full-bridge rectification, synchronization signal processing circuit (2) carries out voltage division processing to carrier signal and guarantees carrier signal to be still just profound carrier signal be that its amplitude is different, and in the zone of reasonableness of voltage control IC3 in central control circuit (1), then from SI hold output amplitude to meet carrier signal that central control circuit (1) requires to 19 pin of IC3 central control circuit (1), the IC3 of central control circuit (1) is transmission data start bit and decline stage according to the carrier signal ascent stage is the PPM that transmission data position of rest formulates transfer of data, then central control circuit (1) outputs to the grid of field effect transistor Q1 signal transmission circuit (4) from 7 pin of IC3 according to the data of PPM coding needs transmission, after field effect transistor Q1 and interlock circuit, get back to CN2 interface through full bridge rectifier (7) again upload to power line.CN3 interface 1 pin of External Functionality Interface circuit (6) connects 24V power supply, 2 pin ground connection, 3 pin connect 5V power supply, 4,5,6,7,8,9,10,11,12 pin are connected with 8,9,10,11,12,13,14,3,4 pin of IC3 in central control circuit (1) respectively, and External Functionality Interface circuit (6) is main with connecting other peripheral function circuit such as the general key circuit of like product, control circuit, RS232 serial communication circuit.
Central control circuit (1) by resistance R11, R12, crystal oscillator CY1, electric capacity C9, C10, integrated circuit (IC) 3 form, and described IC3 is MICROCHIP series monolithic, a termination 5V power supply of resistance R11,4 pin of another termination IC3; Crystal oscillator CY1 and resistance R12 is connected in parallel between 18 pin of IC3 and 17 pin; 18 pin of the one termination IC3 of electric capacity C9, other end ground connection; 17 pin of one termination IC3 of electric capacity 10, other end ground connection; 20 pin of IC3 are that data signal input is connected with the data output end DI of signal receiving circuit (3); 7 pin of IC3 are that data transmit output and are connected with the data input pin DO of signal transmission circuit (4); 19 pin of IC3 are carrier signal input and are connected with synchronization signal processing circuit (2) carrier signal output SI.Its circuit function has: gather the signal of synchronization signal processing circuit (2), communication signal is received, calculate and sends, communicate with one another with the circuit such as key circuit, control circuit, RS232 serial communication circuit that external circuit is as general in: like product.
Synchronization signal processing circuit (2) is made up of resistance R1, R2, R3, R4, R5, the negative pole of a termination full bridge rectifier (7) middle diode D3, D4 after resistance R1, R2, R3, R4 series connection, 19 pin of one end of other end connecting resistance R5 and the middle IC3 of central control circuit (1), the other end ground connection of resistance R5.Its circuit function is: carry out voltage division processing to the just profound ripple after full-bridge rectification, thus the signal voltage guaranteeing the CPU IC3 being input to central control circuit (1) in the reasonable scope, and the carrier signal being input to CPU IC3 is still the just profound ripple after full-bridge rectification, just its amplitude is different.
Signal receiving circuit (3) by diode D7, D8, resistance R8, R13, R14, electric capacity C11, C12, C13, BAV99 pipe B1, inductance L 3, L4 form, the positive pole of diode D7, D8 is connected with the bipod of AC connectivity port CN2 respectively; After electric capacity C11 connects with inductance L 3, one end of electric capacity C11 is connected with one end of resistance R13 with the negative pole of diode D7, D8, and one end of inductance L 3 is connected with 3 pin of BAV99 pipe B1, the other end ground connection of resistance R13; Resistance R8 is in parallel with electric capacity C11; After electric capacity C12 is in parallel with inductance L 4, one end is connected with 3 pin of BAV99 pipe B1, other end ground connection; 1 pin and 2 of a termination BAV99 pipe B1 after resistance R14 and electric capacity C13 parallel connection, and be connected with 20 pin of IC3 in central control circuit (1), other end ground connection.Its circuit function has: carry out detection to the signal of bandwidth corresponding on power line, and the LC resonant circuit of electric capacity C11, C12 in circuit, inductance L 3, L4 composition L-type carries out resonance amplification to the signal of the frequency met; The BAV99 pipe B1 arranged in circuit is signal limiter effect, and the signal too low to amplitude limits thus improve the antijamming capability of circuit; Resistance R14, electric capacity C13 form the signal of RC resonance to input central control circuit (1) and carry out frequency-selective filtering, thus guarantee that its correctness of signal that DI end exports and amplitude are needs; Diode D7, D8 in circuit can guarantee signal receiving circuit (3) the electric power of CN2 interface be no matter just or reversal connection time can normally detection; Resistance R13 is release resistance, unnecessary or unwanted signal fault offset; The signal waveform exported at DI end is pulse, spike, the waveform such as just profound.
Signal transmission circuit (4) is by diode D6, inductance L 2, electric capacity C6, C14, resistance R9, R10, field effect transistor Q1 forms, diode D6 positive pole is connected with the negative pole of diode D3, D4 of full bridge rectifier (7), and its negative pole is connected with one end of inductance L 2, and the other end of inductance L 2 is connected with the drain electrode of field effect transistor Q1; Electric capacity C6 is connected in parallel between the drain electrode of field effect transistor Q1 and source electrode; The source ground of field effect transistor Q1; Resistance R9 is connected in parallel between the grid of field effect transistor Q1 and source electrode; The grid of a termination field effect transistor Q1 after resistance R10 is in parallel with electric capacity C14, the other end is connected with 7 pin of IC3 in central control circuit (1).Its circuit function has: the square-wave pulse signal of DO end input is converted into free harmonic vibration signal and is discharged on power line after full bridge rectifier (7) again, in circuit, inductance L 2 and electric capacity C6 form LC resonance; Field effect transistor Q1 is transmitting tube, also plays destruction resonance effect simultaneously; Electric capacity C14 is speed-up capacitor, switching speed when accelerating the signal of DO end thus guarantee that field effect transistor Q1 works.
Power supply processing circuit (5) is by diode D5, D9, D10, electric capacity C1, C2, C3, C4, C5, C7, C8, C15, inductance L 1, integrated circuit (IC) 1, IC2, resistance R6, R7, stabistor Z1 forms, and the positive pole of diode D5 connects the negative pole of diode D3, D4 in full bridge rectifier (7), and the negative pole direct type number of diode D5 is 8 pin of (VIPER22A) IC2; 8,7,6, the 5 pin short circuits of IC2; One end of electric capacity C1 and the negative pole of diode D5, other end ground connection; 1 pin of IC2 and 2 pin short circuits; Electric capacity C4 is connected in parallel between 1 pin of IC2 and 3 pin; Stabistor Z1 is connected in parallel between 3 pin of IC2 and 4 pin; Electric capacity C5 is connected in parallel between 1 pin of IC2 and 4 pin; The plus earth of diode D9, negative pole is connected with 1 pin of IC2; 1 pin of one termination IC2 of inductance L 2, one end of another termination capacitor C3, C7, resistance R6 and the positive pole of diode D10, the other end ground connection of electric capacity C3 and C7, one end of the negative pole connecting resistance R7 of diode D10,4 pin of another termination IC2 of resistance R7; The other end direct type number of resistance R6 is 1 pin of (LM78L05) IC1, the 2 pin ground connection of IC1; Electric capacity C8 is connected in parallel between 1 pin of IC1 and 2 pin; Electric capacity C15, C2 are connected in parallel between 3 pin of IC1 and 2 pin.Its circuit function is: other circuit provides 24VDC and 5VDC two kinds of voltages, and diode D5 plays one-way conduction effect when being connected with full bridge rectifier (7), and 1,2,19,20 pin of described IC3 are IO functional pins; 3,4,8,9,10,11,12,13,14 pin of IC3 are GPIO functional pins; 17,18 pin of IC3 are OSC functional pins; 5,6 pin of IC3 are VSS functional pins; 15,16 pin of IC3 are VCC functional pins.
Protection scope of the present invention should not be limited to above embodiment, " IC3 of central control circuit (1) is transmission data start bit and decline stage according to the carrier signal ascent stage is the PPM that transmission data position of rest formulates transfer of data, and then central control circuit (1) needs the data of transmission according to PPM coding " content according to recording in the embodiment of the present invention can inspire those skilled in the art to obtain this kind of data transfer mode by other circuit structure; Same basis " the BAV99 pipe B1 arranged in circuit is signal limiter effect; the signal too low to amplitude limits thus improve the antijamming capability of circuit " content can inspire those skilled in the art to obtain this kind of Anti-interference Design by other element of the same type or elements combination, and above-described enlightening content should belong to the row of protection scope of the present invention.
Claims (5)
1. electric line carrier communication circuit, it comprises central control circuit (1), synchronization signal processing circuit (2), signal receiving circuit (3), signal transmission circuit (4), power supply processing circuit (5), External Functionality Interface circuit (6), full bridge rectifier (7), it is characterized in that full bridge rectifier (7) is by four ultrahigh speed diode D1, D2, D3, the bridge rectifier of D4 composition, the carrier signal incoming end of full bridge rectifier (7) is connected with AC power line interface CN2, the carrier signal output of full bridge rectifier (7) respectively with the input of synchronization signal processing circuit (2), the input of power supply processing circuit (5), the output of signal transmission circuit (4) is connected, carrier signal outputs to synchronization signal processing circuit (2) by after full bridge rectifier (7) full-bridge rectification, synchronization signal processing circuit (2) to after carrier signal process from SI hold output amplitude to meet carrier signal that central control circuit (1) requires to central control circuit (1), the IC3 of central control circuit (1) is MICROCHIP series monolithic, be transmission data start bit and decline stage according to carrier signal ascent stage be the PPM that transmission data position of rest formulates transfer of data, then central control circuit (1) exports and transmits data to signal transmission circuit (4), power line is uploaded to through full bridge rectifier (7) to CN2 interface again after signal transmission circuit (4) process.
2. electric line carrier communication circuit according to claim 1, it is characterized in that described central control circuit (1) is by resistance R11, R12, crystal oscillator CY1, electric capacity C9, C10, integrated circuit (IC) 3 form, the one termination 5V power supply of resistance R11,4 pin of another termination IC3; Crystal oscillator CY1 and resistance R12 is connected in parallel between 18 pin of IC3 and 17 pin; 18 pin of the one termination IC3 of electric capacity C9, other end ground connection; 17 pin of one termination IC3 of electric capacity 10, other end ground connection; 20 pin of IC3 are that data signal input is connected with the data output end DI of signal receiving circuit (3); 7 pin of IC3 are that data transmit output and are connected with the data input pin DO of signal transmission circuit (4); 19 pin of IC3 are carrier signal input and are connected with synchronization signal processing circuit (2) carrier signal output SI, and 1,2,19,20 pin of described IC3 are IO functional pins; 3,4,8,9,10,11,12,13,14 pin of IC3 are GPIO functional pins; 17,18 pin of IC3 are OSC functional pins; 5,6 pin of IC3 are VSS functional pins; 15,16 pin of IC3 are VCC functional pins.
3. electric line carrier communication circuit according to claim 1, it is characterized in that described synchronization signal processing circuit (2) is made up of resistance R1, R2, R3, R4, R5, the negative pole of a termination full bridge rectifier (7) middle diode D3, D4 after resistance R1, R2, R3, R4 series connection, 19 pin of one end of other end connecting resistance R5 and the middle IC3 of central control circuit (1), the other end ground connection of resistance R5,19 pin of described IC3 are IO functional pins.
4. electric line carrier communication circuit according to claim 1, it is characterized in that described signal receiving circuit (3) is by diode D7, D8, resistance R8, R13, R14, electric capacity C11, C12, C13, BAV99 pipe B1, inductance L 3, L4 form, and the positive pole of diode D7, D8 is connected with the bipod of AC connectivity port CN2 respectively; After electric capacity C11 connects with inductance L 3, one end of electric capacity C11 is connected with one end of resistance R13 with the negative pole of diode D7, D8, and one end of inductance L 3 is connected with 3 pin of BAV99 pipe B1, the other end ground connection of resistance R13; Resistance R8 is in parallel with electric capacity C11; After electric capacity C12 is in parallel with inductance L 4, one end is connected with 3 pin of BAV99 pipe B1, other end ground connection; 1 pin of a termination BAV99 pipe B1 and 2 pin after resistance R14 and electric capacity C13 parallel connection, and be connected with 20 pin of IC3 in central control circuit (1), other end ground connection, 20 pin of described IC3 are IO functional pins.
5. electric line carrier communication circuit according to claim 1, it is characterized in that described signal transmission circuit (4) is by diode D6, inductance L 2, electric capacity C6, C14, resistance R9, R10, field effect transistor Q1 forms, and diode D6 positive pole is connected with the negative pole of diode D3, D4 of full bridge rectifier (7), its negative pole is connected with one end of inductance L 2, and the other end of inductance L 2 is connected with the drain electrode of field effect transistor Q1; Electric capacity C6 is connected in parallel between the drain electrode of field effect transistor Q1 and source electrode; The source ground of field effect transistor Q1; Resistance R9 is connected in parallel between the grid of field effect transistor Q1 and source electrode; The grid of a termination field effect transistor Q1 after resistance R10 is in parallel with electric capacity C14, the other end is connected with 7 pin of IC3 in central control circuit (1), and 7 pin of described IC3 are GPIO functional pins.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310480619.2A CN103501190B (en) | 2013-10-15 | 2013-10-15 | Electric line carrier communication circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310480619.2A CN103501190B (en) | 2013-10-15 | 2013-10-15 | Electric line carrier communication circuit |
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| CN103501190A CN103501190A (en) | 2014-01-08 |
| CN103501190B true CN103501190B (en) | 2016-04-20 |
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| CN105227126A (en) * | 2014-06-03 | 2016-01-06 | 北京动力源科技股份有限公司 | A kind of photovoltaic module power optimizer and there is the photovoltaic generating system of this optimizer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4734919A (en) * | 1981-02-20 | 1988-03-29 | Gold Star Tele-Electric Co., Ltd. Incorporated | Circuit for serial data communication and power transmission |
| CN102006101A (en) * | 2010-12-27 | 2011-04-06 | 东莞市华业新科电子科技有限公司 | Power line carrier communication module |
| CN203193587U (en) * | 2013-04-18 | 2013-09-11 | 北京爱朗格瑞科技有限公司 | Voltage quadrant identification circuit |
| CN203596819U (en) * | 2013-10-15 | 2014-05-14 | 东莞市华业新科电子科技有限公司 | Power line carrier wave communication circuit |
-
2013
- 2013-10-15 CN CN201310480619.2A patent/CN103501190B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4734919A (en) * | 1981-02-20 | 1988-03-29 | Gold Star Tele-Electric Co., Ltd. Incorporated | Circuit for serial data communication and power transmission |
| CN102006101A (en) * | 2010-12-27 | 2011-04-06 | 东莞市华业新科电子科技有限公司 | Power line carrier communication module |
| CN203193587U (en) * | 2013-04-18 | 2013-09-11 | 北京爱朗格瑞科技有限公司 | Voltage quadrant identification circuit |
| CN203596819U (en) * | 2013-10-15 | 2014-05-14 | 东莞市华业新科电子科技有限公司 | Power line carrier wave communication circuit |
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