CN103490782B

CN103490782B - Capacitance type comparator averaging circuit

Info

Publication number: CN103490782B
Application number: CN201310381503.3A
Authority: CN
Inventors: 刘雄
Original assignee: SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Current assignee: SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Priority date: 2013-08-29
Filing date: 2013-08-29
Publication date: 2017-01-18
Anticipated expiration: 2033-08-29
Also published as: CN103490782A

Abstract

The invention discloses a capacitance type comparator averaging circuit. The capacitance type comparator averaging circuit is composed of a first comparator, a second comparator and a third comparator, wherein the first-level p end output of the second comparator is connected with the second-level p end input of the first comparator and the second-level p end input of the third comparator, the second-level p end input of the second comparator is connected with the first-level p end output of the first comparator and the first-level p end output of the third comparator, the first-level n end output of the second comparator is connected with the second-level n end input of the first comparator and the second-level n end input of the third comparator, and the second-level n end input of the second comparator is connected with the first-level n end output of the first comparator and the first-level n end output of the third comparator. According to the capacitance type comparator averaging circuit, averaging is achieved by means of capacitance, interference to the DC bias of the amplification stage of each comparator is avoided, averaging strength and distribution can be achieved through adjustment of the capacitance of the comparators on the same layer, the capacitance connected to an upper layer and the capacitance connected to a lower layer, and then influence of thermal noise is reduced on the whole.

Description

A kind of comparator capacitor averaging circuit

Technical field

The present invention relates to a kind of average circuit, more particularly, to a kind of comparator capacitor averaging circuit.

Background technology

Analog to digital conversion circuit refers to circuit analogue signal being compared according to reference voltage and quantifying, wherein, core Device is comparator circuit.

Described comparator circuit refers to the circuit that applied signal voltage and reference voltage are compared, and is output as height, table Bright input signal is higher than reference voltage.Vice versa.Main consideration index is drifted about for input direct-current, input noise, bandwidth etc.. Input direct-current drifts about, and input noise determines the precision of quantization, determines the digit of analog digital conversion together with reference voltage, and such as 8 Position analog digital conversion.The bandwidth of comparator determines the speed of analog digital conversion.Described input direct-current drift is main in cmos device Refer to the threshold voltage inputting, due to various physical factors, refer in the different cmos device of two causing input Threshold voltage different.Certainly in audion and other techniques, the not equal other factors of current amplification factor also result in input DC shift.And input noise is the mainly thermal noise of device and the flicker noise in cmos device middle finger.

In order to reduce the impact of thermal noise and input direct-current drift, people devise flash analog digital conversion, its inside Comparator circuit as shown in Figure 1, constitutes comparator array by multiple comparators, in order to reduce the defeated of afterbody latch circuit Enter DC shift and input noise, mainly adopt multilevel hierarchy, under conditions of ensureing bandwidth, input differential signal is progressively put Greatly；Adopt two-stage pre1 and pre2 to amplify in Fig. 1, but amplifying circuit inherently has own noise and input direct-current drift；For Reduce the input direct-current drift of amplifying circuit, general using output auto zero, or input auto zero；Output is returned automatically Zero error and the gain switching of amplifying circuit are smaller, adopt relatively more typically in high-speed comparator, or input is automatically Zero needs big amplifying circuit gain, typically using relatively more in low speed comparator.

In auto zero, drifting about through the own input direct-current amplifying of output will be stored in electric capacity；In normal work When making, the error brought with input direct-current drift is automatically deducted by the voltage difference at electric capacity two ends, thus realizing no input direct-current The effect of the amplification of drift.

In Fig. 1, this technology is employed to amplifier stage pre1 naturally it is also possible to this technology is adopted to pre2.But adopting should Technology can affect bandwidth and comparator area, if adopts, and using how many levels, is determined by the requirement designing.

The flicker noise of the low speed to amplifier for the above-mentioned technology, equally functions similarly to the effect of input direct-current drift.But For the thermal noise of high frequency, the particularly noise of sample frequency odd-multiple, tend not to play suppression, or even play amplification and make With.

Content of the invention

The technical problem to be solved is to provide one kind and can reduce thermal noise impact and realize no inputting directly The comparator capacitor averaging circuit of stream drift.

In order to solve above-mentioned technical problem, the present invention is achieved by the following technical solutions: a kind of comparator condenser paper All circuit, are made up of first comparator, the second comparator and the 3rd comparator, each comparator by the first amplifier stage pre1, Second amplifier stage pre2 and latch circuit latch are in series, and described first amplifier stage pre1 is provided with the output of first order p end With the output of first order n end, the output of described first order p end and the output of first order n end respectively be arranged on the second amplifier stage pre2 The second level p end input and the second level n end input connect, and the first order p end output with the second level p end input and first order n Respectively be in series with an electric capacity between end output and the input of second level n end, the output of first order p end on described second comparator respectively with Second level p end input in first comparator and the 3rd comparator connects, the input of second level p end on the second comparator respectively with First order p end output in first comparator and the 3rd comparator connects；On second comparator the first order n end output respectively with Second level n end input in first comparator and the 3rd comparator connects, and on the second comparator, the input of second level n end is respectively with the First order n end output on one comparator and the 3rd comparator connects.

Preferably, the in the first order p end output on described second comparator and first comparator and the 3rd comparator Between the input of two grades of p ends, and the in the second level p end input on the second comparator and first comparator and the 3rd comparator Between the output of one-level p end, and the in the first order n end output on the second comparator and first comparator and the 3rd comparator Between two grades of n end inputs, and the first order in the input of the second comparator second level n end and first comparator and the 3rd comparator Respectively it is in series with an electric capacity between the output of n end.

Compared with prior art, usefulness of the present invention is: this comparator capacitor averaging circuit to be put down using electric capacity All, interference, average intensity and distribution will not be produced to the direct current biasing of the amplifier stage of comparator, can be by adjusting this layer ratio To realize compared with the size of the electric capacity on device and the electric capacity being coupled with upper strata, lower floor, to reduce the impact of thermal noise on the whole.

Brief description:

The present invention is further described below in conjunction with the accompanying drawings.

Fig. 1 is the comparator circuit structural representation of existing flash analog to digital conversion circuit；

Fig. 2 is this comparator capacitor averaging electrical block diagram.

In figure: 1, first comparator；2nd, the second comparator；3rd, the 3rd comparator；11st, 21,31, first order p end output； 12nd, 22,32, second level p end input；13rd, 23,33, first order n end output；14th, 24,34, second level n end input.

Specific embodiment:

Below in conjunction with the accompanying drawings and specific embodiment describes the present invention:

A kind of comparator capacitor averaging circuit shown in Fig. 2, by first comparator 1, the second comparator 2 and the 3rd comparator 3 Constitute, each comparator is in series by the first amplifier stage pre1, the second amplifier stage pre2 and latch circuit latch, described The output of first order p end and the output of first order n end, the output of described first order p end and first order n are provided with the first amplifier stage pre1 End output is connected with the second level p end input being arranged on the second amplifier stage pre2 and the input of second level n end respectively, and the first order Respectively it is in series with an electric capacity, it is special between the output of p end and the input of second level p end and the output of first order n end and the input of second level n end Levy and be: first order p end on described second comparator 2 output 21 respectively with first comparator 1 and the 3rd comparator 3 on the Two grades of p end input 12,32 connections, the second level p end input 22 on the second comparator 2 is compared with first comparator 1 and the 3rd respectively Compared with first order p end output 11,31 connection on device 3；First order n end output 23 on second comparator 2 is compared with first respectively On device 1 and the 3rd comparator 3 the second level n end input 14,34 connection, on the second comparator 2 second level n end input 24 respectively with First order n end output 13,33 connection in first comparator 1 and the 3rd comparator 3.

On described second comparator 2 in first order p end output 21 and first comparator 1 and the 3rd comparator 3 second Between level p end input 12,32, and the second level p end input 22 on the second comparator 2 is compared with first comparator 1 and the 3rd Between first order p end output 11,31 on device 3, and the first order n end output 23 on the second comparator 2 and first comparator 1 With the 3rd between the second level n end input 14,34 on comparator 3, and the second comparator 2 second level n end input 24 and first Respectively it is in series with an electric capacity between first order n end output 13,33 on comparator 1 and the 3rd comparator 3.

This comparator capacitor averaging circuit adopts electric capacity average, and the direct current biasing of the amplifier stage of comparator will not be produced Raw interference, average intensity and distribution, can be by adjusting the electric capacity on this layer of comparator and the electricity being coupled with upper strata, lower floor The size held, to realize, reduces the impact of thermal noise on the whole.

It is emphasized that: the above is only presently preferred embodiments of the present invention, not the present invention is made any formal Restriction, any simple modification, equivalent variations and modification that every technical spirit according to the present invention is made to above example, All still fall within the range of technical solution of the present invention.

Claims

1. a kind of comparator capacitor averaging circuit, by first comparator (1), the second comparator (2) and the 3rd comparator (3) structure Become, each comparator is in series by the first amplifier stage pre1, the second amplifier stage pre2 and latch circuit latch, described the The output of first order p end and the output of first order n end, the output of described first order p end and first order n end are provided with one amplifier stage pre1 Output is connected with the second level p end input being arranged on the second amplifier stage pre2 and the input of second level n end respectively, and first order p Respectively it is in series with an electric capacity, it is special between end output and the input of second level p end and the output of first order n end and the input of second level n end Levy and be: first order p end on described second comparator (2) output (21) respectively with first comparator (1) and the 3rd comparator (3) second level p end input (12,32) on connects, and second level p end on the second comparator (2) input (22) is respectively with first First order p end output (11,31) on comparator (1) and the 3rd comparator (3) connects；First order n on second comparator (2) End output (23) is connected with second level n end input (14,34) in first comparator (1) and the 3rd comparator (3) respectively, and second Upper second level n end input (24) of comparator (2) is defeated with the first order n end in first comparator (1) and the 3rd comparator (3) respectively Go out (13,33) to connect；Comparator capacitor averaging circuit adopts electric capacity average, average intensity and distribution, by adjusting this layer Electric capacity on comparator and be coupled with upper strata, lower floor electric capacity size realizing.

2. comparator capacitor averaging circuit according to claim 1, is characterized in that, on described second comparator (2) Between second level p end input (12,32) on one-level p end output (21) and first comparator (1) and the 3rd comparator (3), with And second first order p in second level p end input (22) on comparator (2) and first comparator (1) and the 3rd comparator (3) Between end output (11,31), and first order n end output (23) on the second comparator (2) and first comparator (1) and the 3rd Between second level n end input (14,34) on comparator (3), and the second comparator (2) second level n end input (24) and the Respectively it is in series with an electric capacity between first order n end output (13,33) on one comparator (1) and the 3rd comparator (3).