CN103490601A - DCM Boost PFC converter for low-output voltage ripples - Google Patents

DCM Boost PFC converter for low-output voltage ripples Download PDF

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CN103490601A
CN103490601A CN201310424284.2A CN201310424284A CN103490601A CN 103490601 A CN103490601 A CN 103490601A CN 201310424284 A CN201310424284 A CN 201310424284A CN 103490601 A CN103490601 A CN 103490601A
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resistance
input
circuit
output
operational amplifier
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姚凯
李强
阮新波
胡文斌
毕晓鹏
付晓勇
孟庆赛
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a DCM Boost PFC converter for low-output voltage ripples. The DCM Boost PFC converter comprises a main power circuit and a control circuit. An output end A of a first bleeder circuit of the control circuit is connected to a peak sampling circuit, a first multiplying unit and an input end of a subtraction circuit, an output end B of the peak sampling circuit is connected with a third input end of the first multiplying unit, an output end C of a second bleeder circuit is connected to a first input end of the first multiplying unit and a third input end of a second multiplying unit, an output end D of the first multiplying unit is connected to an input end of a summing circuit, an output end E of the subtraction circuit is connected with another input end of the summing circuit, an output end F of the summing circuit is connected with a first input end of the second multiplying unit, an output end of an error control circuit is connected with a second input end of the second multiplying unit, and an output end P of the second multiplying unit is connected to a door electrode of a main power circuit switching tube Qb after being sequentially driven by a PWM IC chip and a switching tube. According to the DCM Boost PFC converter for the low-output voltage ripples, the output voltage ripples are reduced, the threshold inductance value can be increased, and the conversion efficiency is improved.

Description

The DCM Boost pfc converter of low output voltage ripple
Technical field
The present invention relates to the DCM Boost pfc converter in the A.C.-D.C. converter field of electrical energy changer, particularly a kind of low output voltage ripple.
Background technology
Power factor correction (Power factor correction, PFC) converter can reduce Harmonics of Input, improve input power factor, be used widely, DCM Boost pfc converter has switching tube zero current turning-on, diode without the advantage such as oppositely recovering and switching frequency is constant, but, when within half input cycle, duty ratio is constant, Harmonics of Input content is larger.Input current mainly contains the triple-frequency harmonics with fundamental current phase place phase difference of pi, and not only power factor is lower, and makes the input power pulsation become large, thereby output voltage ripple is high, needs larger output storage capacitor.
Summary of the invention
To the objective of the invention is in order keeping under the DCM Boost pfc converter PF value prerequisite substantially constant with the Changing Pattern of input voltage, to reduce output voltage ripple or output storage capacitor.
The technical solution that realizes the object of the invention is: a kind of DCM Boost pfc converter of low output voltage ripple, comprise main power circuit and control circuit, and described main power circuit comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L b, switching tube Q b, diode D b, storage capacitor C o, load R ld, input voltage source v wherein inwith the input port of electromagnetic interface filter, be connected, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L ban end connect, the Boost inductance L bthe other end access respectively switching tube Q bdrain electrode and diode D banode, switching tube Q bsource electrode with reference potential, be connected zero point, diode D bnegative electrode access respectively storage capacitor C oanode and load R ldan end, storage capacitor C onegative electrode and load R ldthe other end all with reference potential, be connected zero point, load R ldboth end voltage be output voltage V o; Described control circuit comprises that the first bleeder circuit, peak sample circuit, the second bleeder circuit, the first multiplier, subtraction circuit, add circuit, regulating error circuit, the second multiplier, PWM IC chip, switching tube drive, and wherein the output terminals A of the first bleeder circuit accesses respectively the input of peak sample circuit, the second input v of the first multiplier ywith the input of subtraction circuit, the 3rd input v of the output B of peak sample circuit and the first multiplier zconnect, the output C of the second bleeder circuit accesses respectively the first input end v of the first multiplier x, the second multiplier the 3rd input v z, the output D of the first multiplier is connected with an input of add circuit, and the output E of subtraction circuit is connected with another input of add circuit, the output F of add circuit and the first input end v of the second multiplier xconnect the output v of regulating error circuit eAthe second input v with the second multiplier ybe connected, the output P of the second multiplier is connected with the input of PWM IC chip, and the output of PWM IC chip is connected with the input that switching tube drives, output and switching tube Q that switching tube drives bgate pole connect.
Compared with prior art, its remarkable advantage is in the present invention: under (1) prerequisite that the Changing Pattern of PF value is substantially constant within keeping whole input voltage range, reduced output voltage ripple or output storage capacitor; (2) can reduce conduction loss, improve conversion efficiency.
The accompanying drawing explanation:
Fig. 1 is Boost pfc converter main circuit schematic diagram.
Fig. 2 is the inductive current oscillogram of DCM Boost pfc converter.
Fig. 3 is half input current waveform figure after the interior standardization of power frequency period.
Fig. 4 is the curve chart of power factor PF.
Fig. 5 is the instantaneous input power oscillogram of first-harmonic and 3 subharmonic.
Fig. 6 is the surface chart that concerns of power factor PF value and a and y0.
Fig. 7 be f ' (a) with f (a) curve comparison figure.
Fig. 8 is the electrical block diagram of DCM Boost pfc converter.
Fig. 9 is 3,5,7 subharmonic and the curve chart of the ratio of first-harmonic.
Figure 10 is the instantaneous input power perunit value curve chart of determining under the variable duty cycle control mode.
Figure 11 is the ratio curve chart of determining the output voltage ripple under the variable duty cycle control mode.
Figure 12 is the threshold inductance value curve chart under different input voltages.
Figure 13 is the ratio curve chart of the inductive current effective value under fixed empty Duty ratio control mode.
Embodiment
The operation principle of 1DCM Boost pfc converter
Fig. 1 is Boost pfc converter main circuit.Fig. 2 has provided the inductive current waveform that is operated in DCM.
Input ac voltage v in(t) expression formula is:
v in(t)=V msinωt (1)
In a power frequency period, as duty ratio D yin the time of fixedly, the mean value i that the efficiency of supposing converter is input current in 100%, one switch periods in, duty ratio D ywith power factor, PF is respectively:
i in ( t ) = V m D y 2 2 L b f s sin ωt 1 - V m | sin ωt | / V o - - - ( 2 )
D y = 1 V m 2 π L b f s P o ∫ 0 π sin 2 ωt 1 - V m | sin ωt | / V o dωt - - - ( 3 )
PF = 2 π ∫ 0 π sin 2 ωt 1 - V m | sin ωt | / V o dωt ∫ 0 π ( sin ωt 1 - V m | sin ωt | / V o ) 2 dωt - - - ( 4 )
V wherein mfor the amplitude of input ac voltage, the angular frequency that ω is input ac voltage, V ofor output voltage, P ofor power output, f sfor switching frequency, L bfor the Boost inductance value.
For easy analysis, by formula (2) standardization, (fiducial value is ) be can be made in different V m/ V oin situation, in half power frequency period waveform, as shown in Figure 3.Can find out, the shape of input current only and V m/ V orelevant, V m/ V oless, input current is more close to sine.This is that its mean value is sinusoidal form because of the inductive current ascent stage; And in the inductive current decline stage, descending slope and V m/ V orelevant, V m/ V oless, inductive current descends faster, and the mean value of this stage inductive current is more close to 0, thereby the mean value of electric current is more close to sine in whole switch periods, and the PF value is more approaching with 1.
Can make the curve of PF according to formula (4), as shown in Figure 4.As can be seen from the figure, V m/ V olarger, the PF value is lower.Work as V m/ V obe greater than at 0.9 o'clock, the PF value will be lower than 0.9.In 85V~265VAC input voltage range, when input voltage is 265VAC, output voltage while being 400V, the PF value only has 0.859.
In order to analyze the harmonic wave of input current, can carry out Fourier decomposition to it.The fourier decomposition form of input current is:
i in ( t ) = a 0 2 + Σ n = 1 ∞ [ a n cos ( nωt ) + b n sin ( nωt ) ] - - - ( 5 )
Wherein
a n = 2 T line ∫ 0 T line i in ( t ) cos ( nωt ) dωt ( n = 0,1,2 , . . . ) b n = 2 T line ∫ 0 T line i in ( t ) sin ( nωt ) dωt ( n = 1,2,3 . . . ) - - - ( 6 )
T lineit is the input voltage cycle.
By formula (2) substitution formula (5), can obtain as calculated the contained each harmonic of input current.Wherein, the sinusoidal composition of cosine and even is 0, that is:
a n=0(n=0,1,2,...) (7)
b n=0(n=2,4,6...)
Fig. 9 has provided curve that in the input current, the ratio of 3,5,7 subharmonic and first-harmonic changes with input voltage (if ratio, for negative, shows to calculate the b of gained nfor negative, the initial phase of this subharmonic and first-harmonic phase difference of pi).
As can be seen from Figure 9, in input current, mainly containing poor with fundamental phase is the triple-frequency harmonics of π, and input voltage is higher, and this triple-frequency harmonics content is larger.
The impact of 2 tertiary current harmonic waves on the input power pulsation
The input current first-harmonic i of pfc converter in1expression formula is
i in1(t)=I 1sinωt (8)
In formula, I 1amplitude for fundamental current.
The input instantaneous power p that fundamental current produces in1(t) be:
p in1(t)=v ini in1=V mI 1sin 2(ωt) (9)
If contain the triple-frequency harmonics i identical with the first-harmonic initial phase in input current in3, its expression formula is
i in3(t)=I 3sin(3ωt) (10)
In formula, I 3for the triple harmonic current amplitude.
The instantaneous input power p of this THIRD-HARMONIC GENERATION so in3for
p in3(t)=v ini in3=V mI 3sin(ωt)sin(3ωt) (11)
If the triple-frequency harmonics i that to contain with the first-harmonic initial phase difference in input current be π in3_ π, the instantaneous input power p of its expression formula and generation thereof so in3_ πexpression formula be respectively
i in3_π(t)=I 3sin(3ωt-π) (12)
p in3_π(t)=v ini in3_π=-V mI 3sin(ωt)sin(3ωt) (13)
According to formula (9), formula (11), formula (13), can make fundamental power p in1, the triple harmonic current i identical with the fundamental current initial phase in3power p in3, with the fundamental current initial phase difference triple harmonic current i that is π in3_ πpower p in3_ πwaveform, as Fig. 5.
The energy that when the dash area area in Fig. 5 represents PF=1, the output storage capacitor need to be stored.As can be seen from the figure, at T line/ 8~3T linein/8 scopes, with the fundamental current initial phase difference triple harmonic current i that is π in3_ πincreased the pulsation of input power, triple-frequency harmonics content is larger, and the input power pulsation of first-harmonic just is increased manyly, and the PF value is lower, and required output storage capacitor amount is also larger; And the triple harmonic current i identical with the fundamental current initial phase in3reduced the pulsation of input power, same triple-frequency harmonics content is larger, and the input power pulsation of first-harmonic just is reduced manyly, and required output storage capacitor amount is also less.We will analyze the mode of how to pass through to regulate duty ratio, inject a certain amount of and synchronous triple harmonic current of first-harmonic in the input current of DCM Boost pfc converter, to reach the purpose that significantly reduces to export storage capacitor, keep the Changing Pattern of PF value in whole input voltage range simultaneously and determine Duty ratio control basic identical.
3 inject a certain amount of triple-frequency harmonics in input current
3.1 desired duty cycle expression formula
If by certain control mode, inject a certain amount of triple-frequency harmonics identical with the fundamental current initial phase in input current, the expression formula of input current is
i in ( t ) = I 1 sin ωt + I 3 sin 3 ωt = I 1 ( sin ωt + I 3 * sin 3 ωt ) - - - ( 14 )
In formula, * be the perunit value of harmonic current to the fundamental current amplitude.
Now the input power factor PF of converter is
PF = 1 / 1 + I 3 * 2 - - - ( 15 )
By formula (4) and formula (15), can be released with V m/ V orelational expression, but formula (4) relative complex will be obtained with V m/ V orelation very difficult, simplify to obtain PF so can first to formula (4), carry out matching _ fit1
PF _ fit 1 = 1 - 0.968 a 1 - 0.952 a - - - ( 16 )
A=V wherein m/ V o, the input voltage that this paper adopts changes in the 85-265VAC scope, and output voltage is 400V, and a changes between 0.3 to 0.94.Formula (4) is substantially similar at the excursion inner curve of a to formula (16), as shown in Figure 4, can use formula (16) replacement formula (4).
By formula (15) and formula (16), can be obtained with the relational expression of a, be
I 3 * = ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 - - - ( 17 )
The efficiency of supposing converter is 100%, i.e. half interior Mean Input Power P of input cycle inequal power output P o, so
P in = P o = 1 π ∫ 0 π v in ( t ) i in ( t ) d ( ωt ) = 1 π ∫ 0 π V m sin ωt · I 1 ( sin ωt + I 3 * sin 3 ωt ) dωt = V m I 1 2 - - - ( 18 )
The input current expression formula that can be injected after triple-frequency harmonics by formula (14) and formula (18) is
i in ( t ) = 2 P o V m ( sin ωt + I 3 * sin 3 ωt ) - - - ( 19 )
Simultaneous formula (2) and formula (19), can obtain duty ratio should be by following variation
D y = D 0 ( 1 - a | sin ωt | ) ( 1 + I 3 * sin 3 ωt sin ωt ) = D 0 ( 1 - a | sin ωt | ) ( 1 + I 3 * 3 sin ωt - 4 sin 3 ωt sin ωt ) = D 0 ( 1 - a | sin ωt | ) ( 1 + 3 I 3 * - 4 I 3 * sin 2 ωt ) - - - ( 20 )
In formula D 0 = 2 L b f s P o / V m .
3.2 the fitting function of duty ratio
The duty ratio that formula (20) provides implements more complicated, needs to adopt a plurality of multipliers, divider and root circuit, therefore is necessary to simplify.
For simplicity, make y=|sin ω t|, formula (20) is:
D y = D 0 ( 1 - ay ) ( 1 + 3 I 3 * - 4 I 3 * y 2 ) - - - ( 21 )
By this function at y=y 0place carries out Taylor expansion, has:
D y = D 0 ( 1 - ay 0 ) ( 1 + 3 I 3 * - 4 I 3 * y 0 2 ) + 12 I 3 * ay 0 2 - 8 I 3 * y 0 - a ( 1 + 3 I 3 * ) 2 ( 1 - ay 0 ) ( 1 + 3 I 3 * - 4 I 3 * y 0 2 ) ( y - y 0 ) + . . . - - - ( 22 )
Ignore high-order term, first two that only get above formula are carried out matching, i.e. the duty ratio D ' of matching y_fitexpression formula is:
D y _ fit ′ = D 1 [ 1 - a ( 1 + 3 I 3 * ) + 8 I 3 * y 0 - 12 I 3 * ay 0 2 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 y ] - - - ( 23 )
In formula D 1 = D 0 · 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 2 ( 1 - ay 0 ) ( 1 + 3 I 3 * - 4 I 3 * y 0 2 ) .
By formula (23) substitution formula (2), can obtain input current and be:
i in ( t ) = V m D 1 2 2 L b f s sin ωt 1 - a | sin ωt | ( 1 - a ( 1 + 3 I 3 * ) + 8 I 3 * y 0 - 12 I 3 * ay 0 2 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 | sin ωt | ) 2 - - - ( 24 )
The efficiency of supposing converter is 100%, the Mean Input Power P of converter infor
P in = P o = 1 T line / 2 ∫ 0 T line / 2 v in ( t ) i in ( t ) dt = V m 2 D 1 2 2 π L b f s ∫ 0 π ( sin 2 ωt ) ( 1 - a ( 1 + 3 I 3 * ) + 8 I 3 * - 12 I 3 * ay 0 2 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 | sin ωt | ) 2 1 - a | sin ωt | d ( ωt ) - - - ( 25 )
By formula (24) and formula (25), can obtain the PF value suc as formula (26).
By formula (26), the known PF value of formula (17), except outside the Pass having with a, gone back and breaking up point y 0choose relevant.The suitable y of How to choose below is discussed 0, to use variable duty cycle to control gained PF value, farthest approach and determine Duty ratio control.
PF = P in V in _ rms I in _ rms = P in 1 2 V m 1 T line / 2 ∫ 0 T line / 2 ( i in ( t ) ) 2 dt = 2 π ∫ 0 π sin 2 ωt ( 1 - a ( 1 + 3 I 3 * ) + 8 I 3 * y 0 + 12 I 3 * ay 0 2 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 | sin ωt | ) 2 1 - a · | sin ωt | dωt ∫ 0 π sin 2 ωt ( 1 - a ( 1 + 3 I 3 * ) + 8 I 3 * y 0 - 12 I 3 * ay 0 2 2 ( 1 + 3 I 3 * ) - a ( 1 + 3 I 3 * ) y 0 - 4 I 3 * ay 0 3 | sin ωt | ) 4 ( 1 - a | sin ωt | ) 2 dωt - - - ( 26 )
V in formula in_rmsfor input voltage effective value, I in_rmsfor the input current effective value;
Make PF and a and y according to formula (26), (17) 0concern curved surface, as shown in Figure 6.Input voltage is higher, and the PF value is lower, therefore chooses y 0the time, overriding concern guarantees that when input voltage is the highest PF value under two kinds of control methods is identical, the time, make formula (4) equate with formula (26), can obtain y 0=0.8.
By y 0=0.8, formula (17) substitution formula (26), can make the curve PF of PF about a _ fit2, as Fig. 4.By y 0=0.8 with formula (17) substitution formula (23), can obtain D ' y_fitwith the relational expression of a, be
D y _ fu ′ = D 1 [ 1 - a ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) + 6.4 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 - 7.68 a ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 2 ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) - 0.8 a ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) - 2.048 a ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 | sin ωt | ] - - - ( 27 )
Realize the control that duty ratio changes by formula (27), still more complicated, so will be simplified formula (27), make
f ′ ( a ) = a ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) + 6.4 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 - 7.68 a ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 2 ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) - 0.8 a ( 1 + 3 ( 1 - 0.952 a 1 - 0.968 a ) 2 - 1 ) - 2.048 a ( 1 - 0.952 a 1 - 0 . 968 a ) 2 - 1 - - - ( 28 )
Make f ' curve (a) according to formula (28), as Fig. 7, how lower surface analysis uses simple expression formula to its matching.
This curve approaches straight line as can be seen from Figure 7, therefore considers, with straight line, it is carried out to matching, establishes the straight line expression formula and is
F (a)=ma+n (29) further to f ' tracing analysis (a) to determine the value of m, n in formula (29), near the input voltage peak, PF value for maximum proximity (27) gained after the assurance matching, can make straight line and f ' (a) intersect at place, and slope m equals (a) slope when input voltage is the highest of f ', can solve m=[d f ' (a)/da] | a=0.94=1.13, n=-0.149, thus f (a)=1.13a-0.149, as shown in Figure 7.
By fitting a straight line f (a) substitution formula (27), the duty ratio expression formula after can simplifying
D y _ fit = D 1 [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] - - - ( 30 )
By formula (1), formula (2) and formula (30) available power factor, be
PF fit 3 = P in V inrms I inrms = 1 T line / 2 ∫ 0 T line / 2 v in ( t ) i in ( t ) dt V m 2 1 T line / 2 ∫ 0 T line / 2 ( i in ( t ) ) 2 dt = 2 π ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 1 - a · | sin ωt | dωt ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 4 ( 1 - a | sin ωt | ) 2 dωt - - - ( 31 )
Can make PF according to formula (31) _ fit3about the curve of a, as shown in Figure 4.As can be seen from the figure, when input voltage is low, PF _ fit3higher than PF _ fit2, reason is as follows: low pressure when input, determine power factor under Duty ratio control relatively high and close to 1, thus the variable duty cycle of introducing be controlled at half interior excursion of power frequency period can not be too large, otherwise reduced on the contrary power factor.As shown in Figure 7, straight line f (a) at the low pressure place lower than curve f ' (a), compares with formula (27), and the excursion of the duty ratio of formula (30) gained in half power frequency period is less.
As seen from Figure 4, in whole input voltage range, input voltage one regularly, the power factor of variable duty cycle under controlling with determine that Duty ratio control equates substantially and slightly high.
3.3 control circuit
As Fig. 8, input voltage v gthrough resistance the first resistance R 1with the second resistance R 2dividing potential drop obtains v a=k vgv m| sin ω t|, k here vgit is the dividing potential drop coefficient.The 3rd resistance R 3, the 4th resistance R 4, the first diode D 1, the first capacitor C 1form the peak sample circuit, vB=k vgv m, output voltage V othrough the 5th resistance R 5with the 6th resistance R 6dividing potential drop obtains v c=k vgv o, can obtain the first multiplier and be output as v d=v av c/ v b=k vgv o| sin ω t|, v awith V oaccess subtraction circuit, wherein R 13/ (R 13+ R 15)=0.5k vg, R 14=1.3R 12, be output as v e=k vg(1.15V o-1.3k vgv m| sin ω t|).V dwith v eaccess add circuit, wherein R 7=R 8, R 10=6.6R 9, R 11=1.13R 9, be output as v f=k vg[V o-(1.13V m-0.149V o) | sin ω t|.Output voltage V oby the 16 resistance R 16with the 17 resistance R 17dividing potential drop, and given voltage V ogcompare, here V og=5.1V, R 16=77.43R 17, via the 18 resistance R 18with the second capacitor C 2the adjuster formed obtains error signal v eA, v f, v cwith v eAaccess the second multiplier, it exports v p=v eAv f/ v c=v eA[1-(1.13V m/ V o-0.149) | sin ω t|], by v phand over to cut with sawtooth waveforms and can obtain the duty ratio suc as formula Changing Pattern shown in (30).V wherein a, v b, v c, v d, v e, v f, v eA, v pbe respectively the output voltage of the first bleeder circuit 2, peak sample circuit 3, the second bleeder circuit 4, the first multiplier 5, subtraction circuit 6, add circuit 7, regulating error circuit 8, the second multiplier 9.
4 performance comparison
4.1 the variation of Harmonics of Input
By formula (30) substitution formula (2), the input current expression formula that can obtain under variable duty cycle control is
i in ( t ) = V m D 1 2 [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 2 L b f s sin ωt 1 - V m | sin ωt | / V o - - - ( 32 )
By a=V m/ V othe substitution above formula, work as V oduring=400V, simultaneous formula (32) and formula (6) can obtain variable duty cycle and control the curve of the ratio of 3,5,7 subharmonic and first-harmonic in lower input current with the input voltage variation, as Fig. 9.Can find out, compare with determining Duty ratio control, after adopting variable duty cycle to control, in whole input voltage range, regularly, 3 subharmonic sizes are substantially constant for input voltage one, single spin-echo, and 5 times and 7 subharmonic amplitudes reduce.
4.2 reducing of output voltage ripple
Adopt while determining Duty ratio control, can be obtained the instantaneous input power perunit value of converter by formula (1), formula (2) and formula (3) (fiducial value is power output) is:
p in _ 1 * ( t ) = v in ( t ) i in ( t ) P o = sin 2 ωt 1 - a | sin ωt | 1 π ∫ 0 π sin 2 ωt 1 - a | sin ωt | dωt - - - ( 33 )
While adopting variable duty cycle to control, the efficiency of supposing converter is 100%, can be obtained the instantaneous input power perunit value of converter by formula (1) and formula (32) (fiducial value is power output) is:
p in _ 2 * ( t ) = v in ( t ) · i in ( t ) P o = v in ( t ) · i in ( t ) 1 T line / 2 ∫ 0 T line / 2 v in ( t ) i in ( t ) dt = ( sin ωt ) 2 1 - a · | sin ωt | · [ 1 - ( 1.13 a - 0.149 ) · | sin ωt | ] 2 1 π · ∫ 0 π ( sin ωt ) 2 · [ 1 - ( 1.13 a - 0.149 ) · | sin ωt | ] 2 1 - a · sin ωt dωt - - - ( 34 )
Analysis from the 1st joint, input voltage is higher, the triple-frequency harmonics of determining the contained fundamental phase phase difference of pi of DCM Boost pfc converter input current under Duty ratio control is larger, input power pulsation is also larger, thereby the input power pulsation of output storage capacitor amount when the highest by input voltage determines.In whole input voltage 85-265VAC scope, when output voltage is 400V, a from 0.3 to 0.94, change.Get a=0.94, can make instantaneous input power perunit value under the two kinds of control modes change curve in half power frequency period by formula (33) and formula (34), as shown in figure 10.
When instantaneous input power perunit value the time, storage capacitor C ocharging; When the time, C oelectric discharge.Suppose from ω t=0, determine under Duty ratio control and variable duty cycle control the waveform time shaft coordinate corresponding with first intersection point of 1 be respectively t 1and t 2, storage capacitor C othe poor perunit value of the ceiling capacity stored in half power frequency period (fiducial value is half output energy in power frequency period) is respectively
Δ E 1 * = 2 ∫ 0 t 1 [ 1 - p in _ 1 * ( t ) ] dt / ( T line / 2 ) - - - ( 35 )
Δ E 2 * = 2 ∫ 0 t 2 [ 1 - p in _ 2 * ( t ) ] dt / ( T line / 2 ) - - - ( 36 )
According to the computing formula of capacitance energy storage, the poor perunit value of this ceiling capacity can be expressed as again
Δ E 1 * ≈ 1 2 C o ( V o + ΔV o 1 2 ) 2 - 1 2 C o ( V o - Δ V o 1 2 ) 2 P o T line / 2 = 2 C o V o Δ V o 1 P o T line - - - ( 37 )
Δ E 2 * ≈ 1 2 C o ( V o + Δ V o 2 2 ) 2 - 1 2 C o ( V o - Δ V o 2 2 ) 2 P o T line / 2 = 2 C o V o Δ V o 2 P o T line - - - ( 38 )
Δ V wherein o1for determining the output voltage ripple value under Duty ratio control, Δ V o2for the output voltage ripple value under variable duty cycle control.
By formula (35)-(38), can be obtained
Δ V o 1 = 2 P o ∫ 0 t 1 [ 1 - p in _ 1 * ( t ) ] dt / C o V o - - - ( 39 )
Δ V o 2 = 2 P o ∫ 0 t 2 [ 1 - p in _ 2 * ( t ) ] dt / C o V o - - - ( 40 )
Simultaneous formula (33), (34), (39), (40), and by a=V m/ V osubstitution, the design objective (will provide in the 5th joint) according to converter, can obtain Figure 11.
As can be seen from Figure 11, design objective according to this paper, when input voltage changes between 85-265VAC, the output voltage ripple of determining under Duty ratio control increases to 7.0V gradually from 4.6V, output voltage ripple under variable duty cycle control is reduced to 2.5V gradually from 4.3V, with determining Duty ratio control, compares, after adopting variable duty cycle to control, if keep storage capacitor appearance value constant, output voltage ripple reduces; If keep the maximum ripple of output voltage constant, the storage capacitor value can be reduced to original 61.4%.
4.3 the variation of the design of inductance and inductive current ripple
For making discontinuous current mode, must meet
D yV o/(V o-V m|sinωt|)≤1 (41)
By formula (3) substitution above formula, can determine the threshold inductance value L under Duty ratio control b1for
L b 1 ≤ ( 1 - a ) 2 V m 2 2 P o f s 1 π ∫ 0 π sin 2 ωt 1 - a | sin ωt | dωt - - - ( 42 )
The efficiency of supposing converter is 1, can be obtained the power output P of converter by formula (1) and formula (32) ofor
P o = P in 1 T line / 2 ∫ 0 T line / 2 v in ( t ) i in ( t ) dt = V m 2 D 1 2 2 π L b f s ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 1 - a | sin ωt | d ( ωt ) - - - ( 43 )
By formula (43), can be obtained
D 1 = 1 V m 2 π L b f s P o ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 1 - a | sin ωt | dωt - - - ( 44 )
By formula (44) substitution formula (30), obtain matching duty ratio D y_fitexpression formula is:
D yfit = 1 V m 2 π L b f s P o ( 1 - ( 1.13 a - 0.149 ) | sin ωt | ) ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 1 - a | sin ωt | d ( ωt ) - - - ( 45 )
By formula (45) substitution formula (41), can obtain the threshold inductance value L under variable duty cycle control b2for:
L b 2 ≤ V m 2 2 π P o f s ∫ 0 π sin 2 ωt [ 1 - ( 1.13 a - 0.149 ) | sin ωt | ] 2 1 - a · | sin ωt | d ( ωt ) [ 1 - ( 1.13 a - 0.149 ) | sin ωt | 1 - a | sin ωt | ] 2 - - - ( 46 )
The design objective of associative transformation device, can obtain Figure 12 by formula (42) and formula (46).Can find out, the threshold inductance value of determining under duty ratio and variable duty cycle control is respectively 92 μ H and 212 μ H.
Power frequency period internal inductance current effective value I lb_rmsfor:
I Lb _ rms = V m T s L b 2 T line ∫ 0 T line 2 V o D y 3 ( sin ωt ) 2 3 ( V o - V m | sin ωt | ) dt - - - ( 47 )
Guarantee certain design capacity, get the inductance value of determining under duty ratio and variable duty cycle control and be respectively L b1=80 μ H, L b2=200 μ H, the design objective of associative transformation device, by formula (3), L b1=80 μ H and formula (45), L b2=200 μ H are substitution formula (47) respectively, can determine the inductive current effective value I under Duty ratio control lb1_rms, the inductive current effective value I of variable duty cycle under controlling lb2_rms; By formula (45), L b1=80 μ H substitution formulas (47), the inductive current effective value I in the time of can keeping the threshold inductance value constant under variable duty cycle control lb3_rms, as shown in figure 13.As can be seen from the figure, with determining Duty ratio control, compare, after adopting variable duty cycle to control, because the threshold inductance value becomes large, the inductive current effective value reduces, and the current effective value of switching tube and diode is corresponding diminishing also, be conducive to reduce the conduction loss of converter, improve conversion efficiency.If keep inductance value constant, the inductive current effective value is substantially constant at the low pressure place, when input voltage is higher, increases.
5 the present invention adopt the triple-frequency harmonics injection method to reduce the Boost pfc converter of storage capacitor
In conjunction with Fig. 8, input voltage v gthrough resistance the first resistance R 1with the second resistance R 2dividing potential drop obtains v a=k vgv m| sin ω t|, k here vgit is the dividing potential drop coefficient.The 3rd resistance R 3, the 4th resistance R 4, the first diode D 1, the first capacitor C 1form the peak sample circuit, v b=k vgv m, output voltage V othrough the 5th resistance R 5with the 6th resistance R 6dividing potential drop obtains v c=k vgv o, can obtain the first multiplier and be output as v d=v av c/ v b=k vgv o| sin ω t|, v awith V oaccess subtraction circuit, wherein R 13/ (R 13+ R 15)=0.5k vg, R 14=1.3R 12, be output as v e=k vg(1.15V o-1.3kv gv m| sin ω t|).V dwith v eaccess add circuit, wherein R 7=R 8, R 10=6.6R 9, R 11=1.13R 9, be output as v f=k vg[V o-(1.13V m-0.149V o) | sin ω t|.Output voltage V oby the 16 resistance R 16with the 17 resistance R 17dividing potential drop, and given voltage V ogcompare, here V og=5.1V, R 16=77.43R 17, via the 18 resistance R 18with the second capacitor C 2the adjuster formed obtains error signal v eA, v f, v cwith v eAaccess the second multiplier, it exports v p=v eAv f/ vC=v eA[1-(1.13V m/ V o-0.149) | sin ω t|], by v phand over to cut with sawtooth waveforms and can obtain the duty ratio suc as formula Changing Pattern shown in (30).V wherein a, v b, v c, v d, v e, v f, v eA, v pbe respectively the output voltage of the first bleeder circuit 2, peak sample circuit 3, the second bleeder circuit 4, the first multiplier 5, subtraction circuit 6, add circuit 7, regulating error circuit 8, the second multiplier 9.Physical circuit is as follows:
The DCM Boost pfc converter of low output voltage ripple of the present invention, comprise main power circuit 1 and control circuit, and described main power circuit 1 comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L b, switching tube Q b, diode D b, storage capacitor C o, load R ld, input voltage source v wherein inwith the input port of electromagnetic interface filter, be connected, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L ban end connect, the Boost inductance L bthe other end access respectively switching tube Q bdrain electrode and diode D banode, switching tube Q bsource electrode with reference potential, be connected zero point, diode D bnegative electrode access respectively storage capacitor C oanode and load R ldan end, storage capacitor C onegative electrode and load R ldthe other end all with reference potential, be connected zero point, load R ldboth end voltage be output voltage V o; It is D that described control circuit adopts Changing Pattern 1the output signal driving switch pipe Q of the duty ratio of [1-(1.13a-0.149) | sin ω t|] bcomprise that the first bleeder circuit 2, peak sample circuit 3, the second bleeder circuit 4, the first multiplier 5, subtraction circuit 6, add circuit 7, regulating error circuit 8, the second multiplier 9, PWM IC chip 10, switching tube drive 11, wherein the output terminals A of the first bleeder circuit 2 accesses respectively the input of peak sample circuit 3, the second input v of the first multiplier 5 ywith the input of subtraction circuit 6, the 3rd input v of the output B of peak sample circuit 3 and the first multiplier 5 zconnect, the output C of the second bleeder circuit 4 accesses respectively the first input end v of the first multiplier 5 x, the second multiplier 9 the 3rd input v z, the output D of the first multiplier 5 is connected with an input of add circuit 7, and the output E of subtraction circuit 6 is connected with another input of add circuit 7, the first input end v of the output F of add circuit 7 and the second multiplier 9 xconnect the output v of regulating error circuit 8 eAthe second input v with the second multiplier 9 ybe connected, the output P of the second multiplier 9 is connected with the input of PWM IC chip 10, and the output of PWM IC chip 10 is connected with the input of switching tube driving 11, and switching tube drives 11 output and switching tube Q bgate pole connect.
Described the first bleeder circuit 2 comprises the first operational amplifier A 1, the first resistance R 1, the second resistance R 2; The first resistance R 1an end and input voltage sampled point V gthe output cathode that is diode rectifier circuit RB connects, the first resistance R 1the other end and the second resistance R 2one end connects and common port accesses the first operational amplifier A 1positive input, the second resistance R 2the other end with reference potential, be connected zero point, the first operational amplifier A 1reverse input end with output terminals A, directly be connected, form the in-phase voltage follower.
Described peak sample circuit 3 comprises the 3rd resistance R 3, the first diode D 1, the first capacitor C 1, the 4th resistance R 4, the second operational amplifier A 2; The 3rd resistance R wherein 3an end and the first operational amplifier A of the first bleeder circuit 2 1output terminals A connect, the 3rd resistance R 3the other end and the first diode D 1anodal series connection is by the first diode D 1negative pole access the second operational amplifier A 2normal phase input end, the first capacitor C 1with the 4th resistance R 4an end and the second operational amplifier A after in parallel 2normal phase input end be connected, another termination reference point position zero point, the second operational amplifier A 2inverting input with output B, directly be connected.
Described the second bleeder circuit 4 comprises the 5th resistance R 5with the 6th resistance R 6, the 5th resistance R wherein 5an end and the output voltage V of main power circuit 1 othe anodal connection, the 5th resistance R 5the other end and the 6th resistance R 6the output C that an end connects and its common port is the second bleeder circuit 4, the 6th resistance R 6other end access reference point position zero point.
Described subtraction circuit 6 comprises the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, four-operational amplifier A 4; The 15 resistance R wherein 15one end and output voltage V othe anodal connection, the other end is connected to four-operational amplifier A 4positive input, the 13 resistance R 13one end is connected to four-operational amplifier A 4positive input, the 13 resistance R 13the other end with reference potential, be connected zero point, the 12 resistance R 12one end is connected with the output terminals A of the first bleeder circuit 2, the 12 resistance R 12the other end and four-operational amplifier A 4reverse input end connect, the 14 resistance R 14be connected to four-operational amplifier A 4reverse input end and output E between.
Described add circuit 7 comprises the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 3rd operational amplifier A 3; The tenth resistance R wherein 10one end is connected with the output D of the first multiplier 5, other end access the 3rd operational amplifier A 3positive input, the 11 resistance R 11one end is connected with subtraction circuit 7 output E, other end access the 3rd operational amplifier A 3positive input, the 9th resistance R 9one end and the 3rd operational amplifier A 3positive input connect, other end access reference point position zero point, the 7th resistance R 7one termination enters the 3rd operational amplifier A 3reverse input end, other end access reference point position zero point, the 8th resistance R 8access the 3rd operational amplifier A 3reverse input end and output E between.
Described regulating error circuit 8 comprises the 16 resistance R 16, the 17 resistance R 17, the 18 resistance R 18, the second capacitor C 2, the 5th operational amplifier A 5; The 16 resistance R wherein 16one end and output voltage V oanodal connection, the other end and the 5th operational amplifier A 5reverse input end connect, the 17 resistance R 17one end and the 5th operational amplifier A 5reverse input end connect, other end access reference point position zero point, the 18 resistance R 18with the second capacitor C 2access the 5th operational amplifier A after series connection 5reverse input end and output between, the 5th operational amplifier A 5positive input and input voltage reference point V ogconnect.
In sum, the DCM Boost pfc converter of low output voltage ripple of the present invention, keep the PF value with the essentially identical prerequisite of the Changing Pattern of input voltage under, adopt variable duty cycle to control and realize in input current only containing a certain amount of triple-frequency harmonics identical with the first-harmonic initial phase, output voltage ripple or output storage capacitor had both been reduced, can also make the threshold inductance value increase, improve conversion efficiency.

Claims (7)

1. the DCM Boost pfc converter of a low output voltage ripple, is characterized in that, comprises main power circuit (1) and control circuit, and described main power circuit (1) comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L b, switching tube Q b, diode D b, storage capacitor C o, load R ld, input voltage source v wherein inwith the input port of electromagnetic interface filter, be connected, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L ban end connect, the Boost inductance L bthe other end access respectively switching tube Q bdrain electrode and diode D banode, switching tube Q bsource electrode with reference potential, be connected zero point, diode D bnegative electrode access respectively storage capacitor C oanode and load R ldan end, storage capacitor C onegative electrode and load R ldthe other end all with reference potential, be connected zero point, load R ldboth end voltage be output voltage V o; Described control circuit comprises that the first bleeder circuit (2), peak sample circuit (3), the second bleeder circuit (4), the first multiplier (5), subtraction circuit (6), add circuit (7), regulating error circuit (8), the second multiplier (9), PWM IC chip (10), switching tube drive (11), and wherein the output terminals A of the first bleeder circuit (2) accesses respectively the input of peak sample circuit (3), the second input v of the first multiplier (5) yand the input of subtraction circuit (6), the 3rd input v of the output B of peak sample circuit (3) and the first multiplier (5) zconnect, the output C of the second bleeder circuit (4) accesses respectively the first input end v of the first multiplier (5) x, the second multiplier (9) the 3rd input v zthe output D of the first multiplier (5) is connected with an input of add circuit (7), the output E of subtraction circuit (6) is connected with another input of add circuit (7), the first input end v of the output F of add circuit (7) and the second multiplier (9) xconnect the output v of regulating error circuit (8) eAthe second input v with the second multiplier (9) ybe connected, the output P of the second multiplier (9) is connected with the input of PWM IC chip (10), the output of PWM IC chip (10) drives the input of (11) to be connected with switching tube, and switching tube drives output and the switching tube Q of (11) bgate pole connect.
2. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, described the first bleeder circuit (2) comprises the first operational amplifier A 1, the first resistance R 1, the second resistance R 2; The first resistance R 1an end and input voltage sampled point V gthe output cathode that is diode rectifier circuit RB connects, the first resistance R 1the other end and the second resistance R 2one end connects and common port accesses the first operational amplifier A 1positive input, the second resistance R 2the other end with reference potential, be connected zero point, the first operational amplifier A 1reverse input end with output terminals A, directly be connected, form the in-phase voltage follower.
3. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, described peak sample circuit (3) comprises the 3rd resistance R 3, the first diode D 1, the first capacitor C 1, the 4th resistance R 4, the second operational amplifier A 2; The 3rd resistance R wherein 3an end and the first operational amplifier A of the first bleeder circuit (2) 1output terminals A connect, the 3rd resistance R 3the other end and the first diode D 1anodal series connection is by the first diode D 1negative pole access the second operational amplifier A 2normal phase input end, the first capacitor C 1with the 4th resistance R 4an end and the second operational amplifier A after in parallel 2normal phase input end be connected, another termination reference point position zero point, the second operational amplifier A 2inverting input with output B, directly be connected.
4. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, described the second bleeder circuit (4) comprises the 5th resistance R 5with the 6th resistance R 6, the 5th resistance R wherein 5an end and the output voltage V of main power circuit (1) othe anodal connection, the 5th resistance R 5the other end and the 6th resistance R 6the output C that an end connects and its common port is the second bleeder circuit (4), the 6th resistance R 6other end access reference point position zero point.
5. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, described subtraction circuit (6) comprises the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, four-operational amplifier A 4; The 15 resistance R wherein 15one end and output voltage V othe anodal connection, the other end is connected to four-operational amplifier A 4positive input, the 13 resistance R 13one end is connected to four-operational amplifier A 4positive input, the 13 resistance R 13the other end with reference potential, be connected zero point, the 12 resistance R 12one end is connected with the output terminals A of the first bleeder circuit (2), the 12 resistance R 12the other end and four-operational amplifier A 4reverse input end connect, the 14 resistance R 14be connected to four-operational amplifier A 4reverse input end and output E between.
6. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, add circuit (7) comprises the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 3rd operational amplifier A 3; The tenth resistance R wherein 10one end is connected with the output D of the first multiplier (5), other end access the 3rd operational amplifier A 3positive input, the 11 resistance R 11one end is connected with subtraction circuit (7) output E, other end access the 3rd operational amplifier A 3positive input, the 9th resistance R 9one end and the 3rd operational amplifier A 3positive input connect, other end access reference point position zero point, the 7th resistance R 7one termination enters the 3rd operational amplifier A 3reverse input end, other end access reference point position zero point, the 8th resistance R 8access the 3rd operational amplifier A 3reverse input end and output E between.
7. the DCM Boost pfc converter of low output voltage ripple according to claim 1, is characterized in that, described regulating error circuit (8) comprises the 16 resistance R 16, the 17 resistance R 17, the 18 resistance R 18, the second capacitor C 2, the 5th operational amplifier A 5; The 16 resistance R wherein 16one end and output voltage V oanodal connection, the other end and the 5th operational amplifier A 5reverse input end connect, the 17 resistance R 17one end and the 5th operational amplifier A 5reverse input end connect, other end access reference point position zero point, the 18 resistance R 18with the second capacitor C 2access the 5th operational amplifier A after series connection 5reverse input end and output between, the 5th operational amplifier A 5positive input and input voltage reference point V ogconnect.
CN201310424284.2A 2013-09-17 2013-09-17 DCM Boost PFC converter for low-output voltage ripples Pending CN103490601A (en)

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CN104967323A (en) * 2015-06-12 2015-10-07 南京理工大学 Low-output-voltage-ripple discontinuous-mode flyback power factor correction converter
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CN110690815A (en) * 2018-07-04 2020-01-14 群光电能科技股份有限公司 Mixed mode boost power factor correction converter
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CN105939121A (en) * 2015-11-23 2016-09-14 中国矿业大学 Wind generator current-adjustment and phase-modulation control-based parallel DCM Boost PFC converter
CN106487215A (en) * 2016-11-11 2017-03-08 南京航空航天大学 CRM boost PFC changer changes the optimal control of ON time
CN106487215B (en) * 2016-11-11 2019-04-09 南京航空航天大学 The optimal control of CRM boost PFC converter variation turn-on time
CN109149963A (en) * 2017-06-28 2019-01-04 南京理工大学 The DCM of switch periods optimal utilization rate control is depressured pfc converter
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