CN103489915B - A kind of laterally high pressure Superjunction power semiconductor device - Google Patents
A kind of laterally high pressure Superjunction power semiconductor device Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Abstract
The present invention relates to power semiconductor technologies, relate to specifically a kind of horizontal high pressure Superjunction power semiconductor device of charge compensation. Horizontal high pressure Superjunction power semiconductor device of the present invention, in the structure of P type substrate layer surface coverage one deck N-type charge compensation layer, N-type charge compensation layer has multiple doping way, comprises Uniform Doped, linear doping and discrete doping etc. Linear doping can make substrate-assisted depletion effect obviously reduce. Beneficial effect of the present invention is, on the basis of linear doping, use injection choice function doping content adjustment to be obtained to a kind of doping way of optimization, it takes into full account the charge balance conditions of desirable substrate condition and equivalent substrate itself, can overcome better the impact of substrate-assisted depletion effect, make super junction LDMOS obtain optimum withstand voltage properties. The present invention is particularly useful for horizontal high pressure Superjunction power semiconductor device.
Description
Technical field
The present invention relates to power semiconductor technologies, relate to specifically a kind of super knot of horizontal high pressure power of charge compensationSemiconductor devices.
Background technology
Along with developing rapidly of semiconductor technology, power MOSFET device is little with its driving power, switching speed fast, nothing twoInferiorly puncture, the advantage such as negative temperature coefficient and good thermal stability is widely applied. But in the time of high-voltage applications, traditional meritRate MOSFET than conducting resistance Ron，sp(SpecificOn-resistance) with breakdown voltage BV (BreakdownVoltage) 2.5 powers increase, and this has hindered the development of device. The proposition of super knot SJ (SuperJunction) structure is brokenThe theoretical limit of conventional MOS FET, keep the advantageous while of MOS, have again lower conduction loss.
Lateral double diffusion metal oxide semiconductor LDMOS (LateralDouble-diffusedMOSFET) device isHigh voltage integrated circuit HVIC (HighVoltageIntegratedCircuit) and power integrated circuit PIC (PowerIntegratedCircuit) key components. Its main feature is to have added between channel region and drain region one section of phaseTo longer light dope drift region, this drift region doping type is consistent with drain terminal, can play the effect of sharing breakdown voltage.
Super junction LDMOS device is a kind of improved LDMOS, by adulterating with drain terminal between channel region in LDMOS and drain regionAlternately arrange with one group in the light dope drift region that type is consistent and concentration is tied compared with the super knot of GaoNXing Tiao district and P Xing Tiao district formationStructure replaces, and in the time that drain terminal is setovered, by mutual assisted depletion between N/P bar, realizes N/P bar charge balance under perfect condition,Thereby obtain uniform Electric Field Distribution on surface, drift region. Simultaneously because N-type district is highly doped, the therefore electrical conductivity in N district when conductingVery large, make Ron，spObtain good improvement.
But compare longitudinally super junction device, because horizontal super junction device is made on the substrate of certain resistivity, surface is superInterface is subject to the impact of longitudinal electric field, and the P substrate after exhausting can be introduced acceptor's negative electrical charge can not consume the P bar district in super knot completelyCause surface super knot electric charge unbalance, thereby breakdown voltage is sharply reduced, be i.e. so-called substrate-assisted depletion effect to the greatest extent.
Cause laterally surpassing the unbalance problem of junction device N/P bar electric charge in order to solve substrate-assisted depletion effect, the present invention carriesGo out a kind of horizontal high-voltage power semiconductor devices of charge compensation, between P type substrate layer and super knot layer, introduce N-type charge compensationLayer, is considered as effective substrate by layer of compensation and P type substrate and sets up model, in the time border, LDMOS substrate depletion region being done to one dimension and be similar toShow that charge compensation layer optimum doping mode is linear doping, consider physical condition, on the basis of linear doping, utilize and injectChoice function is adjusted doping content, obtains the doping way of charge compensation layer optimum. This kind of doping way can overcomeThe impact of substrate-assisted depletion effect, makes laterally to surpass the withstand voltage effect of junction device and is significantly improved.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, a kind of laterally high pressure Superjunction power semiconductor device is proposed.
The present invention solves the problems of the technologies described above adopted technical scheme: the super knot of a kind of laterally high pressure power semiconductor devicePart, its structure cell comprises P type substrate 1, NXing Tiao district 3, P Xing Tiao district 4, P type tagma 5, N-type heavy doping source region 6, the heavy doping of P typeTagma, district 7, gate oxide 8, N+ drain region 9, drain electrode contact electrode 10, polysilicon gate 11, source electrode contact electrode 12 and substrateContact electrode 13; Described NXing Tiao district 3 and P Xing Tiao district 4 are along the P type substrate 1 upper surface formation super-junction structure that is longitudinally staggered, instituteState P type tagma 5 and be arranged on one end of P type substrate 1 upper surface and be connected with super-junction structure, described N+ drain region 9 is arranged on superOn junction structure, away from the one end in P type tagma 5, described drain electrode contact electrode 10 is arranged on the upper surface of N+ drain region 9; Described NType heavy doping source region 6 and P type heavily doped region tagma 7 are arranged in P type tagma 5 also separate; Described source electrode contact electrode 12Be arranged on the upper surface in P type heavily doped region tagma 7, described gate oxide 8 is arranged on upper surface and the part N-type weight in P type tagma 5The upper surface of doping source region 6; Described polysilicon gate 11 is arranged on the upper surface of gate oxide 8; Described substrate contact electrode 13 is establishedPut the lower surface at P type substrate 1; It is characterized in that, also comprise N-type charge compensation layer 2, described N-type charge compensation layer 2 is arranged onBetween P type substrate 1, NXing Tiao district 3 and P type tagma 5, the lower surface of N-type charge compensation layer 2 is connected with the upper surface of P type substrate 1,Upper surface YuNXing Tiao district 3 is connected with the lower surface in P type tagma 5.
The technical scheme that the present invention is total, by having covered the uniform N-type charge compensation of a layer thickness on P type substrate 1Layer 2. When device forward conduction, layer of compensation electric charge forms conduction region from source to drain terminal together with super heavy doping NXing Tiao district of tying,Be device than conducting resistance Ron，spThe parallel connection of charge compensation layer resistance and heavily doped super junction resistance, compare traditional duringStructure, Ron，spBe reduced. Oppositely time, laterally withstand voltagely mainly born by super knot N/PTiao district, under the condition of optimizing, electric chargeLayer of compensation compensates the electric charge of N/P bar is unbalance, and substrate-assisted depletion effect is significantly suppressed, now due to N/P barBe similar to and exhaust completely, the similar distributed rectangular of transverse electric field, thus horizontal voltage endurance capability is enhanced. Meanwhile, charge compensation layerForm N/P with substratesubTie longitudinal pressure-resistance structure, body internal electric field is strengthened, the longitudinal withstand voltage of device is also improved.
Concrete, described N-type charge compensation layer 2 is for to mix by the one in Uniform Doped, linear doping and discrete dopingAssorted mode forms.
Beneficial effect of the present invention is, by the N-type charge compensation in P type substrate layer surface coverage one deck optimization dopingLayer, the layer of compensation structure of optimizing doping takes into full account the charge balance conditions of desirable substrate condition and equivalent substrate itself, canTo overcome substrate-assisted depletion effect to the unbalance adverse effect of device super-junction structure N/P bar electric charge, improve device withstand voltage, simultaneouslyReduce device and compare conducting resistance.
Brief description of the drawings
Fig. 1 is laterally high pressure Superjunction power semiconductor device structure chart of tradition;
Fig. 2 is horizontal high pressure Superjunction power semiconductor device structure chart of the present invention;
Fig. 3 is horizontal high pressure Superjunction power semiconductor device illustraton of model of the present invention;
Fig. 4 structure chart during with N buffering area that is horizontal high pressure Superjunction power semiconductor device of the present invention at drain terminal;
Fig. 5 is horizontal high pressure Superjunction power semiconductor device structure chart of the present invention, and its backing material is SOI substrate, buriesOxygen layer is made on silicon substrate, and charge compensation layer is located at the upper surface of oxygen buried layer;
Fig. 6 is when between the super knot of horizontal high pressure Superjunction power semiconductor device of the present invention N/P bar, working medium is isolatedStructure chart;
Fig. 7 is that this horizontal high pressure Superjunction power semiconductor device is applied to LIGBT (LateralInsulated-GateBipolarTransistor) structure chart time;
Fig. 8 is an example of horizontal high pressure Superjunction power semiconductor device of the present invention, and its charge compensation layer is excellent respectivelyElectric field and the contrast of the horizontal high pressure Superjunction power semiconductor device of conventional structure electric field on AA ' curve when change, linearity, Uniform DopedFigure;
Fig. 9 is that horizontal high pressure Superjunction power semiconductor device layer of compensation electric charge of the present invention is respectively in optimization, linear, evenThe breakdown voltage of the breakdown voltage under distribution occasion and N/P nonequilibrium density relation and the super knot of conventional laterally high pressure power device withN/P nonequilibrium density is related to comparison diagram;
Figure 10 is that horizontal high pressure Superjunction power semiconductor device Optimization Compensation layer charge of the present invention is realized process principle figure.
Detailed description of the invention
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
As shown in Figure 1, be traditional horizontal high pressure Superjunction power semiconductor device, its structure cell comprises P type substrate 1, NXing Tiao district 3, P Xing Tiao district 4, P type tagma 5, N-type heavy doping source region 6, P type heavily doped region tagma 7, gate oxide 8, N+Drain regionTerritory 9, drain electrode contact electrode 10, polysilicon gate 11, source electrode contact electrode 12 and substrate contact electrode 13; Described NXing Tiao district 3 and PXing Tiao district 4 is along the P type substrate 1 upper surface formation super-junction structure that is longitudinally staggered, and described P type tagma 5 is arranged on P type substrate 1The one end on surface is also connected described N with super-junction structure+Drain region 9 is arranged on one end away from P type tagma 5 on super-junction structure,Described drain electrode contact electrode 10 is arranged on N+The upper surface of drain region 9; Described N-type heavy doping source region 6 and P type heavily doped region bodyDistrict 7 is arranged in P type tagma 5 also separate; Described source electrode contact electrode 12 is arranged on the upper table in P type heavily doped region tagma 7Face, described gate oxide 8 is arranged on the upper surface in P type tagma 5 and the upper surface in part N-type heavy doping source region 6; Described polysiliconGrid 11 are arranged on the upper surface of gate oxide 8; Described substrate contact electrode 13 is arranged on the lower surface of P type substrate 1.
As shown in Figure 2, be horizontal high pressure Superjunction power semiconductor device of the present invention, at the super knot of traditional high pressure power halfOn conductor device, also comprise N-type charge compensation layer 2, described N-type charge compensation floor 2 is arranged on P type substrate 1, NXing Tiao district 3 and PBetween type tagma 5, the lower surface of N-type charge compensation floor 2 is connected with the upper surface of P type substrate 1, upper surface YuNXing Tiao district 3 and PThe lower surface in type tagma 5 connects.
Operation principle of the present invention is:
On substrate layer, covered the charge compensation layer of one deck N-type, when device forward conduction, due to layer of compensation electric charge fromSource forms conducting channel together with the heavy doping N-type bar of drain terminal and super knot, device than conducting resistance Ron，spThat electric charge is mendedRepay the parallel connection of layer resistance and heavily doped super junction resistance, compare traditional device architecture, Ron，spBe reduced. Oppositely time, deviceLaterally the withstand voltage main N/P bar by super knot is born, under the condition of optimizing, and the electric charge mistake of charge compensation layer to N/P bar on the one handWeighing apparatus compensates, and substrate-assisted depletion effect is significantly weakened, and now exhausts transverse electric field completely because N/P bar approachesSimilar distributed rectangular, thus horizontal voltage endurance capability is enhanced. On the other hand, charge compensation layer and substrate have formed N/PsubTie longitudinal pressure-resistance structure, device body internal electric field is strengthened, longitudinally voltage endurance capability is improved.
Wherein, N-type charge compensation layer 2 has multiple doping way, comprises Uniform Doped, linear doping and discrete doping etc.Linear doping can make substrate-assisted depletion effect obviously reduce. On the basis of linear doping, use and inject choice function to mixingAssorted concentration adjustment obtains a kind of doping way of optimization, and it takes into full account desirable substrate condition and equivalent substrate itselfCharge balance conditions, can overcome the impact of substrate-assisted depletion effect better, makes super junction LDMOS obtain optimum resistance to pressureEnergy. Said structure and doping way are also conducive to reduce the ratio conducting resistance of device. The present invention also comprises a kind of doping benefit of optimizingRepay the technique implementation of layer.
The optimum doping way of layer of compensation obtains by following process:
Layer of compensation and P type substrate are considered as to effective substrate and set up model, selecting arbitrary surperficial N bar mid point is initial point, x, y, zDirection difference directed in orthogonal is in NP bar direction, drain terminal direction, substrate direction, as shown in Figure 3. Surperficial SJ layer and charge compensation in figureLayer junction depth is ts、tc; The substrate depletion region degree of depth is t (y); Surface N/P bar length and width are respectively LdAnd W; The doping of N/P bar is denseDegree is Na(N/P doping content equates), layer of compensation and substrate doping are respectively NsubAnd N (y), VDRepresent drain terminal voltage.
By set up Solving Three-Dimensional poisson Equation in the super knot layer in surface, utilize the periodic boundary condition of super knot and laterallyThe interface electric flux continuity boundary condition of LDMOS carries out dimensionality reduction to Solving Three-Dimensional poisson Equation, and makes electricity consumption at device source leakage two endsThe differential equation of gesture boundary condition after to abbreviation solves, and obtains device surface Potential Distributing and is:
εsRepresent semi-conductive capacitivity, q represents the absolute value of an electrically charged amount in electron institute, and π is pi.
Can obtain device surface by formula (1) along N/P bar direction Potential Distributing is:
In formula (1), (2), T represents device substrate feature thickness. Its value is:
The substrate depletion layer degree of depth is carried out first approximation and used tesReplace t (y), obtain:
There is extreme point at an A, A ', B, B ' in the Section 1 that can find out expression formula from formula (2), device breakdown is named a person for a particular jobAppear at these points. Further, by the electric field expression formula of curve A A ' can abbreviation be:
In formula (5):
Formula (5) and being met by the derive electric field expression formula that obtains of formula (2): a) two formulas have identical electric field extreme point,B) two formula Section 1 integrated values equate.
Defining ideal substrate only surpasses as surface the supporting construction of tying layer, laterally SJ electric field and longitudinal super knot of surface when withstand voltageSimilar. Based on this definition, the idealized compensating electric field distribution and expression formula that (2) formula of utilization can obtain being produced by compensation charge:
E in formula (7)cRepresent silicon critical breakdown electric field. Desirable compensating electric field size is dull reduction from source to drain terminal, andAnd device source needs the value of compensating electric field higher than drain terminal, in the time that the complementary field of charge compensation layer generation more approaches this expression formula,Substrate-assisted depletion effect just more can be effectively suppressed.
Further, while meeting desirable substrate, having a) equivalent substrate electrostatic charge concentration is 0; B) equivalent substrate surface electric fieldFor constant. According to idealized substrate condition (b) and consider device withstand voltage maximum, obtain equivalence by solving two-dimentional Poisson's equationSubstrate surface field:
T in formula (8)EBe the characteristic thickness of equivalent substrate, its value is:
tsubBe the substrate depletion layer degree of depth, use first approximation to be expressed as:
In formula (10)Represent the average doping content of charge compensation layer. From formula (8), can find out that equivalent substrate is equalThe conditional request layer of compensation of even surface field is N-type linear doping.
For the impact of quantitative description layer of compensation electric field on device surface field, while supposing device withstand voltage, layer of compensation exhausts entirely,Write out two-dimentional Poisson's equation in charge compensation layer, longitudinal electromotive force in charge compensation layer is used to the second Taylor series, to dividing arbitrarilyCloth layer of compensation electric charge, application Green Function Method can solve and obtain equivalent substrate surface electromotive force and Electric Field Distribution, wherein linear dopingThe complementary field that charge compensation layer produces is:
N in formula (11)drRepresent drain terminal below charge compensation layer doping content, γ represents equivalent substrate surface electric field to changeThe scale factor of calculating device surface, its value is:
Can find out by comparing formula (7) and formula (11), distribute and do the approximate bar of one dimension on border, substrate depletion regionUnder part, linear compensation charge generation additional electric field and desirable compensating electric field have identic expression formula, therefore pass through deviceThe optimal design of size, that can realize horizontal super knot withstand voltagely reaches desirable effect.
In model solution process, for the needs of reduced equation, substrate depletion region is distributed and used one dimension approximate, thisThe optimization layer of compensation electric charge obtaining of deriving under part is linear distribution. In fact the depletion layer degree of depth is along with equivalent substrate surface electricityGesture changes and changes, and therefore simple linear doping charge compensation layer can not make equivalent substrate effective charge concentration level off to0, the derive optimization linear doping compensation charge that obtains of above-mentioned theory distributes and can not realize the optimization of device withstand voltage. DefinitionInjecting choice function is the aperturefunction of i district photolithography plate, that is:
T in formula (13)submBe the maximum depletion width of substrate, M is photolithography plate opening number, tiThat i district corresponding substrate is realBorder depletion depth, its value is:
Formula (14) is injected to choice function and act on linear doping layer of compensation, can realize surperficial N/P bar better satisfiedCharge balance conditions, show that optimum doping way is compensation charge layer class parabolic distribution thus.
As shown in Figure 3, be horizontal high pressure Superjunction power semiconductor device illustraton of model provided by the invention. Model is with surperficial NXing Tiao district (3) mid point is initial point, and x, y, z direction difference directed in orthogonal is in N/P bar direction, drain terminal direction, substrate direction. ts、tcPointThe junction depth of other presentation surface SJ layer and charge compensation layer; The substrate depletion region degree of depth is t (y), tavRepresent depletion region mean depth; TableFace N/P bar length and width are respectively LdAnd W, surperficial dotted line represents super knot N, P Tiao center. A, A ' represent N-type bar 3 outboard endsPoint, B, B ' they are the end points of P type bar 4 center dotted lines, are one and half cellulars between AA ' and BB '; In figure, mark respectively N-typeIn charge compensation layer, in ionized donor electric charge and P type substrate, ionize acceptor's electric charge, wherein dotted line represents depletion region border.
As shown in Figure 4, for horizontal high pressure Superjunction power semiconductor device provided by the invention at drain terminal with N-type buffering areaThe structure chart of 14 o'clock, on the basis of said structure, by N+Drain region 9 is arranged in N-type buffering area 14, N-type buffering area 14Be connected with super-junction structure and N-type charge compensation layer 2.
While as shown in Figure 5, using SOI material for horizontal high pressure Superjunction power semiconductor device substrate provided by the inventionStructure chart, oxygen buried layer 15 is positioned at silicon substrate upper surface, and charge compensation layer 2 is located on oxygen buried layer 15.
As shown in Figure 6, for the super knot of horizontal high pressure Superjunction power semiconductor device provided by the invention N/P bar working medium everyFrom time structure chart, wherein SiO2Medium 16 is between super knot N bar and P bar.
As shown in Figure 7, the structure while being applied to LIGBT for the horizontal high pressure Superjunction power semiconductor device of confession of the present inventionFigure. Comprise low-doped P type substrate 1, be positioned at the N-type charge compensation layer 2 of P type substrate top surface, on N-type charge compensation layerBe the groundwork region of device, comprise staggered transversely arranged heavy doping N-type bar 3 and P type bar 4, they form device jointlySuper knot divide. Upper surface and N/P bar right side at charge compensation layer 2 are P type tagmas 5, are positioned at source electrode contact electrode 12 and P shapeThe P that is between tagma 5+Heavy doping body contact zone 7, N+Source region 6 is positioned at 7 left sides, body contact zone, in tagma 5 and device surface itBetween be respectively gate oxide 8 from the bottom to top and cover the polysilicon gate 11 on gate oxide 8. Be positioned at super-junction structure right sideThe right-hand member of device is distinguished ShiNXing anode buffer district 17, P type heavy doping anode region 18 and anode contact zone 10 from the bottom to top, is positioned atDevice bottommost be substrate contact electrode 13.
As shown in Figure 8, for horizontal high pressure Superjunction power semiconductor device provided by the invention is at ts＝tc＝1μm、Ld＝15μm、W＝1μm、x＝0μm、z＝0μm、Nsub=1e14cm-3, N/P bar doping content NN＝NP＝4e16cm-3Time, charge compensationIn layer, optimize respectively, electric field and the horizontal high pressure Superjunction power semiconductor device of conventional structure on AA ' curve when linear, Uniform DopedElectric field comparison diagram. In figure, solid line represents the analytic solutions of model, and point represents the numerical solution being obtained by ISE emulation, can find outExcept close source-and-drain junction position, two groups of curves are better, and it is due to the curvature effect of having ignored PN junction in model that error producesImpact and introduce the one dimension of substrate depletion region thickness is approximate.
As shown in Figure 9, be horizontal high pressure Superjunction power semiconductor device charge compensation layer charge difference provided by the inventionSurpass and tie power with N/P nonequilibrium density relation and conventional laterally high pressure in optimization, breakdown voltage linear, that be uniformly distributed under conditionThe breakdown voltage of device and N/P nonequilibrium density are related to comparison diagram. As can be seen from the figure three kinds of compensating forms all can be realized N/PCharge balance between bar, optimizes the SJ-LDMOS structure of CONCENTRATION DISTRIBUTION charge compensation layer equivalence substrate electroneutrality condition when withstand voltageCan better be met, therefore there is the highest withstand voltage 301V. Linear, be uniformly distributed that compensation charge SJ-LDMOS is withstand voltage to be respectively278V and 225V, conventional structure device in the time that N bar concentration increases by 25% is maximum withstand voltage for 216V, lower than three kinds of charge compensation conditionsUnder withstand voltage.
As shown in figure 10, realize work for the invention provides horizontal high pressure Superjunction power semiconductor device Optimization Compensation layer chargeSkill schematic diagram. The mode that adopts a phosphorus injection to increase temperature annealing forms Optimization Compensation layer charge and distributes, and device diverse location is mixedAssorted concentration is by implantation dosage DeAnd the injection choice function η of correspondence positioniDetermine ηiBe defined as the opening letter of i district photolithography plateNumber. L in figureiRepresent i district photolithography plate A/F, L0Represent N/P bar length LdDivided equally the width of every portion after M part.
Horizontal high pressure Superjunction power semiconductor device provided by the invention embeds one deck doping dense between super knot and substrateThe N-type charge compensation layer that degree optimization distributes, the layer of compensation structure of optimizing doping takes into full account desirable substrate condition and equivalence liningThe charge balance conditions of copy for the record or for reproduction body, can overcome substrate-assisted depletion effect unbalance to device super-junction structure N/P bar electric chargeProfit impact. In the time of device forward conduction, N-type charge compensation layer forms conduction together with heavily doped N-type bar in super knot on the one handRaceway groove, is reduced the ratio conducting resistance of device, and on the other hand, charge compensation layer is super to what cause due to the effect of P type substrateLotus is unbalance compensates for knot conduction, has reduced substrate-assisted depletion effect, and the horizontal voltage endurance capability of device is significantly improved,Due to the existence of charge compensation layer, the body internal electric field of device is enhanced, and is also conducive to improve the longitudinal withstand voltage of device simultaneouslyImprove.
Claims (1)
1. a horizontal high pressure Superjunction power semiconductor device, its structure cell comprises P type substrate (1), NXing Tiao district (3), P typeBar district (4), P type tagma (5), N-type heavy doping source region (6), P type heavily doped region tagma (7), gate oxide (8), N+Drain region(9), drain electrode contact electrode (10), polysilicon gate (11), source electrode contact electrode (12) and substrate contact electrode (13); Described N-typeBar district (3) and P Xing Tiao district (4) are along P type substrate (1) the upper surface formation super-junction structure that is longitudinally staggered, described P type tagma (5)Be arranged on one end of P type substrate (1) upper surface and be connected described N with super-junction structure+Drain region (9) is arranged on super-junction structureUpper one end away from P type tagma (5), described drain electrode contact electrode (10) is arranged on N+The upper surface of drain region (9); Described NType heavy doping source region (6) and P type heavily doped region tagma (7) are arranged in P type tagma (5) also separate; Described source electrode contactElectrode (12) is arranged on the upper surface in P type heavily doped region tagma (7), and described gate oxide (8) is arranged on the upper of P type tagma (5)The upper surface in surface and part N-type heavy doping source region (6); Described polysilicon gate (11) is arranged on the upper surface of gate oxide (8);Described substrate contact electrode (13) is arranged on the lower surface of P type substrate (1); It is characterized in that, also comprise N-type charge compensation layer(2), described N-type charge compensation floor (2) is arranged between P type substrate (1), NXing Tiao district (3) and P type tagma (5), and N-type electric charge is mendedThe lower surface of repaying floor (2) is connected with the upper surface of P type substrate (1), the following table in upper surface YuNXing Tiao district (3) and P type tagma (5)Face connects; Described N-type charge compensation layer (2) is for to form by Uniform Doped mode.
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