CN103488595A - Data transmission method capable of ensuring small capacity cache serial communication safety - Google Patents

Abstract

The present invention relates to a data transmission method that guarantees the safety of small-capacity cached serial port communication. Firstly, the relationship between the capacity N of the cached FIFO, the single-byte data transmission time T and the maximum interrupted time T _interrupt is given. In different Judging the working state of the cache FIFO at the moment of data transmission, adopting different transmission strategies according to the different states of the cache FIFO, thereby ensuring the reliability and continuity of serial communication and preventing interruptions from affecting data transmission. The data transmission method of the present invention is based on the cache FIFO capacity, single-byte data transmission time, maximum interrupt processing time and other inherent characteristic designs are applicable to large-capacity FIFO and small-capacity FIFO at the same time, especially suitable for small-capacity FIFOs with a capacity of ≤10 bytes; and the realization process of the method of the present invention It is simple, easy to implement, and has strong practicability.

Description

A data transmission method to ensure the security of small-capacity buffer serial port communication

technical field

The invention relates to a data transmission method for ensuring the safety of small-capacity buffered serial port communication, belonging to the field of serial port communication.

Background technique

Serial port communication is a communication method commonly used in embedded systems. Ensuring the real-time and correctness of communication is the focus of communication logic design. In the embedded system, interruption is an important factor that threatens the normal communication of the serial port. In order to prevent the impact of external interruption on the communication of the serial port, the industry starts with hardware resources and adopts a large-capacity buffer (FIFO) to ensure the continuity of data transmission. In the case of a large-capacity cache, the software can write a sufficient amount of data to the cache each time, by enabling the transmission state machine to read the data from the transmit FIFO and transmit it to the shift register, and the shift register passes through the FSM Complete data output. In this way, even if a sending process of the software is interrupted by an interruption, since there is enough data in the sending FIFO, the interruption process will not affect the normal transmission work of the transmission state machine, thereby ensuring the real-time and continuity of data transmission. However, the use of large-capacity cache requires additional peripheral circuits and chips, which undoubtedly increases the complexity and cost of the system. In addition, if the traditional large buffer communication method is used to fill up the FIFO at one time, because there are still unsent data, there may still be unavoidable interruptions between the two writing processes. In addition, especially for small-capacity caches, the probability of interruption during data transmission is more frequent. Once interrupted, the continuity of data transmission cannot be guaranteed.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned defects of the prior art, and provide a data transmission method that ensures the security of small-capacity buffered serial port communication. The method can effectively ensure the continuity of data transmission and prevent interruptions from affecting data transmission. The method is applicable to large-capacity buffer FIFO and small-capacity buffer FIFO at the same time, and is especially suitable for small-capacity buffer FIFO with a capacity of ≤10 bytes.

Above-mentioned purpose of the present invention is mainly achieved through the following technical solutions:

其中ε为温度损耗系数，具体实现方法如下：A data transmission method that guarantees the security of small-capacity buffer serial port communication, the serial port is the interface between the upper computer and the lower computer, and the serial port includes a buffer FIFO, a transmission state machine and a shift register, and is characterized in that: the capacity of the buffer FIFO is N, the data transmission time of a single byte is T, and the maximum interrupt time is T _interrupt , satisfying:

Where ε is the temperature loss coefficient, and the specific implementation method is as follows:

(1) The upper computer initializes the serial port and completes the configuration of the working state of the serial port;

(2) The upper computer sends a control command to the transmission state machine, and the transmission state machine stops data transmission according to the control command;

(3) The upper computer writes data into the cache FIFO, and the number of written data is less than or equal to the capacity N of the cache FIFO, and at the same time, the upper computer sends a control command to the transmission state machine;

(4) The transmission state machine reads data from the cache FIFO according to the control instruction and transmits it to the shift register, and the shift register outputs the data to the lower computer;

(5) The host computer judges the state of the cache FIFO, if the cache FIFO capacity is full, then wait, if the cache FIFO capacity is not full, then enter step (6);

(6) If the used capacity in the cache FIFO is ≥ 2 bytes, then the host computer writes data to the unused capacity in the cache FIFO, and enters step (7); if the used capacity in the cache FIFO is < 2 bytes, then the host computer The machine stops writing data into the cache FIFO, and after the data in the cache FIFO is emptied by the transmission state machine, enter step (7);

(7). The host computer judges whether the data has been sent, if it has been sent, end the data transmission; if not, go to step (2).

In the above-mentioned data transmission method for ensuring the security of small-capacity buffer serial port communication, in step (1), the host computer initializes the serial port, and completes the configuration of the serial port working state, including baud rate setting, parity setting, stop bit number setting, Set and clear the cache FIFO in interrupt mode.

In the above-mentioned data transmission method for ensuring the security of small-capacity buffered serial port communication, in step (6), the time for the transmission state machine to empty the data in the cache FIFO is: the time for the transmission state machine to read data from the cache FIFO + the time for the transmission state machine Data transfer time + data output time of shift register.

In the above data transmission method for ensuring the security of small-capacity buffered serial port communication, the temperature loss coefficient ε is within the nominal operating temperature range of the serial port, and takes a value of 1.

In the above-mentioned data transmission method for ensuring the security of small-capacity buffered serial port communication, the maximum interrupt time T _interrupt may be the accumulation of multiple consecutive interrupt times.

In the above data transmission method for ensuring the security of small-capacity buffered serial port communication, the capacity of the buffered FIFO is N≤10 bytes.

Compared with the prior art, the present invention has the following beneficial effects:

(1), the present invention designs a kind of brand-new serial port data transmission method, firstly provides the capacity N of cache FIFO, the relation between the data transmission time T of single byte and the maximum interruption time T _interruption , in different data Judging the working status of the buffer FIFO at the time of transmission, and adopting different transmission strategies according to different states of the buffer FIFO, thus ensuring the reliability and continuity of serial communication and preventing interruptions from affecting data transmission;

(2) The data transmission method of the present invention is designed according to inherent characteristics such as cache FIFO capacity, single-byte data transmission time, and maximum interrupt processing time, and is applicable to both large-capacity FIFO and small-capacity FIFO, especially for capacity ≤ 10 bytes small-capacity FIFO;

(3) The present invention can realize data transmission through a small-capacity buffer FIFO, which reduces the cost of use, and the realization process is simple, easy to implement, and has strong practicability; the data transmission method of the present invention is especially suitable for aviation, aerospace, ships, etc. Fields with special requirements for electronic components.

Description of drawings

Fig. 1 is a connection diagram of hardware equipment of the present invention;

FIG. 2 is a flow chart of the serial communication data transmission method of the present invention.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

The core technical problem solved by the invention is to ensure the real-time and continuity of serial port communication under the condition of insufficient FIFO resources. During the operation of embedded software, interrupts are generated everywhere, and their interrupt frequency, interrupt source, and interrupt processing time are different. No matter what kind of interrupt, as long as its generation timing or processing conflicts with the serial port communication process, it will affect the serial port. Normal communication. Taking a certain control system as an example, the control computer communicates with a load through the RS422 serial port. According to the requirements of the load, the control computer sends the data byte interval <50μs, that is, the load cannot receive the next byte data within 50μs after receiving the upper byte data. Then task communication fails and the communication ends automatically. The interrupt processing time is about 200μs. If the interrupt is sent at the interval of two bytes, it will inevitably cause communication overtime and cause communication failure.

In order to ensure the continuity of communication, the key is to ensure that the time interval of the byte during the whole process from enabling the serial port to sending the data must be within the required time. Due to the limitation of FIFO resources (FIFO depth < data length), if the traditional large buffer communication method is used to fill the FIFO at one time, because there are still unsent data, interruptions cannot be avoided between the two writing processes For this reason, the present invention designs a technical solution to ensure the security of small-capacity buffered serial port communication based on inherent characteristics such as FIFO depth, byte-to-byte transmission time, and interrupt processing time. The data transmission method of the present invention is applicable to large-capacity buffer FIFO and small-capacity buffer FIFO at the same time, especially suitable for small-capacity buffer FIFO with capacity ≤ 10 bytes.

As shown in Fig. 1, it is the connection diagram of the hardware equipment of the present invention, the hardware equipment that the present invention realizes data transmission comprises upper computer, serial port and lower computer, and wherein serial port is the interface of upper computer and lower computer, and serial port includes cache FIFO, transmission state machine and shift registers. Let the capacity of the cache FIFO be N, the data transmission time of a single byte be T, and the maximum interrupt time be T _interrupt , which satisfies the following formula:

Among them: ε is the temperature loss coefficient, and the temperature loss coefficient ε is within the nominal operating temperature range of the serial port, and the value is usually 1.

The data transmission method that the present invention guarantees the security of small-capacity cache serial port communication comprises the following steps, as shown in Figure 2 is the flow chart of the serial port communication data transmission method of the present invention:

(1) First, the host computer initializes the serial port and completes the serial port working status configuration, including baud rate setting, parity setting, stop bit number setting, interrupt mode setting (clock) and clearing the cache FIFO.

(2) Then the host computer sends a control command to the transmission state machine, and the transmission state machine stops data transmission according to the control command;

(3) Afterwards, the upper computer writes the data into the buffer FIFO, and the number of written data is less than or equal to the capacity N of the buffer FIFO, and at the same time, the upper computer sends a control command to the transmission state machine;

(4) The transmission state machine reads the data from the cache FIFO according to the control instruction in step (3) and transmits it to the shift register, and the shift register outputs the data to the lower computer;

(5) The host computer judges the status of the cache FIFO, if the cache FIFO capacity is full, then wait, if the cache FIFO capacity is not full, then enter step (6);

(6) If the used capacity in the cache FIFO is ≥ 2 bytes, the host computer writes data to the unused capacity in the cache FIFO, and enters step (7); if the used capacity in the cache FIFO is < 2 bytes, the host computer Stop writing data into the cache FIFO, and enter step (7) after the transmission state machine empties the data in the cache FIFO; the data emptying time is: the time when the transmission state machine reads data from the cache FIFO + transmission status Machine data transfer time + shift register data output time.

(7) The host computer judges whether the data has been sent, if it has been sent, end the data transmission; if not, go to step (2).

The above-mentioned maximum interruption time T _interruption may be the accumulation of a plurality of continuous interruption times.

The selection of the waiting time in the above steps should fully consider the amount of data in the buffer FIFO at the beginning of waiting and the transmission time after it is taken out of the buffer FIFO, and consider a certain margin to avoid software "dead waiting" once an exception occurs.

Example 1

Taking the cache FIFO capacity as 4 bytes as an example, the data transmission method includes the following steps:

(1) The host computer initializes the serial port and completes the configuration of the serial port working status, including baud rate setting, parity setting, stop bit number setting, interrupt mode setting (clock) and clearing FIFO.

(2) The upper computer sends control instructions to the transmission state machine, and the transmission state machine stops data transmission according to the control instructions.

(3) The host computer writes data into the cache FIFO, and the number of written data is less than or equal to the capacity N of the cache FIFO, and at the same time, the host computer sends a control command to the transmission state machine.

(4) The transmission state machine reads the data from the buffer FIFO according to the control instruction and transmits it to the shift register, and the shift register outputs the data to the lower computer.

(5) The upper computer judges the status of the buffer FIFO, and the capacity of the buffer FIFO is 3 bytes at this time, which is not full, and then enters step (6).

(6) Judging that the used capacity in the buffer FIFO is ≥ 2 bytes, the host computer writes 1 byte of data into the buffer FIFO, and the data in the buffer FIFO is full, and then enter step (7).

(7) The upper computer judges that the data has not been sent, and enters step (2). If it has been sent, end sending.

Example 2

Still taking the buffer FIFO capacity as 4 bytes as an example, the data transmission method includes the following steps:

(1) The host computer initializes the serial port and completes the configuration of the serial port working status, including baud rate setting, parity setting, stop bit number setting, interrupt mode setting (clock) and clearing FIFO.

(2) The upper computer sends control instructions to the transmission state machine, and the transmission state machine stops data transmission according to the control instructions.

(3) The host computer writes data into the cache FIFO, and the number of written data is less than or equal to the capacity N of the cache FIFO, and at the same time, the host computer sends a control command to the transmission state machine.

(4) The transmission state machine reads the data from the buffer FIFO according to the control instruction and transmits it to the shift register, and the shift register outputs the data to the lower computer.

(5) The upper computer judges the status of the buffer FIFO, and the capacity of the buffer FIFO is 1 byte at this time, which is not full, and then enters step (6).

(6) Judging that the used capacity in the buffer FIFO is less than 2 bytes, the host computer stops writing data into the buffer FIFO, and after the data in the buffer FIFO is emptied by the transmission state machine, enter step (7); where the data is emptied The time is: the time when the transmission state machine reads data from the cache FIFO + the data transmission time of the transmission state machine + the data output time of the shift register.

(7) The host computer judges whether the data has been sent, if it has been sent, end the data transmission; if not, go to step (2).

The above description is only the best specific implementation mode of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of changes or modifications within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention.

The content that is not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims (6)

1. a data transmission method that guarantees the security of low capacity buffer memory serial communication, the interface that described serial ports is host computer and slave computer, serial ports comprises buffer memory FIFO, transmit state machine and shift register, it is characterized in that: the capacity of described buffer memory FIFO is N, the data transmission period of byte is T, and be T maximum break period _interrupt, meet:

wherein ε is the temperature losses coefficient, and concrete methods of realizing is as follows:

(1), host computer carries out initialization to serial ports, completes the configuration of serial ports duty;

(2), host computer is to the transmit state machine sending controling instruction, transmit state machine stops data transmission according to described steering order;

(3), host computer writes buffer memory FIFO by data, the data amount check write is less than or equal to the capacity N of buffer memory FIFO, host computer sends steering order to transmitting defeated state machine simultaneously;

(4), transmit state machine is according to described steering order reading out data be sent to shift register from buffer memory FIFO, shift register is exported to slave computer by described data;

(5), the state of host computer judgement buffer memory FIFO, if buffer memory FIFO capacity is full, wait for, if buffer memory FIFO capacity less than, enter step (6);

(6) if used capacity >=2 bytes in buffer memory FIFO, host computer is not used the capacity data writing in buffer memory FIFO, enters step (7); If used capacity<2 bytes in buffer memory FIFO, host computer stops to data writing in buffer memory FIFO, after transmitting state machine the data in buffer memory FIFO are got to sky, enters step (7);

(7), host computer judges whether data distribute, if distribute, end data sends; If do not distribute, enter step (2).

2. a kind of data transmission method that guarantees the security of low capacity buffer memory serial communication according to claim 1, it is characterized in that: in described step (1), host computer carries out initialization to serial ports, completes the configuration of serial ports duty and comprises Configuration of baud rate, parity checking setting, the setting of position of rest number, interrupt mode setting and remove buffer memory FIFO.

3. a kind of data transmission method that guarantees the security of low capacity buffer memory serial communication according to claim 1 is characterized in that: in described step (6), transmit state machine is got the sky time by the data in buffer memory FIFO and is: the data output time of transmit state machine reading out data time+transmit state machine data transfer time+shift register from buffer memory FIFO.

4. a kind of data transmission method that guarantees the security of low capacity buffer memory serial communication according to claim 1, it is characterized in that: described temperature losses coefficient ε is in serial ports nominal operation temperature range, and value is 1.

5. a kind of data transmission method that guarantees the security of low capacity buffer memory serial communication according to claim 1, is characterized in that: described maximum T break period _interruptcan adding up for continuous a plurality of break periods.

6. a kind of data transmission method that guarantees the security of low capacity buffer memory serial communication according to claim 1, is characterized in that: the capacity N of described buffer memory FIFO≤10 bytes.

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