CN103456616A - 制备栅氧层的工艺 - Google Patents
制备栅氧层的工艺 Download PDFInfo
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Abstract
本发明涉及半导体制造领域,尤其涉及一种制备栅氧层的工艺,通过采用氘气的湿氧化工艺制备栅氧层,并利用高温退火工艺对制备的栅氧层进行氮化处理,于栅氧层的表面形成稳定的Si-D键,以减少硅悬键,在降低栅氧界面缺陷的同时,有效降低了栅氧化层的界面缺陷密度和电荷密度,进而有效避免NBTI效应的产生,提高了产品的可靠性能和良率。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种制备栅氧层的工艺。
背景技术
负偏压温度不稳定性效应(Negative Bias Temperature Instability,简称NBTI)指在高温下对PMOSFET施加负栅压而引起的一系列电学参数的退化(一般应力条件为125℃恒温下栅氧电场,源、漏极和衬底接地)。
NBTI效应的产生过程主要涉及正电荷的产生和钝化,即界面陷阱电荷和氧化层固定正电荷的产生以及扩散物质的扩散过程,而氢气和水汽是引起NBTI的两种主要物质。NBTI效应对器件和电路能产生较大的影响,如:使得器件出现栅电流增大、阈值电压负向漂移、亚阈值斜率减小、跨导和漏电流变小等,在模拟电路中引起晶体管间失配,而在数字电路中则会导致时序漂移、噪声容限缩小,甚至产品失效等严重后果。
目前,随着半导体器件工艺的发展,对器件的性能要求越来越高,进而促使器件尺寸不断缩小。但是,随着器件尺寸的不断缩小,工作电压却不能成比例地降低,使得栅氧化层电场相对升高,易形成NBTI效应,尤其是采用传统湿氧氧化工艺制备的栅氧化层(Si+H2O→SiO2),由于在该栅氧化层的界面存在大量的Si-H键,而热激发的空穴与Si-H键作用易生成H原子,从而在界面留下悬挂键,而由于H原子的不稳定性,即两个H原子相遇就会结合,并以氢气分子的形式释放后,就会远离界面而向栅界面扩散,引起阈值电压的负向漂移,形成NBTI效应导致器件性能衰退,甚至造成器件的损坏。
中国专利(公开号:CN1264164A)公开了一种形成金属氧化物半导体的栅氧化物的方法,通过采用半导体的干、湿、干氧化的工艺程序,以降低半导体一氧化物界面处的界面状态密度。该技术文献并没有公开有关如何消除NBTI效应相关的技术特征。
中国专利(公开号:CN1722408A)公开了一种栅氧化膜的制造方法,通过在衬底上形成绝缘膜之后,形成牺牲或栅氧化膜作为氧化膜,并利用抗蚀剂层作为掩膜,经由氧化膜,通过氩(或氟)离子的一个或多个注入工艺形成离子注入层。当使用氧化膜作为牺牲氧化膜时,在除去抗蚀剂膜及氧化膜之后,在元件口中形成栅氧化膜。当使用氧化膜作为栅氧化膜时,通过刻蚀一次减薄氧化膜,并且在除去抗蚀剂层之后使其加厚。由于形成离子注入层,形成较厚的栅氧化膜。该技术文献也没有公开任何有关如何消除NBTI效应的技术特征。
发明内容
针对上述存在的问题,本发明公开了一种制备栅氧层的工艺,采用炉管方式生长所述栅氧层,其中,包括:
依次采用干氧化工艺和湿氧化工艺于一半导体衬底中生长一层栅氧层;
在高温条件下,采用氮气对所述栅氧层进行退火工艺;
其中,采用氧气进行所述干氧化工艺,采用氘气进行所述湿氧化工艺。
上述的制备栅氧层的工艺,其中,还包括:
于所述湿氧化工艺后,继续对所述半导体衬底进行所述干氧化工艺,以形成所述栅氧层。
上述的制备栅氧层的工艺,其中,所述干氧化工艺的温度条件为700℃-900℃,且通入氧气的流量大于或等于1slm。
上述的制备栅氧层的工艺,其中,所述湿氧化工艺的温度条件为700℃-900℃,工艺时间为25min-35min。
上述的制备栅氧层的工艺,其中,进行所述湿氧化工艺时,氘气与氧气的气体流量比例值为1:2-2:1。
上述的制备栅氧层的工艺,其中,所述退火工艺步骤所定义的高温条件为温度大于或等于900℃。
上述的制备栅氧层的工艺,其中,采用流量大于或等5slm的氮气对所述栅氧层进行退火工艺。
上述的制备栅氧层的工艺,其中,所述退火工艺的时间为10min-15min。
上述的制备栅氧层的工艺,其中,还包括:
在所述半导体衬底进行装载工艺后,采用7℃/min-13℃/min的温度上升速度,将反应腔内的温度上升至所述干氧化工艺所要求的温度值,同时控制氧气的气体流量大于等于0.3slm。
上述的制备栅氧层的工艺,其中,还包括:
在进行所述退火工艺前,采用7℃/min-13℃/min的温度上升速度,将反应腔内的温度上升至所述退火工艺所要求的温度值;
在所述半导体衬底进行卸载工艺前,采用1℃/min-5℃/min的温度下降速度,将反应腔内的温度降低至卸载工艺所要求的温度值。
综上所述,本发明一种制备栅氧层的工艺,通过采用氘气的湿氧化工艺制备栅氧层,并利用高温退火工艺对制备的栅氧层进行氮化处理,于栅氧层的表面形成稳定的Si-D键,以减少硅悬键,在降低栅氧界面缺陷的同时,有效降低了栅氧化层的界面缺陷密度和电荷密度,进而有效避免NBTI效应的产生,提高了产品的可靠性能和良率。
附图说明
图1-5为实施例中制备栅氧层的工艺的结构流程示意图。
具体实施方式
下面结合附图对本发明的具体实施方式作进一步的说明:
图1-5为实施例中制备栅氧层的工艺的结构流程示意图;如图1-5所示,一种通过炉管方式制备栅氧层的工艺,首先,如图1所示,在温度为600℃的条件下,对半导体衬底1如硅衬底等进行装载工艺(LOAD),经过稳定工艺(STAB)后,采用7℃/min-13℃/min(如7℃/min、10℃/min或13℃/min等)的温度上升速度,将反应腔室内的温度上升(RAMP UP)至700℃-900℃(如700℃、800℃或900℃等),并保持一段时间(TEAM STAB),以满足后续干氧化工艺的对于温度的要求,同时于反应腔室内通入适量的氧气,且通入的氧气的气体流量要大于等于0.3slm(如0.3slm、0.5slm或0.8slm等)。
其次,对半导体衬底1进行干氧化工艺(DRY OXIDE),以于半导体衬底1的上表面部分中生长第一栅氧化层21,且该第一栅氧化层21覆盖第一剩余半导体衬底11的上表面,以形成如图2所示的结构;其中,在700℃-900℃(如700℃、850℃或900℃等)温度条件下进行15min-25min(如15min、20min或25min等)的干氧化工艺,且同时于反应腔室内通入气体流量大于或等于1slm(如1slm、3slm或5slm等)的氧气。
之后,继续对第一剩余半导体衬底11进行湿氧化工艺(WET+DCE),以于第一剩余半导体衬底11的上表面部分中生长第二栅氧化层22,且该第二栅氧化层22覆盖第二剩余半导体衬底12的上表面,第一栅氧化层21覆盖第二栅氧化层22的上表面,以形成如图3所示的结构,使得在制备的栅氧化层中形成稳定的Si-D键(Si+D2O→SiO2),进而减少硅悬键,达到降低栅氧界面缺陷的目的;其中,在700℃-900℃(如700℃、800℃或900℃等)温度条件下进行25min-35min(如25min、30min或55min等)的湿氧化工艺,且同时于反应腔室内通入氘气,且反应腔室内氘气(D2)与氧气(O2)的气体流量比例值为1:2-2:1(如1:2、1:1或2:1等)。
然后,对第二剩余半导体衬底12进行干氧化工艺(DAY OXIDE),以于第二剩余半导体衬底12的上表面部分中生长第三栅氧化层23,且该第三栅氧化层23覆盖第三剩余半导体衬底13的上表面,第二栅氧化层22覆盖第三栅氧化层23的上表面,以形成如图4所示的结构,且如图4-5所示,上述的第一栅氧化层21、第二栅氧化层22和第三栅氧化层23共同构成栅氧层2;其中,在700℃-900℃(如700℃、800℃或900℃等)温度条件下进行3min-7min(如3min、5min或7min等)的干氧化工艺,且同时于反应腔室内通入气体流量大于或等于1slm(如1slm、5slm或7slm等)的氧气。
继续采用7℃/min-13℃/min(如7℃/min、11℃/min或13℃/min等)的温度上升速度,将反应腔室内的温度上升(RAMP UP)至大于或等于900℃(如900℃、1000℃或1100℃等),以满足后续退火工艺的对于温度的要求。
最后,在温度大于或等于900℃(如900℃、1000℃或1100℃等)的条件下,采用气体流量大于或等5slm(如5slm、7slm或9slm等)的氮气(N2)对栅氧层2进行10min-25min(如10min、15min或25min等)的退火工艺(ANNEAL),以对栅氧层2进行氮化处理,以降低栅氧层2的界面缺陷密度和电荷密度;继续采用1℃/min-5℃/min(如1℃/min、3℃/min或5℃/min等)的温度下降速度,将反应腔室内的温度上升(RAMP DOWN)至600℃左右,以完成后续的卸载工艺(UNLOAD)。
综上所述,由于采用了上述技术方案,本发明实施例提出一种制备栅氧层的工艺,通过采用氘气的湿氧化工艺制备栅氧层,并利用高温退火工艺对制备的栅氧层进行氮化处理,于栅氧层的表面形成稳定的Si-D键,以减少硅悬键,在降低栅氧界面缺陷的同时,有效降低了栅氧化层的界面缺陷密度和电荷密度,进而有效避免NBTI效应的产生,提高了产品的可靠性能和良率。
通过说明和附图,给出了具体实施方式的特定结构的典型实施例,基于本发明精神,还可作其他的转换。尽管上述发明提出了现有的较佳实施例,然而,这些内容并不作为局限。
对于本领域的技术人员而言,阅读上述说明后,各种变化和修正无疑将显而易见。因此,所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容,都应认为仍属本发明的意图和范围内。
Claims (10)
1.一种制备栅氧层的工艺,采用炉管方式生长所述栅氧层,其特征在于,包括:
依次采用干氧化工艺和湿氧化工艺于一半导体衬底中生长一层栅氧层;
在高温条件下,采用氮气对所述栅氧层进行退火工艺;
其中,采用氧气进行所述干氧化工艺,采用氘气进行所述湿氧化工艺。
2.根据权利要求1所述的制备栅氧层的工艺,其特征在于,还包括:
于所述湿氧化工艺后,继续对所述半导体衬底进行所述干氧化工艺,以形成所述栅氧层。
3.根据权利要求1或2所述的制备栅氧层的工艺,其特征在于,所述干氧化工艺的温度条件为700℃-900℃,且通入氧气的流量大于或等于1slm。
4.根据权利要求1所述的制备栅氧层的工艺,其特征在于,所述湿氧化工艺的温度条件为700℃-900℃,工艺时间为25min-35min。
5.根据权利要求1或4所述的制备栅氧层的工艺,其特征在于,进行所述湿氧化工艺时,氘气与氧气的气体流量比例值为1:2-2:1。
6.根据权利要求1所述的制备栅氧层的工艺,其特征在于,所述退火工艺步骤所定义的高温条件为温度大于或等于900℃。
7.根据权利要求1所述的制备栅氧层的工艺,其特征在于,采用流量大于或等5slm的氮气对所述栅氧层进行退火工艺。
8.根据权利要求1所述的制备栅氧层的工艺,其特征在于,所述退火工艺的时间为10min-15min。
9.根据权利要求1所述的制备栅氧层的工艺,其特征在于,还包括:
在所述半导体衬底进行装载工艺后,采用7℃/min-13℃/min的温度上升速度,将反应腔内的温度上升至所述干氧化工艺所要求的温度值,同时控制氧气的气体流量大于等于0.3slm。
10.根据权利要求1所述的制备栅氧层的工艺,其特征在于,还包括:
在进行所述退火工艺前,采用7℃/min-13℃/min的温度上升速度,将反应腔内的温度上升至所述退火工艺所要求的温度值;
在所述半导体衬底进行卸载工艺前,采用1℃/min-5℃/min的温度下降速度,将反应腔内的温度降低至卸载工艺所要求的温度值。
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US6797644B2 (en) * | 2000-08-01 | 2004-09-28 | Texas Instruments Incorporated | Method to reduce charge interface traps and channel hot carrier degradation |
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