CN103390568A - Method for monitoring MOS device threshold voltage drift - Google Patents
Method for monitoring MOS device threshold voltage drift Download PDFInfo
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- CN103390568A CN103390568A CN2012101393367A CN201210139336A CN103390568A CN 103390568 A CN103390568 A CN 103390568A CN 2012101393367 A CN2012101393367 A CN 2012101393367A CN 201210139336 A CN201210139336 A CN 201210139336A CN 103390568 A CN103390568 A CN 103390568A
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- tot
- silicon chip
- threshold voltage
- bias
- mos device
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Abstract
The invention provides a method for monitoring MOS device threshold voltage drift and belongs to the field of semiconductor device measuring and testing technologies. According to the method, after gate medium layer preparation is finished, on-line monitoring on a Qtot and/or Dit value of a silicon wafer is carried out, and the threshold voltage drift of an MOS device prepared through the silicon wafer is estimated according to the Qtot and/or Dit value, wherein the Qtot represents all electric charges inside a gate medium layer, and the Dit represents the interface state density between the gate medium layer and a silicon substrate. The method for monitoring MOS device threshold voltage drift is good in timeliness and beneficial to reducing influences on product yields by the threshold voltage drift.
Description
Technical field
The invention belongs to the technical field of measurement and test of semiconductor device, relate to a kind of can the realization effectively in advance MOS(Metal-Oxide-Semiconductor, metal-oxide semiconductor (MOS)) method monitored of the threshold voltage shift of device.
Background technology
Along with the development of semiconductor technology, technology constantly lifting of generation, processing step more (the flow time is longer), the characteristic size of MOS device constantly reduces, and the thickness of gate dielectric layer also constantly reduces.Threshold voltage (V according to the MOS device
TH) Computing Principle, along with the technology progress in generation, the various factors in manufacture process is also obvious all the more on the impact of threshold voltage, will be reflected in like this in the drift of threshold voltage.Therefore, be to improve product yield, the monitoring threshold voltage shift ever more important that seems.Generally, if the Taste threshold voltage drift need to make adjustment to avoid threshold drift at aspects such as techniques.
The CV(capacitance-voltage of MOS device) curved measurement is the important means that characterizes the threshold voltage of MOS device.From the CV curve, can reflect the flat band voltage (V of mos capacitance
FB), V
FBCan be with for semiconductor surface in the MOS structure and even up (being the flat rubber belting state) required additional voltage, according to the physical principle of threshold voltage, V
FBCan be understood as one of part of threshold voltage, therefore, during the flat band voltage drift, the threshold voltage of MOS device substantially also will produce drift.
Drift for monitoring MOS device threshold voltage, usually introduce WAT(Wafer Accept Test in the manufacture process of MOS device, but the wafer acceptance test) test process, by measuring the CV(capacitance-voltage of MOS device) curve, if find its flat band voltage (V
FB) drift is arranged, can reflect that also there is drift in threshold voltage.in current semiconductor manufacturing factory, the complicated process of preparation of MOS device, processing step is many, be prepared into the WAT test from completing gate dielectric layer, time interval long (general manufactory in reach 1 month) and substantially completed the preparation technology of MOS device, and in this time interval scope, may complete the preparation of many (for example up to ten thousand) gate dielectric layers on makers' production line, if it is serious to test out threshold voltage shift, in interval, probably all there is the threshold voltage shift phenomenon in manufacturing MOS device during this period of time, the serious waste production capacity also reduces yield greatly like this.Therefore, in existing this method for supervising, the monitoring hysteresis to threshold voltage shift, can not meet the requirement that semiconductor is made.
In view of this, be necessary to propose a kind of method that new monitoring MOS device threshold voltage drifts about.
Summary of the invention
The object of the invention is to, monitor ahead of time the drift of MOS device threshold voltage.
For realizing above purpose or other purposes, the invention provides a kind of method with the MOS of monitoring device threshold voltage drift, wherein, and after the gate dielectric layer preparation is completed, the Q of this silicon chip of on-line monitoring
totAnd/or D
itValue, and pass through Q
totAnd/or D
itThe threshold voltage shift of the MOS device that this silicon chip of value prediction is prepared;
Wherein, Q
totAll electric charges that represent described gate dielectric layer inside, D
itRepresent the interface state density between described gate dielectric layer and silicon substrate.
According to the method for supervising of one embodiment of the invention, wherein, the method comprises the following steps:
Complete the gate dielectric layer preparation on the silicon substrate of silicon chip;
This silicon chip is placed on tester table, and to the surperficial biascharge of this silicon chip;
The surface of the described silicon substrate of irradiation;
Measure the V of this silicon chip
s, draw Q
Bias-V
sRelation curve;
According to Q
Bias-V
sRelation curve calculates Q
Bias-SPV relation curve;
According to Q
Bias-SPV relation curve calculates Q
tot
According to Q
totAnd Q
Bias-V
sRelation curve calculates D
it
Judge respectively Q
totAnd/or D
itWhether depart from its corresponding predetermined range value;
If be judged as "Yes", the threshold voltage of explaining the MOS device of the prepared formation of this silicon chip will drift about;
Wherein, Q
BiasThe surperficial biascharge of expression silicon chip, V
sThe surface voltage of expression silicon chip, the surface photovoltage of SPV statement silicon chip.
Preferably, calculating Q
totThe time, Q
tot=-Q
Bias︱ SPV=0.
Preferably, arrange mute in described silicon chip, the Q that on-line monitoring is described mute
totAnd/or D
itValue is to reflect the Q of described silicon chip
totAnd/or D
itValue.
Technique effect of the present invention is that this method for supervising can be completed after the gate dielectric layer preparation is completed, realized online effective monitoring, has improved the ageing of monitoring, is conducive to reduce the impact that product yield is produced because of threshold voltage shift.
Description of drawings
From following detailed description by reference to the accompanying drawings, will make above and other purpose of the present invention and advantage more fully clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the schematic flow sheet of the method for the monitoring MOS device threshold voltage drift that provides according to one embodiment of the invention.
Embodiment
What below introduce is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand,, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementations that one of ordinary skill in the art can propose mutually to replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or restriction to technical solution of the present invention.
Analyze discovery by the applicant, affect the flat band voltage (V of MOS device
FB) factor mainly comprise: Q
totAnd D
itQ wherein
totAll electric charges of expression gate dielectric layer inside, comprise movable electric charge in fixed charge, gate dielectric layer, ionization trap etc.; D
itInterface state density between expression gate dielectric layer and channeled substrate.And found through experiments, when drift occurs in threshold voltage, V
FBAlso produce drift, correspondingly, Q
totAnd/or D
itAlso occurred abnormal.
The schematic flow sheet of the method for the monitoring MOS device threshold voltage drift that provides according to one embodiment of the invention is provided.In the method embodiment, the applicant is according to above discovery, by on-line measurement or monitoring Q
totAnd D
it, know in advance on this silicon chip whether the threshold voltage that will prepare the MOS device in the chip that forms can drift about, rather than etc. silicon chip in running through all MOS preparation process, just carry out WAT and test to monitor its threshold voltage situation.Therefore, the monitoring of threshold voltage can be done sth. in advance with respect to preparation technology's flow process of MOS device.Particularly, method embodiment illustrated in fig. 1 comprises following concrete steps.
At first, step S110, complete the preparation of gate dielectric layer on the silicon substrate of silicon chip.In this step, the silicon chip that need to prepare the MOS device thereon is generally multi-disc, it adopts same process step and process conditions, be typically by batch carrying out, in this embodiment, the threshold voltage of the MOS device that wish on the silicon chip of a batch is wherein formed is monitored in advance, in the silicon chip of this batch, can arrange to test Q
totAnd/or D
itMute (Dummy Wafer), substantially reflect the Q of this batch silicon chip by the result of this mute built-in testing
totAnd/or D
itCertainly, this mute can also be used as other tests etc.
Further, step S120, be placed on tester table mute, and to mute surperficial biascharge Q
Bias.In this embodiment, the board of test adopts the QUANTOX tester table, by this board,, to silicon chip upper offset electric charge, for example, adopts the mode biascharge of scanning biasing, and the scope of its scanning for example can be-5E7C/cm
2To 5E7C/cm
2.In this step, after finishing, the gate dielectric layer preparation namely starts to measure, realized on-line measurement.
Further, step S130, strong illumination surface of silicon.In this step, utilized the photo-generated carrier effect of silicon chip.When high light moment is radiated at surface of silicon, can produces nonequilibrium charge carrier and distribute silicon substrate is inner, and then can change surface potential.In this embodiment, the intensity of irradiation light intensity is roughly luminaire and is biased in the light intensity of sending in the scope of 0.5V to 3V.
Further, step S140, after the strong illumination surface of silicon, measure mute surface voltage V
s, draw Q
Bias-V
sRelation curve.In this step, do not carry out strong illumination in measuring process; Measure surface voltage V
sAfter, those skilled in the art can obtain Q
Bias-V
sRelation curve.
Further, step S150, according to Q
Bias-V
sRelation curve calculates Q
Bias-SPV relation curve, wherein SPV is surface photovoltage.In this step, at Q
Bias-V
sIn the situation that relation curve has provided, those skilled in the art, can calculate Q
Bias-SPV relation curve.
Further, step S160, according to Q
Bias-SPV relation curve calculates Q
tot.At Q
BiasIn-SPV relation curve, when SPV=0, the Q that it is corresponding
BiasWith the Q in gate dielectric layer
totEqual and opposite in direction, the corresponding Q in SPV=0 place
BiasBe Q
totSize (be Q
tot=-Q
Bias︱ SPV=0).
Further, step S170, according to Q
totAnd Q
Bias-V
sRelation curve calculates D
it.In this embodiment, at Q
BiasOn axle, 0 to-Q
totThe Q of correspondence in scope
Bias-V
sIn relation curve, the slope that calculates the extension of its curved section calculates Q
it.
Further, step S180, judgement Q
totAnd D
itWhether depart from predetermined range value.In this step, Q
totAnd D
itAll respectively to a predetermined range value should be arranged, when threshold voltage is normal when flat band voltage normal (also), Q
totAnd D
itShould change in predetermined range value respectively.This predetermined range value can be determined according to factors such as threshold voltage size, redundancy range of drift.If Q
totDepart from its predetermined range value, and/or D
itDepart from its predetermined range value, show that the threshold voltage of the MOS device that forms based on this gate dielectric layer will drift about, it generally can obtain corresponding checking in the CV curve test of its WAT test.
Further, step S190, if be judged as "Yes", the threshold voltage of the MOS device of the chip of the prepared formation of this batch silicon substrate will drift about.In this step,, by measuring mute, can reflect the threshold voltage situation of the MOS device of the chip that the preparation of this batch silicon chip forms.In the situation that threshold voltage will drift about, can stop the preparation of MOS device, adjustment preparation technology parameter etc. is realized the normal of threshold voltage.Like this, before Taste threshold voltage produces drift, prevented the processed manufacturing of too much silicon chip, be conducive to improve yield, reduced costs.
Simultaneously, step S210, will be normal if be judged as "No" monitoring feedback threshold voltage; Proceed other processing steps of MOS device preparation.
So far, realized monitoring to the threshold voltage shift of MOS device.Can find Q by above method for supervising process
totAnd D
itMeasurement can canbe used on line, for example, can complete in 2 hours and just can measure Q in the gate dielectric layer preparation
totAnd D
it, the threshold voltage of the MOS device that wish forms is monitored (rather than monitoring after waiting the MOS device to be completed into) in advance again, has improved the ageing of monitoring, is conducive to reduce because of the impact of threshold voltage shift on the product yield generation.
Need to prove, in above embodiment, Q
totAll electric charges that represent described gate dielectric layer inside, D
itRepresent the interface state density between described gate dielectric layer and silicon substrate, Q
BiasThe surperficial biascharge of expression silicon chip, V
sThe surface voltage of expression silicon chip, the surface photovoltage of SPV statement silicon chip.
Need to prove, the applicant finds, at Q
totAnd D
itIn one substantially understand correspondence and the threshold voltage shift situation occurs while departing from its corresponding predetermined range value, therefore, in other embodiments, also control measurement Q only
totAnd D
itIn one realize the threshold voltage of MOS device is monitored.
Above example has mainly illustrated the method for monitoring MOS device threshold voltage of the present invention drift.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, in the situation that do not break away from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (4)
1. a method of monitoring the drift of MOS device threshold voltage, is characterized in that, after the gate dielectric layer preparation is completed, and the Q of this silicon chip of on-line monitoring
totAnd/or D
itValue, and pass through Q
totAnd/or D
itThe threshold voltage shift of the MOS device that this silicon chip of value prediction is prepared;
Wherein, Q
totAll electric charges that represent described gate dielectric layer inside, D
itRepresent the interface state density between described gate dielectric layer and silicon substrate.
2. the method for claim 1, is characterized in that, the method comprises the following steps:
Complete the gate dielectric layer preparation on the silicon substrate of silicon chip;
This silicon chip is placed on tester table, and to the surperficial biascharge of this silicon chip;
The surface of the described silicon substrate of irradiation;
Measure the V of this silicon chip
s, draw Q
Bias-V
sRelation curve;
According to Q
Bias-V
sRelation curve calculates Q
Bias-SPV relation curve;
According to Q
Bias-SPV relation curve calculates Q
tot
According to Q
totAnd Q
Bias-V
sRelation curve calculates D
it
Judge respectively Q
totAnd/or D
itWhether depart from its corresponding predetermined range value;
If be judged as "Yes", the threshold voltage of explaining the MOS device of the prepared formation of this silicon chip will drift about;
Wherein, Q
BiasThe surperficial biascharge of expression silicon chip, V
sThe surface voltage of expression silicon chip, the surface photovoltage of SPV statement silicon chip.
3. method as claimed in claim 2, is characterized in that, calculating Q
totThe time, Q
tot=-Q
Bias︱ SPV=0.
4. method as claimed in claim 1 or 2, is characterized in that, arranges mute in described silicon chip, the Q that on-line monitoring is described mute
totAnd/or D
itValue is to reflect the Q of described silicon chip
totAnd/or D
itValue.
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|---|---|---|---|
| CN201210139336.7A CN103390568B (en) | 2012-05-08 | 2012-05-08 | A kind of method monitoring MOS device threshold voltage drift |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210139336.7A CN103390568B (en) | 2012-05-08 | 2012-05-08 | A kind of method monitoring MOS device threshold voltage drift |
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| Publication Number | Publication Date |
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| CN103390568A true CN103390568A (en) | 2013-11-13 |
| CN103390568B CN103390568B (en) | 2016-03-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851818A (en) * | 2014-02-14 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Method and device for detecting defects of dielectric layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011404A (en) * | 1997-07-03 | 2000-01-04 | Lucent Technologies Inc. | System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor |
| JP2003347378A (en) * | 2002-05-23 | 2003-12-05 | Toyota Central Res & Dev Lab Inc | Threshold deriving method for abnormality decision of gate insulating film and inspecting method of semiconductor element using the threshold |
| CN101154608A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid medium layer and estimating its electrical parameter |
-
2012
- 2012-05-08 CN CN201210139336.7A patent/CN103390568B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011404A (en) * | 1997-07-03 | 2000-01-04 | Lucent Technologies Inc. | System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor |
| JP2003347378A (en) * | 2002-05-23 | 2003-12-05 | Toyota Central Res & Dev Lab Inc | Threshold deriving method for abnormality decision of gate insulating film and inspecting method of semiconductor element using the threshold |
| CN101154608A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid medium layer and estimating its electrical parameter |
Non-Patent Citations (1)
| Title |
|---|
| 张延庆等: "低温低剂量率下金属-氧化物-半导体器件的辐照效应", 《物理学报》, vol. 50, no. 12, 20 December 2001 (2001-12-20), pages 2434 - 2438 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851818A (en) * | 2014-02-14 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Method and device for detecting defects of dielectric layer |
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| CN103390568B (en) | 2016-03-02 |
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