CN103378805B - Switching type capacitive circuit and method for controlling switching type capacitive circuit - Google Patents
Switching type capacitive circuit and method for controlling switching type capacitive circuit Download PDFInfo
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- CN103378805B CN103378805B CN201210124766.1A CN201210124766A CN103378805B CN 103378805 B CN103378805 B CN 103378805B CN 201210124766 A CN201210124766 A CN 201210124766A CN 103378805 B CN103378805 B CN 103378805B
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Abstract
Disclosed are a switching type capacitive circuit and a method for controlling the switching type capacitive circuit. The switching type capacitive circuit comprises an inverter, a first capacitor and a first switch unit, wherein the inverter is used for receiving a control signal to generate an inverting control signal corresponding to the control signal, the first capacitor is coupled between a first output end and a first endpoint, the first switch unit is used for receiving a first input signal and a second input signal and coupling the second input signal selectively to the first endpoint according to the first input signal, the first input signal is determined by either the control signal or the inverting control signal, and the second input signal is determined by either the control signal or the inverting control signal.
Description
Technical field
The present invention with regard to switch capacitor circuit, espespecially a kind of using delayed control signal and produce inverted control signal
The switch capacitor circuit switching over, and its related control method.
Background technology
In communication system now, local oscillated signal (local oscillation signal, LO signal) is main
Voltage controlled oscillator (voltage-controlled oscillator, VCO) to be passed through is producing.Common for comprising inductance capacitance
Shake for the voltage controlled oscillator of groove circuit (inductor-capacitor tank circuit, LC tank circuit), by
In it, there is good quality factor (quality factor) and signal degree of purity (signal purity), therefore standard can be provided
True local oscillated signal is to lift RF transceiver (radio frequency transceiver, RF transceiver)
Sensitivity (sensitivity).
In general, the inductance on chip occupies sizable area, therefore it will usually be changed by adjusting capacitance
The frequency of oscillation of voltage controlled oscillator, wherein switch-capacitor array (switch-capacitor array) to be produced according to switching voltage
Raw discontinuous switch-capacitor value.However, the switch capacitor circuit of switch-capacitor array may produce junction capacitance effect
(junction capacitance effect), and the transistor among switch capacitor circuit may be defeated because of coupling
Go out the voltage at end and unexpectedly turn on, thus reduce the performance of voltage controlled oscillator.
Accordingly, it would be desirable to a kind of quality of handoff that not only can lift switch capacitor circuit, and hardly increase extra
Circuit layout area innovative circuits design, to solve the above problems.
Content of the invention
In view of this, an object of the present invention is to provide one kind using delayed control signal and to produce anti-phase control letter
Number come the switch capacitor circuit to switch over and its related control method, to solve the above problems.
According to embodiments of the invention, it discloses a kind of switch capacitor circuit.It is anti-that this switch capacitor circuit comprises one
Phase device, one first electric capacity and a first switch unit.This phase inverter to produce corresponding to this control in order to receive a control signal
One inverted control signal of signal processed.This first electric capacity is coupled between one first outfan and a first end point.This first
Switch element is in order to receive one first input signal and one second input signal, and carrys out selectivity according to this first input signal
This second input signal is coupled to this first end point by ground.This first input signal is by this control signal and this inverted control signal
One of them determining, and this second input signal is wherein another by this control signal and this inverted control signal
To determine.
According to embodiments of the invention, it separately discloses a kind of switch capacitor circuit.This switch capacitor circuit comprises one
Phase inverter, an electric capacity and a switch element.This phase inverter in order to produce an inverted control signal according to a control signal.Should
Electric capacity is coupled between an outfan and end point.This switch element have couple a drain electrode of this end points, to receive this anti-phase
One source electrode of control signal and the grid being controlled according to this control signal.
According to embodiments of the invention, it discloses a kind of method controlling a switch capacitor circuit.This switching type capacitor
Circuit comprises an electric capacity.This electric capacity is coupled between an outfan and end point.The method comprises：Receive a control signal；
To produce according to this control signal to should control signal an inverted control signal；And to select according to one first input signal
Selecting property one second input signal is coupled to this end points, wherein this first input signal is by this control signal and this anti-phase control
One of them of signal is determining, and this second input signal is wherein another by this control signal and this inverted control signal
One determining.
The disclosed suitching type electricity being switched over using delayed control signal and generation inverted control signal
Capacitive circuit, it not only can have the high quality factor of differential switching type capacitor structure, and suitching type circuit can be avoided to be applied to
Produced junction capacitance effect and can prevent switch element from surprisingly turning on during voltage controlled oscillator.Additionally, it is disclosed
Switch capacitor circuit hardly increase extra area, without complicated circuit layout.
Brief description
Fig. 1 is the schematic diagram of a first embodiment of switch capacitor circuit of the present invention.
Fig. 2 is the schematic diagram of a second embodiment of switch capacitor circuit of the present invention.
Fig. 3 is the signal timing diagram of the switch capacitor circuit shown in Fig. 2.
Fig. 4 is the schematic diagram of a 3rd embodiment of switch capacitor circuit of the present invention.
Fig. 5 is the signal timing diagram of the switch capacitor circuit shown in Fig. 4.
Fig. 6 is the schematic diagram of a fourth embodiment of switch capacitor circuit of the present invention.
Wherein, description of reference numerals is as follows：
100th, 200,400,600 switch capacitor circuit
110 phase inverters
120th, 230,240 switch element
C1, C2 electric capacity
D delay cell
M1, M2, M3 transistor
N1, N2 end points
V_OUT1, V_OUT2 outfan
Specific embodiment
Although the advantage of disclosed switch capacitor circuit is based on inductance capacitance among voltage controlled oscillator altogether
Shake groove circuit application illustrating, but this is not used for the restriction as the present invention, in other words, disclosed suitching type
Condenser network can be applicable to the suitching type electricity of (but being not limited to) voltage controlled oscillator, resonance trough circuit or other scalable frequency
Hold the circuit of array.
Refer to Fig. 1, Fig. 1 is the schematic diagram of a first embodiment of switch capacitor circuit of the present invention.Switching type capacitor
Circuit 100 comprises a phase inverter (inverter) 110, one first electric capacity C1 and a first switch unit (switch unit)
120.Phase inverter 120 is to receive control signal CS to produce the inverted control signal ICS corresponding to control signal CS.
First electric capacity C1 is coupled between one first outfan V_OUT1 and first end point N1.First switch unit 120 be in order to
Receive one first input signal S_IN1 and one second input signal S_IN2, and to select according to the first input signal S_IN1
Property ground the second input signal S_IN2 is coupled to first end point N1, the wherein first input signal S_IN1 be by control signal CS with
One of them of inverted control signal ICS is determining, and the second input signal S_IN2 is by control signal CS and anti-phase control
Signal ICS wherein another determining.
For example, in this embodiment, first switch unit 120 can be a transistor M1, and the grid of transistor M1
Pole, source electrode and drain electrode are respectively coupled to the first input signal S_IN1, the second input signal S_IN2 and first end point N1.Please note
Meaning, in this embodiment, first switch unit 120 directly receives control signal CS to be come as the first input signal S_IN1, and
Directly receive inverted control signal ICS to come as the second input signal S_IN2, however, above only needing for explanation, be not used for
Restriction as the present invention.In a design variation, first switch unit 120 can directly receive inverted control signal ICS to do
For the first input signal S_IN1, and directly receive control signal CS and come as the second input signal S_IN2 that is to say, that anti-
Phase device 110 also can be coupled to the grid of transistor M1.In another design variation, control signal CS can be first via suitable signal
Process (for example, zooming in or out), just as the first input signal S_IN1 being fed into first switch unit 120 and anti-phase
Control signal ICS can be first via suitable signal processing (for example, zooming in or out), and just conduct is fed into first switch unit
120 the second input signal S_IN2.In this embodiment, it is should in the first input signal S_IN1 (that is, control signal CS)
In the case of first level (for example, high-voltage level), the second input signal S_IN2 that the source electrode of transistor M1 is coupled (
That is, inverted control signal ICS) it is low voltage level, therefore, transistor M1 can be switched on, and electric current flow to crystalline substance from first end point N1
Body pipe M1 (that is, first switch unit 120)；It is this second electrical level in the first input signal S_IN1 (that is, control signal CS)
In the case of (for example, low voltage level), the first input signal S_IN1 that the source electrode of transistor M1 is coupled (that is, anti-phase control
Signal ICS processed) it is high-voltage level, therefore, even if transistor M1 can be cut off, leakage current (leakage current) still may be used
It flow to first end point N1 to lift the voltage of first end point N1 from transistor M1 (that is, first switch unit 120), and then reduce
The impact of junction capacitance effect.
Refer to Fig. 2, Fig. 2 is the schematic diagram of a second embodiment of switch capacitor circuit of the present invention, wherein suitching type
Condenser network 200 adopts the switching type capacitor shown in the design concept of differential type (differential) circuit and Fig. 1 simultaneously
The design concept of circuit 100.Switch capacitor circuit 200 comprises the phase inverter 110 shown in Fig. 1, the first electric capacity C1 and first opens
Close unit 120, one second electric capacity C2, a second switch unit 230 and one the 3rd switch element 240.Second electric capacity C2 couples
Between one second outfan V_OUT2 and one second end points N2.Second switch unit 230 is coupled to first end point N1 and
Between two end points N2, in order to optionally N1 first end point to be coupled to the second end points N2 according to the first input signal S_IN1.
3rd switch element 240 is coupled to the second end points N2, in order to receive the first input signal S_IN1 and the second input signal S_
IN2, and optionally the second input signal S_IN2 to be coupled to the second end points N2 according to the first input signal S_IN1.It is worth
It is noted that the first input signal S_IN1 is to be determined with one of them of inverted control signal ICS by control signal CS, with
And second input signal S_IN2 be to be determined by the other in which of control signal CS and inverted control signal ICS.
For example, in this embodiment, first switch unit 120, second switch unit 230 and the 3rd switch element
240 are respectively a first transistor M1, a transistor seconds M2 and third transistor M2.First, second and third transistor
The grid of M1～M3 is all coupled to the first input signal S_IN1, and the drain electrode of first and second transistor M1 and M2 is all coupled to
End point N1, first and the source electrode of third transistor M1 and M3 be all coupled to the second input signal S_IN2, and transistor seconds
The drain electrode of the source electrode of M2 and third transistor M3 is all coupled to the second end points N2.In the first input signal S_IN1 (that is, controlling
Signal CS) for this first level (for example, high-voltage level) in the case of, first and third transistor M1 and M3 source electrode institute coupling
The second input signal S_IN2 (that is, inverted control signal ICS) connecing is low voltage level, therefore, first, second and third
Transistor M1～M3 all can be switched on, additionally, first and second electric capacity C1 and C2 can be considered preferable ground capacity.Defeated first
In the case of entering signal S_IN1 (that is, control signal CS) for this second electrical level (for example, low voltage level), first and the 3rd
The first input signal S_IN1 (that is, inverted control signal ICS) that the source electrode of transistor M1 and M3 is coupled is high voltage electricity
Flat, even if first, second and third transistor M1～M3 all can be cut off, leakage current still can flow to first end point from transistor M1
N1 is lifting the voltage of first end point N1, and flow to the second end points N2 to lift the voltage of the second end points N2 from transistor M3,
The conducting of transistor seconds M2 not only can be avoided, also can reduce the impact of junction capacitance effect.
It should be noted that in general, the voltage of the second end points N2 will not be too many by leakage current boosted voltage
(for example, hundreds of millivolt), therefore, when the voltage of the second end points N2 couples larger voltage via the second outfan V_OUT2,
The voltage of the second end points N2 still may be less than the grid voltage of transistor seconds M2 so that transistor seconds M2 unexpectedly leads
Logical.Refer to Fig. 3, Fig. 3 is the signal timing diagram of the switch capacitor circuit shown in Fig. 2.From the figure 3, it may be seen that time point T1 it
Before, control signal CS is in high-voltage level, and first, second and third transistor M1～M3 is conducting state, and first
The voltage of end points N1 and the second end points N2 all can be considered ground voltage (that is, no-voltage).When time point T1, control signal CS
Low voltage level is switched to by high-voltage level, transistor seconds M2 ideally should be cut-off state.In first and second end points
In the case of the voltage of N1 and N2 couples larger voltage via first and second outfan V_OUT1 and V_OUT2 respectively, the second end
The voltage of point N2 is less than the grid voltage (that is, no-voltage) of transistor seconds M2 so that transistor seconds M2 unexpectedly turns on,
Thus frequency of oscillation accuracy and the signal degree of purity of voltage controlled oscillator may be affected.
See also Fig. 4 and Fig. 5.Fig. 4 is the schematic diagram of a 3rd embodiment of switch capacitor circuit of the present invention, with
And the signal timing diagram that Fig. 5 is the switch capacitor circuit shown in Fig. 4.Switch capacitor circuit 400 is based on the switching shown in Fig. 2
The structure of formula condenser network 200, main difference is that suitching type circuit 400 additionally comprises a delay cell (delay between the two
Unit) D, wherein delay cell D are coupled to first, second and third switch element 120,230 and 240, and setting is to postpone first
Input signal S_IN1 is producing the first input signal S_IN1 after delay.In addition, after second switch unit 230 is according to postponing
First input signal S_IN1 optionally first end point N1 to be coupled to the second end points N2, and the 3rd switch element 240 according to
Optionally the second input signal S_IN2 to be coupled to the second end points N2 according to the first input signal S_IN1 after postponing.First
The time that input signal S_IN1 is delayed by, or the delay caused by delay cell D, can according to the resistance value of the first electric capacity C1 and
The resistance value of first switch unit 120 is arranging, or the resistance value of the second electric capacity C2 and the resistance value of the 3rd switch element 240 come
Determined.As shown in Figure 5, before time point T1, control signal CS is in high-voltage level, and first, second and third is brilliant
Body pipe M1～M3 is conducting state, and the voltage of first end point N1 and the second end points N2 all can be considered ground voltage (that is,
No-voltage).Between time point T1 and time point T2, (that is, during delay periods TD) are although control signal CS is handed over
For low voltage level, but the signal received by the grid of transistor seconds M2 is still in high-voltage level, additionally, first and
The source electrode of three transistor M1 and M3 is all coupled to the inverted control signal ICS of tool high-voltage level.During delay periods TD, the
The voltage of end point N1 and the second end points N2 can be charged to a precharging voltage value (for example, above-mentioned high-voltage level).As above
Described, delay periods TD can be according to the resistance value of the resistance value of the first electric capacity C1 and first switch unit 120, or the second electric capacity C2
Resistance value and the resistance value of the 3rd switch element 240 to be determined, therefore, delay caused by delay cell D and this is pre-
Depending on charging voltage value visual actual design consideration/demand.Delay cell D is in order to prevent shaking of first end point N1 and the second end points N2
Swing voltage and be less than 0.After time point T2, because the voltage of first end point N1 and the second end points N2 has been charged to this precharge
Pressure value, and the grid of transistor M2 receive delayed after the first input signal S_IN1 (it has low voltage level), institute
So that the situation occurring transistor seconds M2 surprisingly to turn on can be avoided.In short, the voltage of first end point N1 and the second end points N2 in
Sufficiently high magnitude of voltage can be promoted to during delay periods TD to avoid transistor seconds M2 surprisingly to turn on, and then be lifted voltage-controlled
The frequency of oscillation accuracy of agitator and signal degree of purity.
Note that above-described corresponding between first and second input signal and control signal and inverted control signal
Relation only needing for explanation, is not used for the restriction as the present invention.For example, in a design variation, first switch list
Unit 120 can directly receive inverted control signal ICS and come as the first input signal S_IN1, and directly receives control signal CS
Come as the second input signal S_IN2.That is, phase inverter 110 is coupled to the grid of the first transistor M1, delay cell D
The source electrode of the first transistor M1 and third transistor M3 then can be coupled to.Or that, in another embodiment, can be single by postponing
First D and phase inverter 110 phase double replacement or combination.
Additionally, the switch capacitor circuit 100 that single-ended (single-ended) shown in Fig. 1 exports may also be employed Fig. 4 institute
The design concept of the delay cell shown is to lift the performance of voltage controlled oscillator.Refer to Fig. 6, Fig. 6 is switching type capacitor of the present invention
The schematic diagram of one fourth embodiment of circuit, wherein switch capacitor circuit 600 is based on the switch capacitor circuit shown in Fig. 1
100 structure, main difference is that suitching type circuit 600 additionally comprises delay cell D, wherein delay cell D between the two
It is coupled to first switch unit 120, setting to produce the first input signal S_ after delay to postpone the first input signal S_IN1
IN1.In addition, first switch unit 120 comes optionally by the second input signal according to the first input signal S_IN1 after postponing
S_IN2 is coupled to first end point N1, and the time that the wherein first input signal S_IN1 is delayed by can be according to the impedance of the first electric capacity C1
The resistance value of value and first switch unit 120 is determining.Because those skilled in the art should via the above-mentioned related description of reading
Understand the operational details of switch capacitor circuit 600 easily, therefore further instruction here just repeats no more.
From the foregoing, disclosed switch capacitor circuit can be applicable to (but being not limited to) VCO
The circuit of the switching type capacitor array of device, resonance trough circuit or other scalable frequency, therefore, is cut using disclosed
The formula condenser network of changing have can avoid suitching type circuit be applied to produced junction capacitance effect during voltage controlled oscillator, lifting pressure
The quality factor of controlled oscillator, and the advantages of prevent switch element from surprisingly turning on；Additionally, disclosed suitching type electricity
Capacitive circuit hardly increases extra area, without complicated circuit layout.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to the claims in the present invention protection domain
Change and modify, all should belong to the covering scope of the present invention.
Claims (12)
1. a kind of switch capacitor circuit is it is characterised in that comprise：
One phase inverter, to produce the inverted control signal corresponding to this control signal in order to receive a control signal；
One first electric capacity, is coupled between one first outfan and a first end point；
One first switch unit, in order to receive one first input signal and one second input signal, and according to this first input
Signal optionally this second input signal to be coupled to this first end point；
Wherein this first input signal to be determined by this control signal and this inverted control signal one of them, and this second
Input signal be by this control signal and this inverted control signal wherein another determining；And
One delay cell, is coupled to this first switch unit, and setting to produce being somebody's turn to do after delay to postpone this first input signal
First input signal；
Wherein this first switch unit comes optionally by this second input signal coupling according to this first input signal after postponing
It is connected to this first end point.
2. switch capacitor circuit as claimed in claim 1 it is characterised in that this first switch unit be a transistor, with
And the grid of this transistor, source electrode and drain electrode are respectively coupled to this first input signal, this second input signal and this first end
Point.
3. switch capacitor circuit as claimed in claim 1 it is characterised in that the time that this first input signal is delayed by be
To determine according to the resistance value of this first electric capacity and the resistance value of this first switch unit.
4. switch capacitor circuit as claimed in claim 1 is it is characterised in that this delay cell is in order to prevent this first end point
An oscillating voltage be less than 0.
5. switch capacitor circuit as claimed in claim 1 is it is characterised in that additionally comprise：
One second electric capacity, is coupled between one second outfan and one second end points；And
One second switch unit, is coupled between this first end point and this second end points, in order to come according to this first input signal
Optionally this first end point is coupled to this second end points；And
One the 3rd switch element, is coupled to this second end points, in order to receive this first input signal and this second input signal,
And optionally this second input signal to be coupled to this second end points according to this first input signal.
6. switch capacitor circuit as claimed in claim 5 is it is characterised in that this first switch unit, this second switch list
Unit and the 3rd switch element are respectively a first transistor, a transistor seconds and a third transistor；This first, second and
The grid of third transistor is all coupled to this first input signal；The drain electrode of this first and second transistor be all coupled to this first
End points；This first and the source electrode of third transistor be all coupled to this second input signal；And this transistor seconds source electrode and
The drain electrode of this third transistor is all coupled to this second end points.
7. switch capacitor circuit as claimed in claim 5 it is characterised in that：
Described delay cell is further coupled to this second, third switch element；
Wherein this second switch unit optionally to be coupled to this first end point according to this first input signal after postponing
This first input signal after this second end points, and the foundation delay of the 3rd switch element is come optionally by this second input
Signal is coupled to this second end points.
8. switch capacitor circuit as claimed in claim 7 it is characterised in that the time that this first input signal is delayed by be
According to the resistance value of this first electric capacity and the resistance value of this first switch unit, or the resistance value of this second electric capacity and the 3rd is opened
The resistance value closing unit is determining.
9. a kind of switch capacitor circuit is it is characterised in that comprise：
One phase inverter, in order to produce an inverted control signal according to a control signal；
One electric capacity, is coupled between an outfan and end point；
One switch element, has and couples a drain electrode of this end points, receives a source electrode of this inverted control signal and according to this control
Signal is come the grid to control；And
One delay cell, is coupled to this switch element, and setting to produce this control signal after delay to postpone this control signal；
Wherein this switch element is optionally this inverted control signal to be coupled to this according to this control signal after postponing
End points.
10. switch capacitor circuit as claimed in claim 9 it is characterised in that time that this control signal is delayed by be according to
To determine according to the resistance value of this electric capacity and the resistance value of this switch element.
11. switch capacitor circuits as claimed in claim 9 are it is characterised in that this delay cell is in order to prevent this end points
One oscillating voltage is less than 0.
12. a kind of control switch capacitor circuits methods it is characterised in that this switch capacitor circuit comprises an electric capacity,
This electric capacity is coupled between an outfan and end point, and the method comprises：
Receive a control signal；
To produce according to this control signal to should control signal an inverted control signal；
Optionally one second input signal to be coupled to this end points according to one first input signal, wherein this first input letter
Number it is to be determined with one of them of this inverted control signal by this control signal, and this second input signal is by this control
Signal and this inverted control signal wherein another determining；And
Postpone this first input signal to produce this first input signal after delay；
The step wherein optionally this second input signal being coupled to this end points comprises：
Optionally this second input signal to be coupled to this end points according to this first input signal after postponing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210124766.1A CN103378805B (en) | 2012-04-25 | 2012-04-25 | Switching type capacitive circuit and method for controlling switching type capacitive circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210124766.1A CN103378805B (en) | 2012-04-25 | 2012-04-25 | Switching type capacitive circuit and method for controlling switching type capacitive circuit |
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| CN103378805B true CN103378805B (en) | 2017-02-08 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574640A (en) * | 2003-06-20 | 2005-02-02 | 联发科技股份有限公司 | Switched capacitor circuit capable of eliminating clock feedthrough for vco |
| CN101051832A (en) * | 2006-03-29 | 2007-10-10 | 瑞昱半导体股份有限公司 | Error averaging switch capacitor circuit and method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10061241A1 (en) * | 2000-12-08 | 2002-06-27 | Infineon Technologies Ag | oscillator circuit |
| US6975156B2 (en) * | 2003-09-30 | 2005-12-13 | Mediatek Inc. | Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit and method thereof |
| US7710181B2 (en) * | 2007-08-20 | 2010-05-04 | Panasonic Corporation | Variable attenuator and wireless communication device |
| US8044739B2 (en) * | 2009-06-09 | 2011-10-25 | Qualcomm Incorporated | Capacitor switching circuit |
-
2012
- 2012-04-25 CN CN201210124766.1A patent/CN103378805B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574640A (en) * | 2003-06-20 | 2005-02-02 | 联发科技股份有限公司 | Switched capacitor circuit capable of eliminating clock feedthrough for vco |
| CN101051832A (en) * | 2006-03-29 | 2007-10-10 | 瑞昱半导体股份有限公司 | Error averaging switch capacitor circuit and method thereof |
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