CN103367160B - The method of forming a fin field effect transistor - Google Patents

The method of forming a fin field effect transistor Download PDF

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CN103367160B
CN103367160B CN201210101577.2A CN201210101577A CN103367160B CN 103367160 B CN103367160 B CN 103367160B CN 201210101577 A CN201210101577 A CN 201210101577A CN 103367160 B CN103367160 B CN 103367160B
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forming
fin
layer
field effect
effect transistor
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CN103367160A (en
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三重野文健
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中芯国际集成电路制造(上海)有限公司
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Abstract

一种鳍式场效应管的形成方法,包括:提供半导体衬底,所述半导体衬底表面形成有隔离层;形成贯穿所述隔离层、且一端位于半导体衬底内的鳍部,所述鳍部表面高于隔离层表面;形成位于所述隔离层表面、且横跨所述鳍部的顶部和侧壁的栅极结构;形成位于所述栅极结构侧壁和鳍部侧壁的伪侧墙;形成位于所述伪侧墙表面、且包裹所述鳍部的外延层;在形成所述外延层后去除所述伪侧墙。 Method of forming a fin field effect transistor, comprising: providing a semiconductor substrate, the semiconductor substrate is formed with a surface of the isolation layer; formed through the isolation layer, and an end portion of the fin in the semiconductor substrate, the fin the surface portion higher than the surface isolation layer; forming a spacer layer located on the surface and across the top of the gate structure and sidewall portion of the fin; forming a dummy gate structure side of said side wall portion and the sidewall of the fin wall; dummy spacers are formed in said surface, and the epitaxial layer portion enclosing said fins; after forming the epitaxial layer removing the dummy spacer. 本发明实施例形成的鳍式场效应管的性能好。 Good performance fin field effect transistor is formed according to embodiments of the present invention.

Description

鳍式场效应管的形成方法 The method of forming a fin field effect transistor

技术领域 FIELD

[0001] 本发明涉及半导体制造技术领域,尤其涉及一种鳍式场效应管的形成方法。 [0001] The present invention relates to semiconductor manufacturing technology, particularly to a method of forming a fin field effect transistor.

背景技术 Background technique

[0002] 随着半导体工艺技术的不断发展,工艺节点逐渐减小,后栅(gate-last)工艺得到了广泛应用,以获得理想的阈值电压,改善器件性能。 [0002] With the development of semiconductor technology, technology node decreases, the gate (gate-last) technology has been widely used to obtain a desired threshold voltage, improving device performance. 但是当器件的特征尺寸(CD,Critical Dimens1n)进一步下降时,即使采用后栅工艺,常规的MOS场效应管的结构也已经无法满足对器件性能的需求,多栅器件作为常规器件的替代得到了广泛的关注。 However, when the feature size of the device (CD, Critical Dimens1n) is further decreased, even if gate-last process, the structure of the conventional MOS FET has been unable to meet the demand for the performance of the device, a multi-gate device as an alternative to conventional devices has been Widespread concern.

[0003] 鳍式场效应管(Fin FET)是一种常见的多栅器件,图1示出了现有技术的一种鳍式场效应管的立体结构示意图。 [0003] The fin field effect transistor (Fin FET) is a common multi-gate device, FIG. 1 shows a perspective schematic view of the structure forming a fin field effect transistor of the prior art. 如图1所示,包括:半导体衬底10,所述半导体衬底10上形成有凸出的鳍部14,鳍部14 一般是通过对半导体衬底10刻蚀后得到的;介质层11,覆盖所述半导体衬底10的表面以及鳍部14的侧壁的一部分;栅极结构12,横跨在所述鳍部14上,覆盖所述鳍部14的顶部和侧壁,栅极结构12包括栅介质层(图中未示出)和位于栅介质层上的栅电极(图中未示出)。 1, comprising: a semiconductor substrate 10, 14, the fin portion 14 has a projecting fin portion 10 is formed on the semiconductor substrate is typically obtained after 10 by etching the semiconductor substrate; a dielectric layer 11, covering the surface of the semiconductor substrate 10 and a portion of the side wall portion 14 of the fin; gate structure 12 straddles the fin portion 14, covers the top and sidewalls of the fin portion 14, gate structures 12 comprising a gate dielectric layer (not shown) and a gate electrode on the gate dielectric layer (not shown). 对于Fin FET,鳍部14的顶部以及两侧的侧壁与栅极结构12相接触的部分都成为沟道区,即具有多个栅,有利于增大驱动电流,改善器件性能。 For Fin FET, and a top portion of the sidewall of the gate structure 12 on both sides of the fin contacting portions 14 have become a channel region, i.e. having a plurality of gate conducive to increasing the drive current, device performance improvement.

[0004] 然而,随着工艺节点的进一步减小,现有技术的鳍式场效应管的器件性能存在问题。 [0004] However, with further reduction process node, device performance problems of the prior art fin FET.

[0005] 更多关于鳍式场效应管的结构及形成方法请参考专利号为“US7868380B2”的美国专利。 [0005] More and on the method of forming a fin field effect transistor structure refer to Patent No. "US7868380B2" U.S. Pat.

发明内容 SUMMARY

[0006] 本发明解决的问题是提供一种器件性能好的半导体器件、鳍式场效应管的形成方法。 [0006] The present invention solves the problem to provide a good device performance semiconductor device, a method of forming a fin field effect transistor.

[0007] 为解决上述问题,本发明提供了一种鳍式场效应管的形成方法,包括: [0007] In order to solve the above problems, the present invention provides a method of forming a fin field effect transistor, comprising:

[0008] 提供半导体衬底,所述半导体衬底表面形成有隔离层; [0008] providing a semiconductor substrate, the semiconductor substrate is formed with a surface of the isolation layer;

[0009] 形成贯穿所述隔离层、且一端位于半导体衬底内的鳍部,所述鳍部表面高于隔离层表面; [0009] is formed through the isolation layer, and an end portion of the fin in the semiconductor substrate, the fin surface is higher than the surface of the insulating layer;

[0010] 形成位于所述隔离层表面、且横跨所述鳍部的顶部和侧壁的栅极结构; [0010] The isolation layer is formed at the surface of, and across the top of the gate structure and sidewall portion of the fin;

[0011] 形成位于所述栅极结构侧壁和鳍部侧壁的伪侧墙; [0011] The dummy spacer is formed in said sidewall of the gate structure and sidewall portion of the fin;

[0012] 形成位于所述伪侧墙表面、且包裹所述鳍部的外延层; [0012] The dummy spacer is formed in said surface of said epitaxial layer and wrapping the fin portion;

[0013] 在形成所述外延层后去除所述伪侧墙。 [0013] After removing the dummy spacer is formed in the epitaxial layer.

[0014] 可选地,所述伪侧墙的形成步骤包括:形成覆盖所述隔离层、鳍部和栅极结构的伪侧墙薄膜;去除位于所述隔离层表面、鳍部顶部的伪侧墙薄膜。 [0014] Alternatively, the dummy sidewall spacer forming step includes: forming the isolation layer covering the dummy film spacer fin and the gate structure; removing pseudo surface side of the top of the fin portion of the isolation layer wall film.

[0015] 可选地,所述伪侧墙薄膜的材料为氧化硅、氮化硅或氮氧化硅。 [0015] Alternatively, the dummy spacer film material is silicon oxide, silicon nitride or silicon oxynitride.

[0016] 可选地,所述位于鳍部侧壁的伪侧墙的高度与高于隔离层表面部分的鳍部的高度比小于等于1: 3。 [0016] Alternatively, the dummy spacers located at a height of fin portion and sidewall portion higher than the height of the fin surface portion of the spacer layer is less than 1: 3.

[0017] 可选地,所述位于鳍部侧壁的伪侧墙的高度与高于隔离层表面部分的鳍部的高度比大于等于1: 5。 [0017] Alternatively, the dummy spacers located at a height of fin portion and sidewall portion higher than the height of the fin surface portion of the spacer layer is greater than or equal to 1: 5.

[0018] 可选地,所述位于鳍部侧壁的伪侧墙的高度为10-30nm。 [0018] Alternatively, the sidewall portion positioned dummy spacer fin height of 10-30nm.

[0019] 可选地,所述位于鳍部侧壁的伪侧墙的厚度为3-10nm。 [0019] Alternatively, the dummy spacers positioned fin sidewall thickness of 3-10nm.

[0020] 可选地,所述外延层的材料为SiGe、SiC、SiN或SiP。 [0020] Alternatively, the material of the epitaxial layer is SiGe, SiC, SiN or SiP.

[0021] 可选地,所述外延层的形成工艺为选择性外延沉积工艺。 [0021] Alternatively, the process of forming a selective epitaxial layer is an epitaxial deposition process.

[0022] 可选地,还包括:在形成伪侧墙前,在所述栅极结构两侧的鳍部内掺杂形成源/漏区。 [0022] Optionally, further comprising: prior to forming the dummy spacers, doping of the gate in the fin structure is formed on both sides of the source / drain regions.

[0023] 可选地,还包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动绝缘层。 [0023] Optionally, further comprising: forming a flowable insulating layer covering the epitaxial layer, an isolation layer and a gate structure.

[0024] 可选地,所述可流动绝缘层的材料为氧化硅或氮化硅。 [0024] Alternatively, the flowable material of the insulating layer is silicon oxide or silicon nitride.

[0025] 可选地,还包括:对所述可流动绝缘层进行回流处理,使位于所述外延层和栅极结构表面的部分可流动绝缘层回流至相邻两个鳍部间的隔离层表面。 [0025] Optionally, further comprising: said insulating layer flow reflow process, so that part of said epitaxial layer located on the surface of the structure and the gate insulating layer of flowable reflux spacer layer between two adjacent fins to surface.

[0026] 可选地,所述可流动绝缘层的形成步骤包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动薄膜;对所述可流动薄膜进行氧化或氮化处理。 The step of forming [0026] Alternatively, the flowable insulating layer comprises: forming a flowable film covering the epitaxial layer, isolation layer and the gate structure; flowable film of the oxidizing or nitriding treatment.

[0027] 可选地,所述可流动薄膜的材料为硼磷硅玻璃、硼硅玻璃、磷硅玻璃、聚乙烯氧化硅、聚乙烯氮化硅或正硅酸乙酯。 [0027] Alternatively, the flowable material is a film borophosphosilicate glass, borosilicate glass, phosphosilicate glass, silicon oxide, polyethylene, polyethylene, silicon nitride, or TEOS.

[0028] 可选地,还包括:形成覆盖所述外延层、隔离层以及栅极结构的应力层。 [0028] Optionally, further comprising: forming an epitaxial layer overlying the isolation layer, and a stress layer gate structure.

[0029] 可选地,所述应力层的材料与所述外延层的材料相同,为SiGe、SiC、SiN或SiP。 [0029] Alternatively, the stress of the same material layer and the epitaxial layer is SiGe, SiC, SiN or SiP.

[0030] 可选地,所述应力层的形成工艺为原子层沉积工艺、化学气相沉积工艺、低压化学气相沉积工艺或等离子体化学气相沉积工艺。 [0030] Alternatively, the process of forming said stress layer is an atomic layer deposition process, a chemical vapor deposition process, a low pressure chemical vapor deposition process or a plasma chemical vapor deposition process.

[0031] 可选地,所述隔离层的材料为氧化硅、氮化硅或氮氧化硅。 [0031] Alternatively, the separation layer material is silicon oxide, silicon nitride or silicon oxynitride.

[0032] 可选地,所述栅极结构的形成步骤包括:形成覆盖所述鳍部和隔离层的栅介质薄膜;形成覆盖所述栅介质薄膜的栅电极薄膜;形成覆盖所述栅电极薄膜的硬掩膜层,所述硬掩膜层定义出栅极的形状、位置和大小;以所述硬掩膜层为掩膜,刻蚀所述栅电极薄膜和栅介质薄膜,形成栅极;形成位于所述栅极侧壁的侧墙。 [0032] Alternatively, the step of forming the gate structure comprises: forming a gate dielectric film covering the fin portions and the spacer layer; forming a gate electrode on the gate dielectric thin film; forming a thin film covering the gate electrode the hard mask layer, said hard mask layer defines the shape, size and position of the gate; to the hard mask layer as a mask, etching the gate electrode film and the gate dielectric film, forming a gate; forming a gate sidewall spacer is located.

[0033] 与现有技术相比,本发明的实施例具有以下优点: [0033] Compared with the prior art, embodiments of the present invention have the following advantages:

[0034] 本发明的实施例中,在鳍部侧壁形成伪侧墙,在所述伪侧墙的保护下,外延层仅形成在未被伪侧墙覆盖的鳍部表面,后续形成的外延层的体积较小,并且相邻两个鳍部表面的外延层不易接触,不会影响后续工艺的进行,且形成的鳍式场效应管的性能好。 Epitaxial Example [0034] In the present invention, the fin portion is formed in the sidewalls of the dummy spacers, pseudo-spacers under the protection of the epitaxial layer is formed only on the surface of the fin portion is not covered by the dummy spacers, subsequently formed small bulk layer, the epitaxial layer and adjacent two portions of the fin surfaces inaccessibility, does not affect the subsequent processes is performed, performance of the fin and forming a field effect transistor.

[0035] 进一步的,还包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动绝缘层。 [0035] Further, further comprising: forming a flowable insulating layer covering the epitaxial layer, an isolation layer and a gate structure. 之后,还对所述可流动绝缘层进行回流处理,使位于所述外延层和栅极结构表面的部分可流动绝缘层回流至相邻两个鳍部间的隔离层表面,提高了相邻两个鳍式场效应管之间的绝缘效果。 After the further insulating layer of the flowable reflow process, so that an epitaxial layer and the gate structure of the surface portion of the flowable insulating layer between the surface barrier at reflux for two adjacent fins to improve the two adjacent an insulating effect between the fin FET.

[0036] 更进一步的,还包括:形成覆盖所述外延层、隔离层以及栅极结构的应力层。 [0036] Still further, further comprising: forming an epitaxial layer overlying the isolation layer, and a stress layer gate structure. 所述应力层与所述外延层共同包裹所述鳍部表面,进一步提高了鳍式场效应管的沟道区的应力,使其沟道区的载流子迀移率增加,鳍式场效应管的性能好。 The stress layer and wrapping the joint surface of the fin portion of the epitaxial layer, to further improve the stress in the channel region of the fin field-effect transistor, so that carriers in the channel region increases Gan drift rate, fin field effect good performance of the tube.

附图说明 BRIEF DESCRIPTION

[0037] 图1是现有技术的鳍式场效应管的立体结构示意图; [0037] FIG. 1 is a schematic perspective view of a fin field effect transistor of the prior art;

[0038] 图2是本发明的实施例的鳍式场效应管的形成方法的流程示意图; [0038] FIG. 2 is a schematic flow diagram of a method of forming a fin field effect transistor of an embodiment of the present invention;

[0039] 图3、4、6_15是本发明的实施例的鳍式场效应管的形成过程的剖面结构示意图; [0039] FIG 3,4,6_15 is a schematic cross-sectional structure formed during fin FET embodiment of the present invention;

[0040] 图5是图4的俯视结构示意图。 [0040] FIG. 5 is a schematic top view of the structure of FIG.

具体实施方式 Detailed ways

[0041] 正如背景技术所述,现有技术随着工艺节点的进一步减小,形成的鳍式场效应管的性能稳定性有待提尚。 [0041] As the background art, with the prior art to further reduce the process nodes, performance stability fin FET mention still needs to be formed.

[0042] 经过研宄,发明人发现,随着工艺节点的进一步减小,相邻两个鳍部之间的距离进一步减小,在形成栅极结构后,形成包裹所述鳍部的外延层时,相邻两个鳍部的外延层间的距离难以控制,形成的所述相邻两个鳍部的外延层极易接触,影响了后续工艺,并严重影响了鳍式场效应管的性能。 [0042] After a Subsidiary, the inventors have found that, with the further reduction process nodes, between two adjacent fins of the distance is further reduced, after forming the gate structure, forming an epitaxial layer of the wrapped fin portion when the distance between two adjacent fins epitaxial layer is difficult to control the epitaxial layer in contact with two easy fin forming portion of the adjacent affects subsequent processes, and seriously affect the performance of the fin FET .

[0043] 更进一步的,发明人发现,在形成包裹所述鳍部的外延层前,如果在鳍部侧壁形成伪侧墙,在所述伪侧墙的保护下,外延层仅形成在未被伪侧墙覆盖的鳍部表面,后续形成的外延层的体积较小,并且相邻两个鳍部表面的外延层不易接触,不会影响后续工艺的进行,且形成的鳍式场效应管的性能好。 [0043] Further, the inventors found that, prior to forming an epitaxial layer of the wrapped fin portion, if the dummy spacers are formed in the fin side wall portion, the dummy spacers under the protection of the epitaxial layer is formed not only in the fin FET fin surface portion is covered with the dummy spacers, smaller subsequently formed epitaxial layer, the epitaxial layer and adjacent surfaces of the two portions of the fin inaccessibility, it does not affect the subsequent processes is performed, and formed good performance.

[0044] 为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。 [0044] For the above-described objects, features and advantages of the present invention can be more fully understood by reading the following description of the drawings in detail specific embodiments of the present invention binds.

[0045] 请参考图2,本发明实施例的鳍式场效应管的形成方法,包括: [0045] Please refer to FIG 2, a method of forming a fin field effect transistor embodiment of the present invention, comprising:

[0046] 步骤S201,提供半导体衬底,所述半导体衬底表面形成有隔离层; [0046] step S201, the providing a semiconductor substrate, the semiconductor substrate is formed with a surface of the isolation layer;

[0047] 步骤S203,形成贯穿所述隔离层、且一端位于半导体衬底内的鳍部,所述鳍部表面高于隔离层表面; [0047] Step S203, the spacer is formed through the layer, and an end portion of the fin in the semiconductor substrate, the fin surface is higher than the surface of the insulating layer;

[0048] 步骤S205,形成位于所述隔离层表面、且横跨所述鳍部的顶部和侧壁的栅极结构; [0048] step S205, the surface is formed in said spacer layer, and a gate structure across the top and sidewalls of the fin portion;

[0049] 步骤S207,形成位于所述栅极结构侧壁和鳍部侧壁的伪侧墙; [0049] Step S207, the sidewalls of the gate structure formed in said fin portion and the dummy sidewall spacers;

[0050] 步骤S209,形成位于所述伪侧墙表面、且包裹所述鳍部的外延层; [0050] step S209, the dummy spacers are formed in said surface of said epitaxial layer and wrapping the fin portion;

[0051] 步骤S211,在形成所述外延层后去除所述伪侧墙。 [0051] step S211, the dummy removing the spacers after forming the epitaxial layer.

[0052] 具体的,请参考图3-图15,其中,图3、4、6_15是本发明的实施例的鳍式场效应管的形成过程的剖面结构示意图;图5是图4的俯视结构示意图。 [0052] Specifically, please refer to FIGS. 3 to 15, wherein a cross-sectional schematic view of FIG. 3,4,6_15 is a process of forming a fin field effect transistor embodiment of the present invention; FIG. 5 is a top view of the structure of FIG. 4 schematic diagram.

[0053] 请参考图3,提供半导体衬底300,所述半导体衬底300表面形成有隔离层301。 [0053] Please refer to FIG. 3, a semiconductor substrate 300, the surface of the semiconductor substrate 300 with an isolation layer 301 is formed.

[0054] 所述半导体衬底300用于作为后续工艺的工作平台。 [0054] The semiconductor substrate 300 is used as a work platform for the subsequent process. 所述半导体衬底300的材料为硅或锗等半导体材料,所述半导体衬底300还可以为绝缘体上硅(SOI)。 The semiconductor material of the substrate 300 is a semiconductor material like silicon or germanium, the semiconductor substrate 300 may also be a silicon on insulator (SOI). 在本发明的实施例中,所述半导体衬底300的材料为娃。 In an embodiment of the present invention, the material of the semiconductor substrate 300 is baby.

[0055] 所述隔离层301用于后续隔离相邻的鳍式场效应管。 [0055] The spacer layer 301 for the subsequent isolation of adjacent fin FET. 所述隔离层301的形成工艺为沉积工艺,例如低压化学气相沉积或等离子体化学气相沉积。 The process of forming the spacer layer 301 is a deposition process, for example a low pressure chemical vapor deposition or plasma chemical vapor deposition. 所述隔离层301的为氧化硅、氮化硅或氮氧化硅。 The spacer layer is a silicon oxide, silicon nitride or silicon oxide 301. 在本发明的实施例中,所述隔离层301在温度大于500°C的环境下,采用低压化学气相沉积形成,形成的隔离层的材料为氧化硅。 In an embodiment of the present invention, the spacer layer 301 at ambient temperatures greater than 500 ° C, using a low pressure chemical vapor deposition, the material of the isolation layer is formed of silicon oxide.

[0056] 请继续参考图3,形成贯穿所述隔离层301、且一端位于半导体衬底300内的鳍部303,所述鳍部303表面高于隔离层301表面。 [0056] Please continue to refer to FIG. 3, is formed through the isolation layer 301, and an end portion of the fin 303 in the semiconductor substrate 300, the surface 303 of the fin 301 is higher than the surface of the spacer layer.

[0057] 所述鳍部303用于后续形成鳍式场效应管。 The [0057] 303 for subsequent forming fin-type fin FET. 所述鳍部303的形成步骤包括:刻蚀所述隔离层301和半导体衬底300,形成贯穿所述隔离层301并延伸至所述半导体衬底300的沟槽(未图示);填充所述沟槽形成鳍部303,所述鳍部303的表面高于隔离层301表面。 The step of forming the fin portion 303 comprises: etching the spacer layer 301 and the semiconductor substrate 300, is formed through the spacer layer 301 and extends into a groove (not shown) of the semiconductor substrate 300; the filling said groove forming a fin portion 303, portion 303 of the fin surface is higher than the surface of the spacer layer 301.

[0058] 所述鳍部303的材料与所述半导体衬底300的材料相同,为硅。 [0058] The fin material of the material 303 and the same semiconductor substrate 300, is silicon. 在本发明的实施例中,所述鳍部303采用选择性沉积工艺形成。 In an embodiment of the present invention, the fin portion 303 is formed using selective deposition process.

[0059] 需要说明的是,在本发明的其他实施例中,所述鳍部303可以由刻蚀半导体衬底300后得到,所述隔离层301在形成鳍部303后采用沉积工艺得到,在此不再赘述。 [0059] Note that, in other embodiments of the present invention, the fin portion 303 may be obtained by a post-etching the semiconductor substrate 300, the deposition process employed to obtain the isolation layer 301 is formed in the fin portion 303, the this will not be repeated.

[0060] 请结合参考图4和图5,图5为图4所示的俯视结构示意图。 [0060] Please refer to FIGS. 4 and in conjunction with FIG. 5, FIG. 5 is a schematic top view of the structure as shown in FIG. 4. 形成位于所述隔离层301表面、且横跨所述鳍部303的顶部和侧壁的栅极结构(未标示)。 Forming in said surface of the spacer layer 301, and gate structure across said fin top and sidewalls 303 (not shown).

[0061] 所述栅极结构包括:位于所述隔离层301表面、且横跨所述鳍部303的顶部和侧壁的栅介质层305 ;覆盖所述栅介质层305表面的栅电极层307 ;位于所述栅电极层307和栅介质层305侧壁的侧墙311。 [0061] The gate structure comprising: a surface of the spacer layer 301, and across the top and side walls of the fin 303 gate dielectric layer 305; layer 307 covering the gate electrode surface of the gate dielectric layer 305 ; layer located on the gate electrode 307 and sidewall spacers 311,305 gate dielectric layer. 其中,所述栅电极层307和栅介质层305构成栅极,所述栅电极层307的材料为多晶硅或金属,所述栅介质层305的材料为氧化物或高K介质,所述侧墙311用于对所述栅极进行保护,防止在后续工艺例如掺杂形成源/漏区时对栅极造成损伤,所述侧墙311的材料为氧化硅、氮化硅或氮氧化硅。 Wherein the gate electrode layer 307 and the gate dielectric layer 305 constituting the gate, the gate electrode material layer 307 is a polysilicon or metal, the material of the gate dielectric layer 305 is an oxide or a high K dielectric, said spacer 311 is used to protect the gate to prevent damage during subsequent process such as doped source / drain regions to the gate, the spacer material 311 is silicon oxide, silicon nitride or silicon oxynitride.

[0062] 在本发明的实施例中,所述栅介质层305的材料为氧化硅,所述栅电极层307的材料为多晶硅,所述侧墙311的材料为氮氧化硅。 [0062] In an embodiment of the present invention, the material of the gate dielectric layer 305 is silicon oxide, the material of the gate electrode polysilicon layer 307, the spacer material 311 is a silicon oxynitride.

[0063] 所述栅极结构的形成步骤包括:形成覆盖所述鳍部303和隔离层301的栅介质薄膜(未图示);形成覆盖所述栅介质薄膜的栅电极薄膜(未图示);形成覆盖所述栅电极薄膜的硬掩膜层309,所述硬掩膜层309定义出栅极的形状、位置和大小;以所述硬掩膜层309为掩膜,刻蚀所述栅电极薄膜和栅介质薄膜,形成栅电极层307和栅介质层305,即形成栅极;形成位于所述栅电极层307和栅介质层305侧壁的侧墙311。 [0063] The step of forming the gate structure comprises: forming a gate dielectric film 303 covering the fin and the spacer layer 301 (not shown); forming a gate dielectric film covering the gate electrode film (not shown) ; forming a hard mask layer covering the gate electrode film 309, the hard mask layer 309 to define the shape, the position and size of the gate; to the hard mask layer 309 as a mask, etching the gate a gate electrode film and the dielectric film, the gate electrode layer 307 and the gate dielectric layer 305 is formed, i.e., forming a gate; gate electrode layer is formed in said gate dielectric layer 307 and sidewall spacers 311,305.

[0064] 由于形成所述栅极结构的工艺已为本领域技术人员所熟知,在此不再赘述。 [0064] Since the process of forming the gate structure are known to those skilled in the art and are not repeated here.

[0065] 需要说明的是,在本发明的实施例中,在形成栅极结构后,形成伪侧墙前,在所述栅极结构两侧的鳍部303内掺杂形成源/漏区(未图示)。 [0065] Incidentally, in the embodiment of the present invention, after forming the gate structure, the dummy spacers are formed before the doped source / drain regions in both sides of the fin portions 303 of the gate structure ( not shown). 掺杂形成源/漏区的工艺已为本领域技术人员所熟知,在此不再赘述。 Forming doped source / drain regions in the process known to those skilled in the art and are not repeated here.

[0066] 请结合参考图6和图7,图6为图5的基础上形成鳍式场效应管时沿A-Al方向的剖面示意图,图7为图5的基础上形成鳍式场效应管时沿B-Bl方向的剖面示意图。 [0066] Please refer to FIGS. 6 and in conjunction with FIG. 7, FIG. 6 is a schematic cross-sectional view along the direction A-Al forming a fin field effect transistor on the basis of FIG. 5, FIG. 5 FIG. 7 is formed based on the fin FET when the direction along B-Bl sectional view. 形成位于所述栅极结构侧壁和鳍部303侧壁的伪侧墙313。 Sidewalls of the gate structure formed in said sidewalls of the fin 303 and spacer portion 313 of the dummy.

[0067] 考虑到现有技术在形成栅极结构后,形成包裹所述鳍部303的外延层时,相邻两个鳍部303的外延层间的距离难以控制,形成的所述相邻两个鳍部303的外延层极易接触,影响了后续工艺,并严重影响了鳍式场效应管的性能。 [0067] Considering the prior art in the formation of the gate structure, forming an epitaxial layer of the wrapped fin portion 303, the distance between the two fin portions 303 of the epitaxial layer adjacent difficult to control the formation of two adjacent a fin portion 303 of the epitaxial layer can easily contact affects the subsequent process, and seriously affect the performance of the fin FET.

[0068] 发明人发现,在形成包裹所述鳍部303的外延层前,如果在鳍部303侧壁形成伪侧墙313,在所述伪侧墙313的保护下,外延层仅形成在未被伪侧墙313覆盖的鳍部303表面,后续形成的外延层的体积较小,并且相邻两个鳍部303表面的外延层不易接触,不会影响后续工艺的进行,且形成的鳍式场效应管的性能好。 [0068] The inventors have found that an epitaxial layer is formed before wrapping the fin portion 303, if the dummy sidewall spacers 313 are formed in the fin portion 303, under the protection of the dummy spacers 313, an epitaxial layer is formed not only in the fin surface portion 303 is covered with the dummy spacers 313, a smaller volume of the epitaxial layer is subsequently formed, an epitaxial layer 303 and adjacent surfaces of the two fin portions inaccessibility, does not affect the subsequent processes is performed, and the formed fin good performance FET.

[0069]因此,在本发明的实施例中,所述伪侧墙313用于在后续工艺中保护栅极结构,并用于作为后续形成外延层时的支撑,使得形成的外延层的体积小,相邻两个鳍部303表面的外延层的距离大,有助于后续工艺的进行。 [0069] Thus, in the embodiment of the present invention, the dummy spacers 313 in a subsequent process for protection of the gate structure, and is used as the support during the subsequent formation of an epitaxial layer, the epitaxial layer is formed so that the volume is small, the surface of the epitaxial layer 303 adjacent two fins large distance, facilitates subsequent processes.

[0070] 所述伪侧墙313的形成步骤包括:形成覆盖所述隔离层301、鳍部303和栅极结构的伪侧墙薄膜(未标示);去除位于所述隔离层301表面、鳍部303顶部的伪侧墙薄膜,而保留位于所述鳍部303部分侧壁和栅极结构表面的伪侧墙薄膜。 Forming step [0070] The dummy spacer 313 comprises: forming the isolation layer 301 covering the dummy spacer film 303 and the gate portion of the fin structure (not shown); removing surface 301 located on the isolation layer, the fin dummy sidewall spacers 303 on top of the film, while retaining the dummy spacer portion 303 located in the film gate structure and sidewall surface of the fin portion.

[0071] 其中,所述伪侧墙薄膜的材料为氧化硅、氮化硅或氮氧化硅。 [0071] wherein the dummy spacer film material is silicon oxide, silicon nitride or silicon oxynitride. 为便于后续去除,所述伪侧墙薄膜的材料与所述栅极结构的侧墙的材料不同。 For ease of subsequent removal, the different pseudo-film sidewall spacer material as the gate structure. 在本发明的实施例中,所述伪侧墙薄膜的材料为氮化硅。 In an embodiment of the present invention, the dummy spacer material is a silicon nitride film. 所述保留的位于所述鳍部303部分侧壁和栅极结构表面的伪侧墙薄膜即为伪侧墙313。 Dummy spacer portion 303 located in the film gate structure and sidewall surface of the fin is the portion of the reserved dummy spacer 313.

[0072] 所述位于鳍部303侧壁的伪侧墙313的高度Ii1与后续形成的外延层的大小相关,会影响到后续工艺窗口的大小,即相邻两个鳍部303的外延层之间的距离的大小。 [0072] The spacer 303 is located in the side wall of the dummy fin height Ii1 313 is related to the size of the epitaxial layer is subsequently formed, the subsequent processes will affect the size of the window, i.e., an epitaxial layer 303 of the adjacent two fins the size of the distance between. 如果所述位于鳍部303侧壁的伪侧墙313的高度Ii1太小,后续形成的外延层大,后续工艺窗口小,甚至会出现相邻两个鳍部303的外延层相接触的情况,严重影响了后续工艺的进行,形成的鳍式场效应管的性能不稳定;如果所述位于鳍部303侧壁的伪侧墙313的高度Ii1太大,例如伪侧墙313与所述鳍部303表面平行,则会导致后续形成的外延层的体积过小,影响鳍式场效应管的沟道区的载流子迀移率,并且后续形成导电插塞时,导电插塞与外延层的接触面积小,也会影响鳍式场效应管的性能。 If the sidewall 303 is located in sidewall 313 of the fin height Ii1 dummy small, the epitaxial layer is subsequently formed large and small windows subsequent processes, even where two adjacent fin portions of the epitaxial layer 303 will be in contact, seriously affecting the subsequent process, unstable fin field-effect transistor is formed; if located in the sidewalls of the fin 303 height of Ii1 dummy spacer portion 313 is too large, for example, the dummy spacer portion 313 and the fin parallel to the surface 303, will cause the subsequent formation of an epitaxial layer of the volume is too small, the influence of carriers fin FET channel region Gan drift rate, and subsequently forming a conductive plug, the conductive plug and the epitaxial layer, the contact area, can also affect the performance of the fin FET.

[0073] 经过仔细研宄,发明人发现,所述位于鳍部303侧壁的伪侧墙313的高度Ill与高于隔离层301表面部分的鳍部303的高度h2比小于等于1: 3时,后续形成的外延层的大小可以较好的控制,后续工艺窗口较大,形成的鳍式场效应管的性能好。 [0073] After careful study based on the inventors found that, the spacer 303 located on the side wall of the dummy fin height Ill 313 and higher than the height h2 of the spacer layer 301 fin surface portion 303 is less than or equal to 1: 3 , the size of the epitaxial layer subsequently formed can be well controlled, the larger the subsequent process window, good performance of the fin FET formed. 更进一步的,发明人发现,当所述位于鳍部303侧壁的伪侧墙313的高度Ii1与高于隔离层301表面部分的鳍部303的高度h2比小于等于1: 3,大于等于1: 5时,既可以在后续工艺中较好的控制外延层的大小,增大工艺窗口,又可以使后续形成的导电插塞与外延层的接触面积增大,更进一步的提高了鳍式场效应管的性能。 Still further, the inventors found that, when the height h2 of the portion of the sidewalls of the fin 303 is located in the dummy sidewalls of the fin height Ii1 313 above the portion 301 of the surface portion of the spacer layer 303 is less than or equal to 1: 3, greater than or equal to 1 : 5, preferably both in a subsequent process to control the size of the epitaxial layer, increasing the process window, and can subsequently formed conductive plug and the plug contact area of ​​the epitaxial layer is increased, further improving the fin field effect of tube performance.

[0074] 在本发明的实施例中,所述位于鳍部303侧壁的伪侧墙313的高度匕为10_30nm,位于鳍部303侧壁的伪侧墙313的厚度(图6中与高度垂直方向的尺寸)为3-10nm,形成的鳍式场效应管的性能优越。 [0074] In an embodiment of the present invention, the dummy sidewall spacers 303 located in the side wall portion of the height of the fin 313 is dagger 10_30nm, the thickness of the sidewalls of the fin 303 is located in the dummy spacer portion 313 (FIG. 6 and the height of the vertical direction dimension) of 3-10nm, superior performance fin-FET is formed.

[0075] 请结合参考图8和图9,图8为图6基础上形成鳍式场效应管时的剖面结构示意图,图9为图7基础上形成鳍式场效应管时的剖面结构示意图。 [0075] Please refer to FIGS. 8 and in conjunction with FIG. 9, FIG. 8 a schematic cross-sectional structure when forming a fin field effect transistor 6 is on the basis of FIG, 9 is a schematic cross-sectional structure of FIG when forming a fin field effect transistor 7 is on the basis of FIG. 形成位于所述伪侧墙313表面、且包裹所述鳍部303的外延层315。 Forming in said surface of the dummy spacers 313, epitaxial layer 315 and the wrap 303 of the fin portion.

[0076] 所述外延层315用于在鳍式场效应管的沟道区引入拉应力或压应力,从而提高其沟道区的载流子迀移率,提高鳍式场效应管的性能。 [0076] The epitaxial layer 315 for introducing tensile or compressive stress in the channel region of the fin FET, thereby improving the carrier whose channel region Gan drift rate, to improve the performance of the fin FET. 所述外延层315的形成工艺为选择性外延沉积工艺。 The process of forming a selective epitaxial layer 315 is an epitaxial deposition process. 由于各个晶向方向上生长速率存在不同,采用选择性沉积工艺形成的外延层315为如图8、9所示的六面体形。 Due to the presence of the growth rate in the direction of different respective crystal, using hexahedral epitaxial layer 315 shown in FIG. 8 and 9 formed by a selective deposition process is shown in FIG.

[0077] 所述外延层315的材料与待形成的鳍式场效应管的类型有关,当待形成的鳍式场效应管为P型时,所述外延层315的材料为SiGe ;当待形成的鳍式场效应管为η型时,所述外延层315的材料为SiC、SiN或SiP。 [0077] The epitaxial layer 315 with a material type fin FET to be formed, and when the fin field effect tube is formed to be P-type, said epitaxial layer material 315 of the SiGe; be formed when when η is the fin-type field effect transistor, the epitaxial layer material 315 is SiC, SiN or SiP. 在本发明的实施例中,所述外延层的材料为SiGe,形成的鳍式场效应管为P型鳍式场效应管。 In an embodiment of the present invention, the material of the epitaxial layer is SiGe, the fin field effect tube is formed a P-type fin FET.

[0078] 请参考图10-图11,图10为图8基础上形成鳍式场效应管时的剖面结构示意图,图11为图9基础上形成鳍式场效应管时的剖面结构示意图。 [0078] Please refer to FIG. 10 to FIG 11, FIG 10 is a schematic cross-sectional structure when forming a fin field effect transistor 8 is on the basis of FIG. FIG. 11 is a schematic cross-sectional configuration when the fin FET 9 is formed on the basis of FIG. 在形成所述外延层315后去除所述伪侧墙。 After forming the epitaxial layer 315 removing the dummy spacer.

[0079] 去除所述伪侧墙,以便于后续工艺的进行。 [0079] removing the dummy spacers, for the subsequent process. 去除所述伪侧墙的工艺为刻蚀工艺,例如干法刻蚀或湿法刻蚀,在此不再赘述。 Removing the dummy spacers process is an etching process such as dry etching or wet etching, which is not repeated herein.

[0080] 请结合参考图12和图13,图12为图10基础上形成鳍式场效应管时的剖面结构示意图,图13为图11基础上形成鳍式场效应管时的剖面结构示意图。 [0080] Please refer to FIGS. 12 and in conjunction with FIG. 13, FIG. 12 is a schematic cross-sectional structure when forming a fin field effect transistor on the basis of FIG. 10, FIG. 13 is a schematic cross-sectional structure when forming a fin field effect transistor 11 on the basis of FIG. 形成覆盖所述外延层315、隔离层301以及栅极结构的可流动绝缘层317。 Covering the epitaxial layer 315, spacer layer 301 and a flowable insulating layer gate structure 317.

[0081] 所述可流动绝缘层317用于后续形成性能更加稳定的鳍式场效应管。 [0081] The insulating layer 317 may be used in the subsequent flow forming more stable fin FET. 所述可流动绝缘层317的材料为氧化硅或氮化硅。 The flowable material of the insulating layer 317 is silicon oxide or silicon nitride. 所述可流动绝缘层317的形成步骤包括:形成覆盖所述外延层315、隔离层301以及栅极结构的可流动薄膜(未图示);对所述可流动薄膜进行氧化或氮化处理,形成可流动绝缘层317。 The step of forming the flowable insulating layer 317 includes: the epitaxial layer 315 is formed to cover the isolation layer 301 and a flowable film gate structure (not shown); a flowable film of oxidation or nitriding treatment, a flowable insulating layer 317 is formed.

[0082] 其中,所述可流动薄膜的材料为硼磷硅玻璃、硼硅玻璃、磷硅玻璃、聚乙烯氧化硅、聚乙烯氮化硅或正硅酸乙酯。 [0082] wherein the flowable material is a film borophosphosilicate glass, borosilicate glass, phosphosilicate glass, silicon oxide, polyethylene, polyethylene, silicon nitride, or TEOS. 对所述可流动薄膜进行氧化处理采用的气体为氧气或臭氧。 The film of the gas flow may be used in the oxidation treatment is an oxygen or ozone. 在本发明的实施例中,所述可流动薄膜的材料为正硅酸乙酯,对所述可流动薄膜进行氧化处理采用的气体为臭氧,形成的可流动绝缘层317的材料为氧化硅。 In an embodiment of the invention, the flowable material is a thin TEOS, the film is flowable gas used is ozone oxidation treatment, a flowable insulating material layer 317 is formed of silicon oxide.

[0083] 需要说明的是,由于形成的可流动绝缘层317覆盖所述外延层315、隔离层301以及栅极结构的可流动绝缘层317,而真正对后续形成的鳍式场效应管的性能有贡献的部分为位于所述隔离层301表面的部分可流动绝缘层317。 [0083] Incidentally, since the flow of the insulating layer 317 is formed overlying the epitaxial layer 315, spacer layer 301 and a flowable insulating layer of the gate structure 317, while the real performance of the fin FET subsequently formed contributing part 301 is positioned in the surface portion of the spacer layer of flowable insulating layer 317. 因此,在本发明的实施例中,请结合参考图14和图15,图14为图12基础上形成鳍式场效应管时的剖面结构示意图,图15为图13基础上形成鳍式场效应管时的剖面结构示意图。 Thus, in the embodiment of the present invention, please refer to FIGS. 14 and in conjunction with FIG. 15, FIG. 14 a schematic cross-sectional structure when forming a fin field effect transistor on the basis of FIG. 12, FIG. 15 is a FinFET formed on the basis of FIG. 13 a schematic cross-sectional configuration of the tube when. 还包括:对所述可流动绝缘层317进行回流处理,使位于所述外延层315和栅极结构表面的部分可流动绝缘层317回流至相邻两个鳍部303间的隔离层301表面,使得形成的相邻两个鳍式场效应管的绝缘效果更好。 Further comprising: the reflow treatment the flowable insulating layer 317, so that part 315 and a gate structure positioned in the surface of epitaxial layer 317 of a flowable insulating layer 301 under reflux for surface barrier 303 to the two adjacent fins, so that the insulation effect two adjacent fin field effect transistor formed better.

[0084] 需要说明的是,在本发明的其他实施例中,为使得鳍式场效应管的沟道区应力更大,还包括:形成覆盖所述外延层315、隔离层301以及栅极结构的应力层(未图示)。 [0084] Note that, in other embodiments of the present invention, such as the channel region of the fin FET greater stress, further comprising: forming an epitaxial layer 315 overlying the isolation layer 301 and a gate structure stress layer (not shown). 所述应力层的材料与所述外延层315的材料相同,为SiGe、SiC、SiN或SiP,用于进一步增大鳍式场效应管的沟道区应力,提高其沟道区的载流子迀移率,提高鳍式场效应管的性能。 The epitaxial layer of the same material and the material layer 315 of stress, as SiGe, SiC, SiN, or a SiP, for further increasing the stress in the channel region of the fin FET, improving carrier whose channel region Gan drift rate, to improve the performance of the fin FET.

[0085] 所述应力层的形成工艺为原子层沉积工艺、化学气相沉积工艺、低压化学气相沉积工艺或等离子体化学气相沉积工艺。 [0085] The process of forming the stress layer is an atomic layer deposition process, a chemical vapor deposition process, a low pressure chemical vapor deposition process or a plasma chemical vapor deposition process. 由于采用上述方法形成应力层工艺的工艺已为本领域技术人员所熟知,在此不再赘述。 Since the method of forming the above-described process stress layer process known to those skilled in the art and are not repeated here.

[0086] 需要说明的是,在本发明的其他实施例中,所述应力层还可以形成在回流处理过的可流动绝缘层317上,不仅增加了鳍式场效应管的沟道区的载流子迀移率,提高了鳍式场效应管的性能,还使得相邻两个鳍式场效应管的绝缘效果好。 [0086] Note that, in other embodiments of the present invention, the stress layer may be formed on the treated reflux flowable insulating layer 317, the channel region of the carrier not only increases the fin FET Gan carrier drift rate, to improve the performance of a fin field-effect transistor, so that further two adjacent fin-FET good insulating effect.

[0087] 上述步骤完成后,本发明实施例的鳍式场效应管的制作完成。 [0087] After the above steps are completed, of fabricating a fin field effect transistor embodiment of the present invention is completed.

[0088] 综上,本发明的实施例中,在鳍部侧壁形成伪侧墙,在所述伪侧墙的保护下,外延层仅形成在未被伪侧墙覆盖的鳍部表面,后续形成的外延层的体积较小,并且相邻两个鳍部表面的外延层不易接触,不会影响后续工艺的进行,且形成的鳍式场效应管的性能好。 [0088] In summary, embodiments of the present invention, the dummy spacers are formed in the fin side wall portion, the dummy spacers under the protection of the epitaxial layer is formed only on the surface of the fin portion is not covered by the dummy spacers, subsequent forming an epitaxial layer volume is small, the epitaxial layer and adjacent surfaces of the two portions of the fin inaccessibility, does not affect the subsequent processes is performed, performance of the fin and forming a field effect transistor.

[0089] 进一步的,还包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动绝缘层。 [0089] Further, further comprising: forming a flowable insulating layer covering the epitaxial layer, an isolation layer and a gate structure. 之后,还对所述可流动绝缘层进行回流处理,使位于所述外延层和栅极结构表面的部分可流动绝缘层回流至相邻两个鳍部间的隔离层表面,提高了相邻两个鳍式场效应管之间的绝缘效果。 After the further insulating layer of the flowable reflow process, so that an epitaxial layer and the gate structure of the surface portion of the flowable insulating layer between the surface barrier at reflux for two adjacent fins to improve the two adjacent an insulating effect between the fin FET.

[0090] 更进一步的,还包括:形成覆盖所述外延层、隔离层以及栅极结构的应力层。 [0090] Still further, further comprising: forming an epitaxial layer overlying the isolation layer, and a stress layer gate structure. 所述应力层与所述外延层共同包裹所述鳍部表面,进一步提高了鳍式场效应管的沟道区的应力,使其沟道区的载流子迀移率增加,鳍式场效应管的性能好。 The stress layer and wrapping the joint surface of the fin portion of the epitaxial layer, to further improve the stress in the channel region of the fin field-effect transistor, so that carriers in the channel region increases Gan drift rate, fin field effect good performance of the tube.

[0091] 本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。 [0091] While the invention has been disclosed in the above preferred embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the methods and techniques within the spirit and scope of the invention are disclosed above may be utilized SUMMARY made to the technical solution of the present invention is possible variations and modifications, therefore, all without departing from the technical solutions of the present invention, the basis of any simple modification techniques essence of the invention of the above embodiments taken embodiments, equivalents, changes and modifications belong to the present invention scope of the technical solutions.

Claims (19)

1.一种鳍式场效应管的形成方法,其特征在于,包括: 提供半导体衬底,所述半导体衬底表面形成有隔离层; 形成贯穿所述隔离层、且一端位于半导体衬底内的鳍部,所述鳍部表面高于隔离层表面; 形成位于所述隔离层表面、且横跨所述鳍部的顶部和侧壁的栅极结构; 形成位于所述栅极结构侧壁和鳍部侧壁的伪侧墙,所述位于鳍部侧壁的伪侧墙的高度与高于隔离层表面部分的鳍部的高度比小于等于1:3 ; 形成位于所述伪侧墙表面、且包裹所述鳍部的外延层; 在形成所述外延层后去除所述伪侧墙。 1. A method of forming a fin field effect transistor, characterized by comprising: providing a semiconductor substrate, the semiconductor substrate is formed with a surface of the isolation layer; formed through the isolation layer and having an end positioned within the semiconductor substrate fin, fin surface is higher than the surface of the isolation layer; forming a spacer layer located on the surface and across the top and sidewalls of the gate structure of the fin portion; sidewall gate structure formed in said fins and sidewall spacers dummy portion, the sidewall portion located in the dummy spacer fin height higher than the surface height of the fin portions of the isolation layer is less than 1: 3; dummy spacers are formed in said surface, and an epitaxial layer of the wrap fin portion; removing the dummy spacers after forming the epitaxial layer.
2.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述伪侧墙的形成步骤包括:形成覆盖所述隔离层、鳍部和栅极结构的伪侧墙薄膜;去除位于所述隔离层表面、鳍部顶部的伪侧墙薄膜。 2. The method of forming a fin field effect transistor according to claim 1, wherein said step of forming dummy spacers comprises: forming said thin film covering the dummy sidewall spacer layer, the fin structure and the gate ; removing the spacer film surface of the dummy, the top portion of the isolation layer fin.
3.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述伪侧墙的材料为氧化硅、氮化硅或氮氧化硅。 The method of forming a fin field effect transistor according to claim 1, wherein said dummy spacers material is silicon oxide, silicon nitride or silicon oxynitride.
4.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述位于鳍部侧壁的伪侧墙的高度与高于隔离层表面部分的鳍部的高度比大于等于1:5。 4. A method of forming a fin field effect transistor according to claim 1, characterized in that, at the height of the dummy sidewall spacers fin portion higher than the height of the fin portion and a surface portion of the spacer layer is greater than equal to 1: 5.
5.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述位于鳍部侧壁的伪侧墙的高度为10-30nm。 5. A method of forming a fin field effect transistor according to claim 1, characterized in that, at the height of the dummy sidewall spacers fin portion is 10-30nm.
6.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述位于鳍部侧壁的伪侧墙的厚度为3-10nm。 The method of forming the fin FET as claimed in claim 1, wherein said dummy spacers positioned thickness sidewall portion of the fin is 3-10nm.
7.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述外延层的材料为SiGe、SiC、SiN 或SiP。 7. The method of forming a fin field effect transistor according to claim 1, characterized in that the material of the epitaxial layer is SiGe, SiC, SiN or SiP.
8.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述外延层的形成工艺为选择性外延沉积工艺。 8. A method of forming a fin field effect transistor according to claim 1, wherein the process of forming the epitaxial layer is selectively epitaxial deposition process.
9.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,还包括:在形成伪侧墙前,在所述栅极结构两侧的鳍部内掺杂形成源/漏区。 The method of forming a fin field effect transistor as claimed in claim 1, characterized in that, further comprising: prior to forming the dummy spacers, the doped portion of the fin on both sides of the gate structure to form a source / drain region .
10.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,还包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动绝缘层。 10. A method of forming a fin field effect transistor according to claim 1, characterized in that, further comprising: forming a flowable insulating layer covering the epitaxial layer, an isolation layer and a gate structure.
11.如权利要求10所述的鳍式场效应管的形成方法,其特征在于,所述可流动绝缘层的材料为氧化硅或氮化硅。 The method of forming the fin 11. The FET of claim 10, wherein the flowable material of the insulating layer is silicon oxide or silicon nitride.
12.如权利要求10所述的鳍式场效应管的形成方法,其特征在于,还包括:对所述可流动绝缘层进行回流处理,使位于所述外延层和栅极结构表面的部分可流动绝缘层回流至相邻两个鳍部间的隔离层表面。 The method of forming a fin field effect transistor of claim 10 to claim 12, characterized in that, further comprising: said insulating layer flow reflow process, so that an epitaxial layer and the gate structure of the surface portion may be reflux flow to the surface of the insulating layer between the two fin portions adjacent the isolation layer.
13.如权利要求10所述的鳍式场效应管的形成方法,其特征在于,所述可流动绝缘层的形成步骤包括:形成覆盖所述外延层、隔离层以及栅极结构的可流动薄膜;对所述可流动薄膜进行氧化或氮化处理。 The method of forming a fin-type field effect transistor 13. As described in claim 10, wherein the step of forming the flowable insulating layer comprises: forming an epitaxial layer overlying the isolation layer, and a flowable film of the gate structure ; flowable film of the oxidizing or nitriding treatment.
14.如权利要求13所述的鳍式场效应管的形成方法,其特征在于,所述可流动薄膜的材料为硼磷硅玻璃、硼硅玻璃、磷硅玻璃、聚乙烯氧化硅、聚乙烯氮化硅或正硅酸乙酯。 The method of forming a fin field effect transistor as claimed in claim 13, wherein the flowable material is a film borophosphosilicate glass, borosilicate glass, phosphosilicate glass, silicon oxide, polyethylene, polyvinyl silicon nitride or TEOS.
15.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,还包括:形成覆盖所述外延层、隔离层以及栅极结构的应力层。 15. A method of forming a fin field effect transistor according to claim 1, characterized in that, further comprising: forming an epitaxial layer overlying the isolation layer, and a stress layer gate structure.
16.如权利要求15所述的鳍式场效应管的形成方法,其特征在于,所述应力层的材料与所述外延层的材料相同,为SiGe、SiC、SiN或SiP。 The method of forming the fin 16. The FET of claim 15, wherein the material of the stressed layer and the material of the epitaxial layer is the same as SiGe, SiC, SiN or SiP.
17.如权利要求15所述的鳍式场效应管的形成方法,其特征在于,所述应力层的形成工艺为原子层沉积工艺、低压化学气相沉积工艺或等离子体化学气相沉积工艺。 The method of forming the fin 17. The FET of claim 15, wherein the process of forming the stress layer atomic layer deposition process, a low pressure chemical vapor deposition process or a plasma chemical vapor deposition process.
18.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述隔离层的材料为氧化硅、氮化硅或氮氧化硅。 18. The method of forming a fin field effect transistor according to claim 1, characterized in that the material of the isolating layer of silicon oxide, silicon nitride or silicon oxynitride.
19.如权利要求1所述的鳍式场效应管的形成方法,其特征在于,所述栅极结构的形成步骤包括:形成覆盖所述鳍部和隔离层的栅介质薄膜;形成覆盖所述栅介质薄膜的栅电极薄膜;形成覆盖所述栅电极薄膜的硬掩膜层,所述硬掩膜层定义出栅极的形状、位置和大小;以所述硬掩膜层为掩膜,刻蚀所述栅电极薄膜和栅介质薄膜,形成栅极;形成位于所述栅极侧壁的侧墙。 19. The method of forming a fin field effect transistor according to claim 1, wherein the step of forming the gate structure comprises: forming the fin portion covering layer and the isolation gate dielectric thin film; forming a cover the gate electrode gate dielectric thin film; forming a hard mask layer covering the gate electrode film, the hard mask layer defines the shape of the gate electrode, the location and size; to the hard mask layer as a mask, carved etching the gate electrode film and the gate dielectric film, forming a gate; gate electrode is formed in said sidewall spacer.
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