CN103338174A - Generation device of data clock of responder - Google Patents

Generation device of data clock of responder Download PDF

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CN103338174A
CN103338174A CN 201310257643 CN201310257643A CN103338174A CN 103338174 A CN103338174 A CN 103338174A CN 201310257643 CN201310257643 CN 201310257643 CN 201310257643 A CN201310257643 A CN 201310257643A CN 103338174 A CN103338174 A CN 103338174A
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clock
counting
responder
data
module
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CN103338174B (en )
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刘晓鹏
吴中宁
韩雁
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浙江大学
北京交大微联科技有限公司杭州分公司
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Abstract

The invention discloses a generation device of a data clock of a responder. The generation device comprises an FPGA (field programmable gate array), wherein the FPGA is loaded with a judgment module, a frequency division counting module and a clock output module. According to the generation device, a binary FSK (frequency shift keying) signal is taken as a counting clock of the frequency division counting module, the counting range of the frequency division counting module is dynamically adjusted in combination with message data of the responder, and the stable data clock of 564 KHz can be extracted from the FSK signal to read the message data of the responder in a memory. Therefore, the power consumption of the whole responder can be reduced while the hardware cost is lowered.

Description

一种应答器数据时钟的发生装置 Transponder data generating means of the clock

技术领域 FIELD

[0001] 本发明属于铁路系统控制技术领域,具体涉及一种应答器数据时钟的发生装置。 [0001] The present invention belongs to the technical field of railway control system, particularly relates to an apparatus for the occurrence of the transponder data clock. 背景技术 Background technique

[0002] 中国列车控制系统(Chinese Train Control System,CTCS)标准是参考欧洲列车控制系统(European Train Control System, ETCS)制定的,在这个标准中,铁路应答器作为列车运行控制系统的关键部分,使得列车控制系统的自动化程度进一步提高。 [0002] Chinese Train Control System (Chinese Train Control System, CTCS) standard reference ETCS (European Train Control System, ETCS) to develop, in this standard, the railway transponder as train operation control of key parts of the system, It makes the train control system to further improve the degree of automation. 铁路应答器在列车监控装置中的作用有:可实现列车的绝对高精度定位(精度可达+1米),无需人工干预,使人为失误导致的安全事故减到最小;可向列车发送线路纵断面数据,桥梁隧道位置信息,线路限速信息,甚至临时限速信息;也可将轨旁电子单元的信息快速传递给列车等。 Railway transponder in the train control device acts: the train can achieve absolute precision positioning (accuracy up to +1 m), without human intervention, makes mistakes lead to accidents is minimized; vertical line can be sent to train section data, bridges, tunnels position information, speed limit information line, even temporary speed restriction information; information may also be an electronic unit side track quickly transmitted to the trains.

[0003] 应答器的工作原理为:当列车到达地面应答器有效工作范围时,通过安装于列车底部的频率为27.095MHz车载功率天线来激活应答器,应答器开始向列车提供行车信息。 [0003] The transponder works as follows: When the train reaches the ground transponder the valid operating range of the vehicle-mounted power 27.095MHz to activate the transponder antenna installed at the bottom by the frequency of the train, the transponder begins to provide traffic information to the train. 这些信息称之为应答器报文,通过FSK (Frequency-shift keying,频移键控)调制后发送出去;由此可见应答器报文的正确可靠直接决定着列车的行车安全,而应答器数据时钟频率的正确与否直接决定了应答器报文能否被正确发送。 This information is called a transponder message, by FSK (Frequency-shift keying, frequency shift keying) modulated transmitted; Thus transponder reliably accurate packet directly determines the traffic safety of the train, the transponder data clock frequency is correct or not directly determine whether the transponder message is sent correctly.

[0004] 这种铁路应答器技术长期被国外信号公司(比如西门子,阿尔斯通等)垄断,从而造成应答器价格昂贵。 [0004] This technique long railway transponder signal by foreign companies (such as Siemens, Alstom, etc.) monopoly, resulting transponder expensive. 随着我国铁路建设的飞速发展,急需具有中国知识产权的铁路应答器。 With the rapid development of China's railway construction, railway urgently needed transponder with Chinese intellectual property rights. 一般建设一条线路所需车载设备和应答器就要花费数千万人民币,自主研发的应答器在为我国节省大量外汇的同时,可以更好的为我国铁路事业的发展做贡献。 General construction of a circuit board equipment and the required transponder will have to spend tens of millions of yuan, independent research and development of transponders at the same time save a lot of foreign exchange for our country, better for the development of China's railway industry to make contributions.

[0005] 在应答器国家标准(CTCS)中,明确规定了应答器所采用的FSK信号的两个频率为:4.512MHz和3.948MHz,而报文的数据率为564kbps。 [0005] In the national standard transponder (the CTCS), clearly defines the two frequencies of the FSK signal the transponder used is: 4.512MHz and 3.948MHz, and the message data rate is 564kbps. 由于应答器通过电磁耦合得到的能量非常有限,整个应答器的功耗就非常严格。 Since the transponder by electromagnetic coupling energy obtained is very limited, the overall power consumption of the transponder is very strict. 目前关于数据时钟的产生主要有两种方法:第一种是通过高频率晶振分频来产生564KHZ的时钟,但是晶振消耗比较多的能量,这也成为该技术最大的缺点。 There are currently about a data clock generating two ways: The first is to generate the frequency-divided clock 564KHZ by a high frequency oscillator, the crystal but more energy consumption, which has become the biggest drawback of the technology.

[0006] 公开号为CN101364816的中国专利公开了另一种应答器技术,其通过功率天线上的27.095MHz的信号进行48分频得到564KHz的数据时钟;该技术不需要额外的晶振,大大节省了功耗,但是毕竟要进行48分频,硬件开销和功耗还是比较大。 [0006] Chinese Patent Publication No. CN101364816 discloses another transponder technology, which was divided by 48 27.095MHz signal power to the antenna on the data clock obtained by frequency of 564KHz; the technique does not require additional crystal, saves power, after all, but to be 48 points frequency, hardware costs and power consumption is quite large.

发明内容 SUMMARY

[0007] 针对现有技术所存在的上述技术问题,本发明提供了一种应答器数据时钟的发生装置,能够在减小硬件开销的同时也能降低整个应答器的功耗。 [0007] For the above-described problems of the prior art technique exists, the present invention provides a device for the transponder occurs the data clock, also possible to reduce the power consumption of the transponder while reducing hardware overhead.

[0008] 一种应答器数据时钟的发生装置,包括FPGA (现场可编程门阵列),所述的FPGA加载有判决模块、分频计数模块和时钟输出模块;其中: [0008] The data clock generating means is a transponder, comprising an FPGA (field programmable gate array), an FPGA loaded with the decision module, and a module clock divider count output module; wherein:

[0009] 所述的判决模块用于接收应答器的报文数据,根据所述的报文数据生成分频计数模块的计数范围; Decision module [0009] The transponder for receiving message data, the message data in accordance with the green component Count frequency range of the module;

[0010] 所述的分频计数模块用于以FSK信号作为计数时钟,在所述的计数范围内进行计数; [0010] The frequency dividing means for counting as a count clock to the FSK signal, counts the count range;

[0011] 所述的时钟输出模块用于将分频计数模块输出计数结果的最高位作为应答器数据时钟并输出。 The most significant bit [0011] The clock output means for frequency dividing the output count counting module as a result of the transponder data and clock outputs.

[0012] 所述的判决模块根据报文数据生成分频计数模块的计数范围的过程如下: [0012] The decision module according to the packet data generation frequency component Count range module is as follows:

[0013]当分频计数模块以FSK信号上升沿或下降沿作为计数时钟的前提下,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜6 ;若判决模块接收到的报文数据为0,则判决模块输出的计数范围为O〜7 ; [0013] When the premise prescaler counting module as FSK signal rising or falling edge of the count clock, if decision block received message data is 1, the decision module output count range is O~6; if decision block the received message data is 0, the decision module output count range is O~7;

[0014] 当分频计数模块以FSK信号上升沿和下降沿共同作为计数时钟的前提下,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜13 ;若判决模块接收到的报文数据为0,则判决模块输出的计数范围为O〜15。 [0014] When the frequency dividing counter module FSK signal rising and falling edges of the clock count together as the premise, if the decision block of the received message data is 1, the decision module output count range is O~13; if decision module receives the message data is 0, the decision module output count range is O~15.

[0015] 所述的判决模块接收分频计数模块输出的计数结果,若计数结果达到计数范围的最大值,则将所述的计数结果清零后使分频计数模块重新计数。 Decision module [0015] division according to the reception module outputs the counting result of the counting, if the counting result reaches the maximum count range, then clearing the count result so that the prescaler counting module counts again.

[0016] 所述的分频计数模块采用3位计数器或4位计数器;若以FSK信号上升沿或下降沿作为计数时钟,则分频计数模块采用3位计数器;若以FSK信号上升沿和下降沿共同作为计数时钟,则分频计数模块采用4位计数器。 [0016] The frequency dividing counter counting module uses three or four counter; In terms of rising or falling FSK signal as the count clock, the frequency dividing counter 3 counting modules; In terms of the rising and falling signal FSK along common as the count clock, the frequency division counter 4 counts modules.

[0017] 本发明分析应答器相关标准中规定的FSK信号频率(4.512MHz或3.948MHz)和数据速率(564kbps,对应的读数据时钟为564KHz)发现,FSK信号频率约是数据速率的7倍(3.948MHz/564KHz )或8倍(4.512MHz/564KHz )。 [0017] FSK signal frequency (4.512MHz or 3.948MHz) predetermined transponder of the present invention analyzed the relevant standards and data rate (564kbps, the data corresponding to the read clock is 564KHz) found, FSK signal frequency is approximately 7 times the data rate ( 3.948MHz / 564KHz) or eight times (4.512MHz / 564KHz). 用FSK信号作为分频计数模块的计数时钟,通过结合应答器报文数据来动态的产生分频计数器的计数范围来实现动态的分频,即可从FSK信号中提取出稳定的564KHz的数据时钟,以此来读取存储器中的应答器报文数据。 FSK signal with a frequency-divided clock count counting module to achieve dynamic frequency division by binding to dynamically generate a frequency division count of the counter range of the transponder data message, the FSK signal can be extracted from the stable data clock of 564KHz , in order to read the transponder message data in the memory.

[0018] 本发明是以较低频率的FSK信号作为分频计数器的计数时钟,所以本发明最多仅需要进行16分频(需要4位分频计数器)即可得到满足应答器相关标准要求的564KHZ数据时钟。 [0018] The present invention is based on the FSK signal a lower frequency as the division count of the counter clock, the present invention need only be up to 16 frequency division (division requires four counters) relevant to the transponder met standards of 564KHZ data clock. 相对于通过功率天线上的27.095MHz的信号进行48分频(需要6位分频计数器)得到564KHZ的数据时钟的方法,本发明的数据时钟发生装置在减小硬件开销的同时也能降低整个应答器的功耗。 48 with respect to the overall response for division (division requires 6 counter) method for data obtained by the signal 564KHZ 27.095MHz clock on the power to the antenna, a data clock generating apparatus according to the present invention can be reduced while reducing hardware overhead power's.

附图说明 BRIEF DESCRIPTION

[0019] 图1为本发明发生装置的结构示意图。 [0019] Fig 1 a schematic view of the structure generating device of the present invention.

[0020] 图2为以二进制FSK信号上升沿为分频计数模块技术时钟时,在仿真软件Modelsim下的仿真结果。 [0020] FIG. 2 is a binary FSK signal to a rising edge of the count divided clock module technology, simulation results in the simulation software Modelsim frequency.

[0021] 图3为以二进制FSK信号下降沿为分频计数模块技术时钟时,在仿真软件Modelsim下的仿真结果。 When [0021] FIG. 3 is a falling edge in the binary FSK signal is frequency-divided clock counting module technology, simulation results of the simulation software Modelsim.

[0022] 图4为同时以二进制FSK信号上升沿和下降沿为分频计数模块技术时钟时,在仿真软件Modelsim下的仿真结果。 [0022] FIG. 4 is a binary FSK signal simultaneously rising and falling edges of the time-frequency division clock counting module technology, simulation results of the simulation software Modelsim.

具体实施方式 detailed description

[0023] 为了更为具体地描述本发明,下面结合附图及具体实施方式对本发明的技术方案及其相关原理进行详细说明。 [0023] To more particularly describe the present invention, the following technical solution of the present invention and related principles described in detail accompanying drawings and specific embodiments.

[0024] 如图1所示,一种应答器数据时钟的发生装置,包括FPGA,FPGA加载有判决模块、分频计数模块和时钟输出模块;判决模块、分频计数模块和时钟输出模块均通过在FPGA平台下通过程序代码编程实现;其中: [0024] 1, the data generating apparatus Transponder clock, including FPGA, FPGA loaded decision module, and a module clock divider count output module; determining module, and a module clock divider count output modules via implemented in program code programmed FPGA platform; wherein:

[0025] 判决模块用于从外部存储器中读取接收应答器的报文数据,根据报文数据生成分频计数模块的计数范围;具体操作规程如下: [0025] The decision means for receiving the transponder to read message data from the external memory, generating divided data count module counting range based on the packet; specific procedures as follows:

[0026]当分频计数模块以FSK信号上升沿或下降沿作为计数时钟,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜6 ;若判决模块接收到的报文数据为0,则判决模块输出的计数范围为O〜7 ; [0026] When the prescaler counting rising or falling module FSK signal as a count clock, the data packets received if the decision block is 1, the decision module output count range is O~6; if decision block received packet data is 0, the decision module output count range is O~7;

[0027] 当分频计数模块以FSK信号上升沿和下降沿共同作为计数时钟,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜13 ;若判决模块接收到的报文数据为0,则判决模块输出的计数范围为O〜15。 [0027] When the prescaler counting module FSK signal rising and falling edges together as the count clock, if decision block received message data is 1, the decision module output count range is O~13; if decision block received packet data is 0, the decision module output count range is O~15.

[0028] 分频计数模块用于以外部FSK振荡器生成的FSK信号作为计数时钟,在判决模块生成的计数范围内进行计数;本实施方式中,若以FSK信号上升沿或下降沿作为计数时钟,则分频计数模块采用3位计数器;若以FSK信号上升沿和下降沿共同作为计数时钟,则分频计数模块采用4位计数器。 [0028] The frequency dividing means for counting an external FSK FSK signal generated by the oscillator as the count clock counts count range generated by the decision block; in this embodiment, if the FSK signal as the count clock rising or falling edge , the frequency dividing counter 3 counting modules; In terms of the FSK signal rising and falling edges together as the count clock, the frequency division counter 4 counts modules.

[0029] 当分频计数模块输出的计数结果达到计数范围的最大值,判决模块则将该计数结果清零后使分频计数模块重新计数。 [0029] When the output of the frequency division count module counting result reaches the maximum count range, then the decision block after the count results to zero so that dividing counting module counts again.

[0030] 时钟输出模块用于将分频计数模块输出计数结果的最高位作为应答器数据时钟并输出给外围存储器。 [0030] Output clock counter means for dividing the most significant bit of the count result of the module output as the response clock and outputs the data to the peripheral memory.

[0031] 本实施方式中,分频计数模块以二进制FSK信号上升沿作为计数时钟;那么该分频计数模块为3位计数器,判决模块根应答器报文数据来产生分频计数模块的计数范围,如果应答器报文数据为“ I ”,分频计数模块从O计数到6,如果应答器报文数据为“0”,分频计数模块从O计数到7 ;最后以分频计数模块第三位的结果作为提取出来的数据时钟。 [0031] In the present embodiment, the counting module to divide a rising edge of the binary FSK signal as a count clock; then the frequency dividing counter 3 is counting module, the root decision module transponder message data to generate a frequency division count module counting range If the transponder message data is "I", the prescaler counting module counts from O to 6, if the transponder message data is "0", the prescaler counting module counts from O to 7; Finally prescaler counting module section three as a result of the extracted data clock. 如图2所示,可以看出在每一个二进制FSK信号上升沿,分频计数模块加I。 2, it can be seen at each rising edge of a binary FSK signal, frequency dividing counter means-plus I. 最终提取出来的数据时钟频率是564KHz,满足应答器的要求。 The final extracted data clock frequency is 564KHz, to meet the requirements of the transponder.

[0032] 分频计数模块也可以二进制FSK信号下降沿作为计数时钟,该分频计数模块也为3位计数器,判决模块根应答器报文数据来判决分频计数模块的计数范围,如果应答器报文数据为“ I ”,分频计数模块从O计数到6,如果应答器报文数据为“0”,分频计数模块从O计数到7 ;最后以分频计数模块第三位的结果作为提取出来的数据时钟。 [0032] The module may also divide binary counting falling FSK signal as the count clock, the division is also counting module 3 counter, the root decision module transponder data packets to the judgment of the frequency range Count module, if the transponder message data is "I", the counting module counts the frequency-divided O to 6, if the answer message data is "0", the counting module counts the frequency-divided O to 7; and finally in the third division result of the counting module as the extracted data clock. 如图3所示,可以看出在每一个二进制FSK信号下降沿,分频计数模块加I。 3, it can be seen in each of the falling edge of a binary FSK signal, frequency dividing counter means-plus I. 最终提取出来的数据时钟频率是564KHz,满足应答器的要求。 The final extracted data clock frequency is 564KHz, to meet the requirements of the transponder.

[0033] 如果分频计数模块同时以二进制FSK信号上升沿和下降沿作为计数时钟,那么该分频计数模块为4位计数器,判决模块根应答器报文数据来判决分频计数模块的计数范围,如果应答器报文数据为“1”,分频计数模块从O计数到13,如果应答器报文数据为“0”,分频计数模块从O计数到15 ;最后以分频计数模块第四位的结果作为提取出来的数据时钟。 [0033] If the frequency dividing modules while counting rising and falling edges binary FSK signals as the count clock, then the frequency dividing module is a 4-bit counter counting, decision block root transponder data packets to the judgment of the counting module counts the frequency range If the transponder message data is "1", the division counting module counts from O to 13, if the transponder message data is "0", the prescaler counting module counts from O to 15; and finally to divide the counting module of four as a result of the extracted data clock. 如图4所示,可以看出在每一个二进制FSK信号上升沿和下降沿,分频计数模块加I。 4, it can be seen in each of the rising and falling edges binary FSK signal, frequency dividing counter means-plus I. 最终提取出来的数据时钟频率是564KHZ,也满足应答器的要求。 The final extracted data clock frequency is 564KHZ, also meet the requirements of the transponder.

[0034] 本实施方式通过分析应答器相关标准中规定的FSK信号频率(4.512MHz或 [0034] FSK signal of a predetermined frequency by analyzing the relevant standard transponder embodiment of the present embodiment (4.512MHz or

3.948MHz)和数据速率(564kbps,对应的读数据时钟为564KHz)发现,FSK信号频率约是数据速率的7倍(3.948MHz/564KHz)或8倍(4.512MHz/564KHz)。 3.948MHz) and data rate (564kbps, the data corresponding to the read clock is 564KHz) found, FSK signal frequency is about 7 times (3.948MHz / 564KHz), or eight times the data rate (4.512MHz / 564KHz). 故利用FSK信号作为分频计数模块的计数时钟,通过结合应答器报文数据来动态的产生分频计数器的计数范围来实现动态的分频,即可从FSK信号中提取出稳定的564KHz的数据时钟,以此来读取存储器中的应答器报文数据。 Therefore, as the data signal using FSK frequency division Count 564KHz clock module to achieve dynamic frequency division by binding to dynamically generate a frequency division count of the counter range of the transponder data message, the FSK signal can be extracted from the stable in clock, in order to read the transponder message data in the memory.

[0035] 本实施方式以较低频率的FSK信号作为分频计数模块的计数时钟,所以最多仅需要进行16分频(需要4位分频计数器)即可得到满足应答器相关标准要求的564KHZ数据时钟。 [0035] In the present embodiment, the FSK signal a lower frequency as the division Count clock module, it is only required up to 16 frequency division (division requires four counters) can be obtained 564KHZ transponder data meets the relevant standards clock. 相对于通过功率天线上的27.095MHz的信号进行48分频(需要6位分频计数器)得到564KHZ的数据时钟的方法,本实施方式的数据时钟发生装置在减小硬件开销的同时也能降低整个应答器的功耗。 48 relative to one division (division requires 6 counter) method for data obtained by the signal 564KHZ 27.095MHz clock on the power to the antenna, a data clock generating apparatus according to the present embodiment can be reduced while reducing the hardware cost of the entire power consumption of the transponder.

Claims (6)

  1. 1.一种应答器数据时钟的发生装置,包括FPGA ;其特征在于:所述的FPGA加载有判决模块、分频计数模块和时钟输出模块;其中: 所述的判决模块用于接收应答器的报文数据,根据所述的报文数据生成分频计数模块的计数范围; 所述的分频计数模块用于以FSK信号作为计数时钟,在所述的计数范围内进行计数; 所述的时钟输出模块用于将分频计数模块输出计数结果的最高位作为应答器数据时钟并输出。 A transponder data clock generating means including FPGA; wherein: said decision module is loaded with the FPGA, and a prescaler counting clock module output module; wherein: said decision means for receiving the transponder message data, the message data in accordance with the frequency component of the raw count range module; said frequency dividing means for counting as a count clock to the FSK signal, counts the count range; said clock output means for counting the frequency-divided output of the most significant bit block count result as the response data and clock outputs.
  2. 2.根据权利要求1所述的发生装置,其特征在于:当分频计数模块以FSK信号上升沿或下降沿作为计数时钟的前提下,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜6 ;若判决模块接收到的报文数据为O,则判决模块输出的计数范围为O〜7。 2. A generating apparatus according to claim 1, wherein: when the premise prescaler counting module FSK signal as a count rising or falling edge of the clock, when the data packet is received in decision block 1, then decision module output count range is O~6; if decision block received message data is O, then decision module output count range is O~7.
  3. 3.根据权利要求1所述的发生装置,其特征在于:当分频计数模块以FSK信号上升沿和下降沿共同作为计数时钟的前提下,若判决模块接收到的报文数据为1,则判决模块输出的计数范围为O〜13 ;若判决模块接收到的报文数据为O,则判决模块输出的计数范围为O 〜15。 3. The generator according to claim 1, wherein: when the frequency dividing counter module FSK signal rising and falling edges of the clock count together as the premise, if the data packet is received in decision block 1, decision block output count range is O~13; if decision block received message data is O, then decision module output count range is O ~15.
  4. 4.根据权利要求1所述的发生装置,其特征在于:所述的判决模块接收分频计数模块输出的计数结果,若计数结果达到计数范围的最大值,则将所述的计数结果清零后使分频计数模块重新计数。 4. The generator according to claim 1, wherein: said decision means for receiving counting result of the counting frequency-divided output of the module, if the counting result reaches the maximum count range, then the counting result is cleared after allowing the re-division counting module counts.
  5. 5.根据权利要求1所述的发生装置,其特征在于:所述的分频计数模块采用3位计数器或4位计数器。 The generating apparatus according to claim 1, wherein: said frequency dividing counter counting module using 3 or 4-bit counter.
  6. 6.根据权利要求5所述的发生装置,其特征在于:若以FSK信号上升沿或下降沿作为计数时钟,则分频计数模块采用3位计数器;若以FSK信号上升沿和下降沿共同作为计数时钟,则分频计数模块采用4位计数器。 6. A generator as claimed in claim 5, wherein: In terms of rising or falling FSK signal as the count clock, the frequency dividing counter 3 counting modules; In terms of the FSK signal rising and falling edges together as count clock, the frequency division counter 4 counts modules.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483193A (en) * 1995-03-24 1996-01-09 Ford Motor Company Circuit for demodulating FSK signals
CN1313974A (en) * 1998-06-22 2001-09-19 乔治·伦纳德·鲍威尔 Anti-collision tag apparatus and system
CN101432758A (en) * 2006-03-03 2009-05-13 威夫特伦德科技有限公司 Apparatus and methods for electromagnetic identification

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483193A (en) * 1995-03-24 1996-01-09 Ford Motor Company Circuit for demodulating FSK signals
CN1313974A (en) * 1998-06-22 2001-09-19 乔治·伦纳德·鲍威尔 Anti-collision tag apparatus and system
CN101432758A (en) * 2006-03-03 2009-05-13 威夫特伦德科技有限公司 Apparatus and methods for electromagnetic identification

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