CN103325773A - Packing structure for integrated circuit - Google Patents

Packing structure for integrated circuit Download PDF

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Publication number
CN103325773A
CN103325773A CN2012100784895A CN201210078489A CN103325773A CN 103325773 A CN103325773 A CN 103325773A CN 2012100784895 A CN2012100784895 A CN 2012100784895A CN 201210078489 A CN201210078489 A CN 201210078489A CN 103325773 A CN103325773 A CN 103325773A
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CN
China
Prior art keywords
chip
unit
integrated circuit
chip unit
circuit package
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CN2012100784895A
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Chinese (zh)
Inventor
陈声寰
王曙民
韩肇伟
李威侬
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民瑞科技股份有限公司
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Priority to CN2012100784895A priority Critical patent/CN103325773A/en
Publication of CN103325773A publication Critical patent/CN103325773A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention relates to a packing structure for an integrated circuit. The packing structure comprises a first chip unit and a second chip unit tightly combined with the first chip unit. The second chip unit comprises at least one semiconductor layer and at least one metal layer, the second chip unit comprises a plurality of apertures penetrating through the semiconductor layer and the metal layer, and each aperture respectively penetrates through the second chip unit. In addition, the first chip unit is electrically connected with an output/input joint element. The packing structure for the integrated circuit can test the first chip unit through the output/input joint element and can directly cut the first chip unit into a plurality of grains without a general packing procedure. Thus, packing testing cost is effectively reduced, and the size of a packed chip can be reduced.

Description

集成电路的封装结构 The integrated circuit packaging structure

技术领域 FIELD

[0001] 本发明涉及一种集成电路的封装结构,特别是指一种以一芯片单元作为基板的集成电路的封装结构。 [0001] The present invention relates to an integrated circuit package structure, and more particularly to a cell in a chip as an integrated circuit packaging structure of the substrate.

背景技术 Background technique

[0002] 现今一芯片封装的方式概略描述如下:依据一晶圆(Wafer)上多数个晶粒(Die)的排列位置进行切割后,将每一晶粒分别安装到对应的一导线架(Lead frame)或是一个基板(Substrate)上,使得晶粒中的多数个导电脚位(Pin)与导线架或是基板电连接,接收一组测试电压信号,以进行芯片测试。 [0002] Nowadays a schematic manner the chip package is described below: after cutting a plurality of crystal grains according to (Die) arrangement position on a wafer (Wafer), are attached to each die corresponding to a lead frame (Lead a frame) or a substrate (substrate,), such that the majority of the grains of conductive pin (pin) connected to the electrical lead frame or substrate, a set of test voltage signal is received, to perform chip testing.

[0003] 此外,从现今封装技术中晶粒与基板接合方式来做进一步的观察,大致可分为打线接合型(Wire bond, WB )> 自动压焊型(Tape automatic bonding, TAB)、覆晶型(Flip chip, FC)封装方式,若以基板接脚型态来观察,大致可分为引脚插入型(Pin-through-hole, PTH)、表面粘着型(Surface mount technology, SMT)> 外围型(Peripheral package)及数组型(Array area)等,然而,随着电子产品持续朝轻、薄、短、小的趋势演进,芯片封装的技术也逐渐从早期的打线接合型变成以覆晶型为主,且基板接脚型态也由引脚插入型变成以数组型为主(如:锡球格数组封装(Ball Grid Array, BGA)。 [0003] In addition, the current from the die and the package substrate bonding techniques do further observation mode, can be divided into a wire bonding type (Wire bond, WB)> automated bonding type (Tape automatic bonding, TAB), cover Form (Flip chip, FC) packages, if the observed patterns for the substrate pins, can be divided insertion-type pin (pin-through-hole, PTH), a surface mount type (surface mount technology, SMT)> peripheral type (peripheral package) type and an array (array area) and the like, however, with electronic products continue toward light, thin, short, small evolution trend, chip packaging technology gradually from the early to the wire bonding type into COG type main patterns and the substrate also becomes a pin inserted into the pin array type to type-based (eg: ball grid array package, tin (ball grid array, BGA).

[0004] 举例来说,一覆晶锡球格数组封装(FC BGA)如图1所示,一个晶粒910利用多数个锡球991与一个基板920连结,同时所述锡球991与锡铅合金材质的基板接脚992有效电连接,而图2显示一打线接合锡球格数组封装(Wire bond BGA),其中晶粒810是以金属线892与基板820连结。 [0004] For example, a flip-chip solder ball grid array package (FC BGA) shown in Figure 1, a die 910 using a plurality of solder balls 991 coupled with a substrate 920, while the tin-lead solder ball 991 992 alloy substrate effective electrical pin connector, and Figure 2 shows a wire-bonding the solder ball grid array package (wire bond BGA), which is a metal die 810 and the substrate 820 connected to line 892.

[0005] 从上述芯片封装技术中,无论何者都须以一个基板(或是一导线架)做为承载晶粒的装置,且晶粒与基板之间都须以锡球或是金属线的方式连结,是目前芯片封装技术的主流方式之一。 [0005] From the above-described chip package technique, whichever are to be a substrate (or a lead frame) as the device carrier grains, and are to be solder balls or metal wire manner between the die and the substrate link, is one of the main ways the current chip packaging technology.

发明内容 SUMMARY

[0006] 有鉴于此,本发明的目的在于提供一种集成电路的封装结构。 [0006] In view of this, an object of the present invention to provide an integrated circuit package.

[0007] 为达到上述目的,本发明提供一种集成电路的封装结构,所述集成电路的封装结构包含: [0007] To achieve the above object, the present invention provides an integrated circuit package, the integrated circuit packaging structure comprising:

一第一芯片单兀;以及 A first single-chip Wu; and

一第二芯片单元,其与所述第一芯片单元电性连接,所述第二芯片单元具有至少一半导体层与至少一金属层,且第二芯片单元具有多数个贯穿所述半导体层与金属层的孔径;其中,每一孔径分别贯穿第二芯片单元,且第一芯片单元与一输出输入接合元件电性连接。 A second chip unit connected to the first electrically chip unit, the second unit having at least one semiconductor chip and at least one layer of the metal layer, and a second chip having a plurality of cells extending through the semiconductor layer and the metal aperture layer; wherein each chip unit through the second aperture, respectively, with a chip unit and a first output connected to an input electrically engaging element.

[0008] 作为优选方案,其中所述第二芯片单元还具有一接合金属层,且根据半导体工艺将所述接合金属层制作出多数个输出输入接合元件。 [0008] As a preferred embodiment, wherein the chip unit further having a second bonding metal layer, the metal layer and the semiconductor process to produce a plurality of input and output element engaging the engagement.

[0009] 作为优选方案,其中所述集成电路的封装结构还包含一接合层单元,且根据半导体工艺将所述接合层单元制作出多数个输出输入接合元件。 [0009] As a preferred embodiment, wherein the packaged integrated circuit structure further comprises a bonding layer unit, and the semiconductor layer process unit according to engage a plurality of input and output to produce engaging element. [0010] 作为优选方案,其中所述第一芯片单元、第二芯片单元及接合层单元封装成一集成电路模组。 [0010] As a preferred embodiment, wherein the first chip unit, the second unit and the bonding layer unit chip packaged into an integrated circuit module.

[0011] 作为优选方案,其中所述第二芯片单元的面积大于第一芯片单元的面积。 [0011] As a preferred embodiment, wherein the second area is larger than the area of ​​the first chip unit chip unit.

[0012] 作为优选方案,其中所述第二芯片单元的面积等于第一芯片单元的面积。 [0012] As a preferred embodiment, wherein the second area is equal to the area of ​​the first chip unit chip unit.

[0013] 作为优选方案,其中所述第一芯片单元与第二芯片单元封装成一集成电路模组。 [0013] As a preferred embodiment, wherein the first chip unit and the second unit is packaged into an integrated circuit chip module.

[0014] 作为优选方案,其中所述半导体层的材质为硅。 [0014] As a preferred embodiment, wherein a material of the semiconductor layer is silicon.

[0015] 作为优选方案,其中所述半导体层的材质为砷化镓。 [0015] As a preferred embodiment, wherein a material of the semiconductor layer is GaAs.

[0016] 本发明所提供的集成电路的封装结构,经由该输出输入接合元件对该第一芯片单元进行测试,并且无须经过一般封装程序即可直接将该第一芯片单元切割成多数个晶粒,因此,可以有效降低封装测试成本及缩减芯片封装后的面积大小。 [0016] The integrated circuit package of the present invention is provided, via which the engagement element on the first output of the input test chip unit, without going through the conventional package and the program can direct the first plurality of die cut into chip units Therefore, packaging and testing costs can be effectively reduced and the reduced size of the area of ​​a chip package.

附图说明 BRIEF DESCRIPTION

[0017] 图1是现有技术中一覆晶锡球格数组封装的侧视不意图; [0017] FIG. 1 is a prior art flip chip solder ball grid array package is not intended to side;

图2是现有技术中一打线接合锡球格数组封装的侧视示意图; FIG 2 is a prior art wire bonding solder ball grid array package side view;

图3是本发明中第一较佳实施例的侧视示意图; FIG 3 is a side view of a first preferred embodiment of the present invention;

图4是本发明中第一较佳实施例经半导体工艺得到多数电路元件及输出输入接合元件后的侧视不意图; FIG 4 is a preferred embodiment of the present invention in a first embodiment of a semiconductor process, and an output circuit element of the majority of the input side via the engaging element is not intended;

图5是本发明中第一较佳实施例经半导体工艺得到多数电路元件及输出输入接合元件后的俯视不意图;`` FIG 5 is a first preferred embodiment of the present invention, the process of the majority of the semiconductor circuit element and an output element after joining a top input not intended by the; ``

图6是本发明中第二较佳实施例的侧视示意图; FIG 6 is a schematic side view of a second preferred embodiment of the present invention;

图7是本发明中第三较佳实施例的俯视示意图。 7 is a plan schematic view of a third preferred embodiment of the present invention, FIG.

[0018]【主要元件符号说明】 [0018] The main reference numerals DESCRIPTION

晶圆片-10 ;第一芯片单元-11 ;导电脚位-110 ;半导体层-111;金属层-112;第二芯片单元-12 ;孔径-121 ;接合层单元-13 ;输出输入接合元件-131 ; -10 wafer; a first chip units -11; -110 conductive pin; -111 semiconductor layer; -112 metal layer; and a second chip units -12; -121 aperture; -13 bonding layer unit; engagement element input and output -131;

晶粒-810 ;基板-820 ;金属线-892 ; Die -810; -820 substrate; a metal wire -892;

晶粒-910 ;基板-920 ;锡球-991 ;基板接脚-992 ; Die -910; -920 substrate; solder ball -991; -992 pin substrate;

电路元件-CKTI〜CKTn ; Circuit elements -CKTI~CKTn;

晶粒_Dl〜Dm。 Grain _Dl~Dm.

具体实施方式 Detailed ways

[0019] 有关本发明的特征与技术内容,以下配合参考附图的三个较佳实施例详细说明如下。 Detailed Description [0019] For technical features of the present invention, the following with reference to the drawings following three preferred embodiments.

[0020] 由于本发明具有多数个较佳实施例,因此在详细说明之前,在以下较佳实施例中的相似的元件是以相同的编号来表示。 [0020] Since the present invention has a most preferred embodiment, prior to detailed description therefore, similar elements in the following preferred embodiment is represented by the same reference numerals.

[0021] 1.集成电路的封装结构的第一较佳实施例 The first preferred embodiment of a package structure [0021] 1. IC

参阅图3,本发明的一较佳实施例,包含:一个第一芯片单元11、一个第二芯片单元12及一个接合层单元13。 Referring to Figure 3, a preferred embodiment of the present invention, comprising: a first chip unit 11, a second chip unit 12, and a joining layer unit 13. 第一芯片单元11、第二芯片单元12分别包括至少一半导体层111与至少一金属层112,且半导体层111的材质为一半导体材料(如:娃(Si)、砷化镓(GaAs)等),且接合层单元13是一金属层。 The first chip unit 11, the second chip 12 each unit comprises at least a semiconductor layer 111 with at least a metal layer 112, and the semiconductor material of layer 111 is a semiconductor material (such as: Wa (Si), gallium arsenide (GaAs), etc. ), and the bonding layer 13 is a metal layer unit. [0022] 值得说明的是,第一芯片单元11、第二芯片单元12、接合层单元13以第二芯片单元12介于第一芯片单元11与接合层单元13之间依序接合,且第二芯片单元12的面积大于或等于第一芯片单元11的面积,此外,由于接合层单元13为一金属层,故也可利用第二芯片单元12中的最底层据以实施。 [0022] It should be noted that the first chip unit 11, the second chip unit 12, a second bonding layer unit 13 interposed between the first chip unit 12 sequentially chip unit 11 and the bonding layer 13 between the engagement means and the first two chip unit area greater than or equal to the area 12 of the first die unit 11 and, in addition, since the bonding layer is a metal layer unit 13, so that the bottom may be utilized in the chip unit 12 according to the second embodiment.

[0023] 第一芯片单元11、第二芯片单元12是以半导体工艺的方式(如:曝光、氧化层沉积、蚀刻、显影等),制作相关电路元件于其中,由于一应用半导体工艺的电路元件制作方式并非本发明的主要特征,请参酌Neil HEWeste及Kamran Eshraghian等人所著的“Principles of CMOS VLSI Design”一书中相关内容的说明,在此不再多加赘述。 [0023] The first chip unit 11, the second chip unit 12 is a semiconductor process method (eg: exposure, oxide deposition, etching, development, etc.), production-related circuit elements therein, since the circuit element in a semiconductor process applications production methods is not the main feature of the invention, please deliberate Neil HEWeste and Kamran Eshraghian et al., "Principles of CMOS VLSI Design" a book description related content, which is not narrated herein.

[0024] 然后,在第二芯片单元12中设置多数个孔径121,其中,每一孔径121分别贯穿第二芯片单元12。 [0024] Then, a plurality of second aperture 121 in the chip unit 12, wherein each aperture 121 through the second chip unit 12, respectively.

[0025] 最后,在接合层单元13中,利用半导体工艺的方式制作多数个输出输入接合元件131 (I/O Pad)ο [0025] Finally, the bonding layer unit 13, using a semiconductor production process a plurality of input-output manner engaging element 131 (I / O Pad) ο

[0026] 联合参阅图4、5,假设第一芯片单元11中具有η个以半导体工艺制作出的电路元件CKTf CKTn,且每一电路元件CKTf CKTn分别具有其对应的导电脚位110,每一导电脚110分别经由一对应的孔径121电连接至一对应的输出输入接合元件131上,使得每一电路元件CKTfCKTn得以经由其对应的输出输入接合元件131上接收一组参考电压(图未示)。 [0026] Referring to Figure 4, joint, assuming that the first chip unit 11 having a semiconductor process η produce CKTf CKTn circuit elements, and each circuit element CKTf CKTn each have their corresponding conductive pins 110, each a conductive pin 110 is connected to a corresponding aperture via an electrical output corresponding to the input 121 of the engaging member 131, so that each circuit element is CKTfCKTn engagement receiving a set of reference voltages on the output device 131 via the corresponding input (not shown) .

[0027] 当第一芯片单元11中的电路元件接收该组参考电压且完成测试后,即可经由晶圆切割方式,得到第一芯片单元11中的每一电路元件CKTfCKTn,由于所述电路元件CKTfCKTn以第二芯片单元12作为支撑,并可通过对应的输出输入接合元件131,以传送或接收信号,因此,并不需要经过如打线、填胶等传统封装流程处理,所以可以降低该电路元件的生产成本。 [0027] When the circuit element chip 11 in the first unit receives the set of reference voltages and complete the test, the wafer can be cut via embodiment, each circuit element CKTfCKTn 11 to obtain a first chip unit, since the circuit element CKTfCKTn chip unit 12 as a second support element 131 may engage a corresponding input and output, to transmit or receive signals, therefore, does not need to go through such wire, fillers and other conventional encapsulation process flow, the circuit can be reduced production cost element.

[0028] 2.集成电路的封装结构的第二较佳实施例 The second preferred embodiment of a package structure [0028] 2. The integrated circuit

参阅图6,第二较佳实施例与第一较佳实施例最大的不同点在于:当第二芯片单元12的最下层为一金属层时,该金属层即可视为接合层单元13,并在该金属层上制作多数个输出输入接合元件,也就是说,接合层单元13与第二芯片12也可以一体成型的方式制作,并不局限于第一较佳实施例中分别制作的方式而实施。 Referring to Figure 6, for example, the maximum difference is the second preferred embodiment and the first preferred embodiment: when the second lowermost chip unit 12 is a metal layer, the metal layer 13 may be regarded as the bonding layer unit, a plurality of input and produce an output member engaging on the metal layer, i.e., the bonding layer 13 made of the second unit 12 may be integrally formed chip manner, the first embodiment is not limited to the preferred embodiment were produced in implemented.

[0029] 3.集成电路的封装结构的第三较佳实施例 The third preferred embodiment of a package structure [0029] 3. The integrated circuit

参阅图7,由于包含所述电路元件CKTfCKTn的第一芯片单元11并不需要如现有技术般的分别设置于一导线架或是一基板上,因此,在本较佳实施例中,是将多数个第一芯片单元I同时设置于一晶圆片10 (Wafer)中,并配合一对应的第二芯片单元12,经由第二芯片单元12的孔径将每一第一芯片单元I的导电脚位(Pin)与一具有多数个输出输入接合元件131的接合层单元13电连接,所以,若是需要进行封装时,每一第一芯片单元11与对应的第二芯片单元12,及接合层单元13可直接共同进行封装,然后经由晶圆切割的程序后,即可得到多数个分别具有所述电路元件CKTrCKTn的晶粒DrDm,换句话说,本较佳实施例可以有效缩减每一具有所述电路兀件CKTl CKTn的晶粒的面积。 Referring to FIG 7, since the circuit element comprises a first CKTfCKTn chip unit 11 is not required as in the prior art like are disposed on a substrate or a lead frame, and therefore, in the present preferred embodiment, is a second plurality of chip unit I while the first chip unit arranged on a wafer 10 (wafer) in a corresponding fitting 12 and, via the second aperture unit 12 of each chip of the first conductive pin chip unit I bit (Pin) and having a so, if the package is required, each of the first chip unit 11 and the unit 12 corresponding to the second chip, and a bonding layer unit outputs a plurality of engaging element input unit 13 is connected electrically bonding layer 131, joint 13 can be directly packaged, then after wafer dicing, via procedures, to obtain a plurality of crystal grains each having DrDm CKTrCKTn said circuit element, in other words, the present preferred embodiment can effectively reduce each having the Wu area of ​​the circuit element CKTl CKTn grains.

[0030] 本发明与现有技术最大的不同点在于,本发明将该第一芯片单元与该第二芯片单元贴合之后,该第一芯片单元得以经由该等第二芯片单元中的孔径接收一组参考电压以进行测试,因此,并非如现有技术一般,将晶圆切割成多数个晶粒后,再将晶粒置于导线架或是基板上以进行封装测试,因此,相较于现有技术而言,本发明整合该第一芯片单元、第二芯片单元、接合层单元于该集成电路中,即可经由该输出输入接合元件对该第一与第二芯片单元进行测试与使用,并且无须经过一般封装程序(如:设置表面粘着型(SMT)接脚、或是以打线接合型(WB)进行芯片封装),即可直接将该第一芯片单元切割成多数个晶粒,因此,相较于现有技术而言,可以有效降低封装测试成本及缩减芯片封装后的面积大小,故确实能达成本发明的目的。 [0030] The present invention and the prior art is that the maximum difference, then the present invention, the first unit and the second chip bonding unit chip, the unit chip is received via the first such unit in a second chip aperture a set of reference voltages for testing, therefore, not as in the prior art in general, after the wafer is cut into a plurality of dies and then placed on the grains to make the lead frame or package test substrate, compared to the prior art, the present invention is the first integrated chip unit, the second unit chip, the bonding layer unit in the integrated circuit, can be tested using the first and second engaging element chip unit via which input output , and without going through the conventional package (such as: a surface mount type disposed (SMT) pins, or to the wire bonding type (WB) for a chip package), the first chip can be directly cut into a plurality of die units Therefore, compared to the prior art, the testing can reduce packaging costs and reduce the size of the area of ​​the chip package, it can really achieve the object of the present invention.

[0031] 以上所述,仅为本发明的较佳实施例,并非用以此限定本发明的专利范围,举凡依本发明专利精神所作的等效变化与修饰等,均同理属于本发明的专利保护范围内。 [0031] The above are only preferred embodiments of the present invention, is not patentable scope is defined by this invention, that whenever such modifications and equivalent other under this Patent made in the spirit of the invention, belonging to the present invention shall fall within the scope of the patent.

Claims (9)

1.一种集成电路的封装结构,其特征在于,所述集成电路的封装结构包含: 一第一芯片单兀;以及一第二芯片单元,其与所述第一芯片单元电性连接,所述第二芯片单元具有至少一半导体层与至少一金属层,且第二芯片单元具有多数个贯穿所述半导体层与金属层的孔径;其中,每一孔径分别贯穿第二芯片单元,且第一芯片单元与一输出输入接合元件电性连接。 An integrated circuit package, wherein the packaged integrated circuit structure comprising: a first single-chip Wu; chip and a second unit with the first unit is electrically connected to the chip, the said second unit having at least one semiconductor chip and at least one layer of the metal layer, and a second chip having a plurality of cells extending through the semiconductor layer and the metal layer aperture; wherein each chip unit through the second aperture, respectively, and the first chip input unit and an output electrically connected to the engagement member.
2.如权利要求1所述集成电路的封装结构,其特征在于,所述第二芯片单元还具有一接合金属层,且根据半导体工艺将所述接合金属层制作出多数个输出输入接合元件。 2. The integrated circuit package of claim 1, characterized in that, said second unit further having a chip bonding metal layer, the metal layer and the semiconductor process to produce a plurality of engaging said input and output engagement element.
3.如权利要求1所述集成电路的封装结构,其特征在于,所述集成电路的封装结构还包含一接合层单元,且根据半导体工艺将所述接合层单元制作出多数个输出输入接合元件。 3. The integrated circuit package of claim 1, characterized in that the integrated circuit package structure further includes a bonding layer unit, and the semiconductor layer process unit according to engage a plurality of outputs to produce an input element engaging .
4.如权利要求3所述集成电路的封装结构,其特征在于,所述第一芯片单元、第二芯片单元及接合层单元封装成一集成电路模组。 4. The integrated circuit package of claim 3, characterized in that said first chip unit, the second unit and the bonding layer unit chip packaged into an integrated circuit module.
5.如权利要求1所述集成电路的封装结构,其特征在于,所述第二芯片单元的面积大于第一芯片单元的面积。 5. The integrated circuit package of claim 1, characterized in that the chip area of ​​the second cell is greater than the area of ​​the first chip unit.
6.如权利要求1所述集成电路的封装结构,其特征在于,所述第二芯片单元的面积等于第一芯片单元的面积。 6. The integrated circuit package of claim 1, characterized in that the chip area of ​​the second unit is equal to the area of ​​the first chip unit.
7.如权利要求1所述集成电路的封装结构,其特征在于,所述第一芯片单元与第二芯片单元封装成一集成电路模组。 7. The integrated circuit package of claim 1, characterized in that the first chip unit and the second unit is packaged into an integrated circuit chip module.
8.如权利要求1所述集成电路的封装结构,其特征在于,所述半导体层的材质为硅。 8. The integrated circuit package of claim 1, characterized in that the material of the semiconductor layer is silicon.
9.如权利要求1所述集成电路的封装结构,其特征在于,所述半导体层的材质为砷化镓。 9. The integrated circuit package of claim 1, characterized in that the material of the semiconductor layer is GaAs.
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WO2000001208A1 (en) * 1998-06-30 2000-01-06 Formfactor, Inc. Assembly of an electronic component with spring packaging
US6379982B1 (en) * 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US20060065976A1 (en) * 2004-09-24 2006-03-30 Min-Chih Hsuan Method for manufacturing wafer level chip scale package structure
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array
WO2000001208A1 (en) * 1998-06-30 2000-01-06 Formfactor, Inc. Assembly of an electronic component with spring packaging
US6379982B1 (en) * 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US20060065976A1 (en) * 2004-09-24 2006-03-30 Min-Chih Hsuan Method for manufacturing wafer level chip scale package structure
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects

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