CN103310735B - A kind of support gray shade scale to expand display control method and system - Google Patents
A kind of support gray shade scale to expand display control method and system Download PDFInfo
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- CN103310735B CN103310735B CN201310263013.3A CN201310263013A CN103310735B CN 103310735 B CN103310735 B CN 103310735B CN 201310263013 A CN201310263013 A CN 201310263013A CN 103310735 B CN103310735 B CN 103310735B
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Abstract
The invention belongs to display control technology field, provide a kind of support gray shade scale to expand display control method and system.The method and system are in synchro control card, the gradation data to be shown that each display precision is n1 is processed, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and have n2≤n1 and n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.Pass through the method, volume of transmitted data between synchro control card and driving chip is n2 position from existing 16 potential drops, therefore, message transmission rate between synchro control card and driving chip improves 16/n2 doubly, thus improve the upper frequency limit of grayscale clock signal, improve row frequency sweep rate, and then improve the refresh rate of picture.
Description
Technical field
The invention belongs to display control technology field, particularly relate to a kind of LED of being mainly used in display and control aspect and the display control method supporting gray shade scale to expand, system and synchro control card, driving chip.
Background technology
In the display and control field of LED display, adopt pulse-length modulation (Pulse WidthModulation, PWM) mode, realize the adjustment to each LED luminosity.Specifically, be within the fixing display cycle, by regulate LED bright/the time ratio that goes out, reach the object that LED luminance regulates, and when LED is bright, what flow through is fixing electric current, and the wavelength of light can not change, and avoids the color tuning problems of LED under different electric current.
Show the typical structure of the display control program of LED display as Fig. 1, it comprises the driving chip of synchro control card and some cascades.Wherein, serial data transmission line SDI is a level on line, and data clock line DCLK, grayscale clock line GCLK and latch line LE are respectively bridging line; Serial data transmission line SDI coordinates with data clock line DCLK, obtains required display data, latches line LE and coordinates with data clock line, obtain required steering order.Specifically, display data transmissions process between synchro control card and driving chip is: synchro control cartoon crosses serial data transmission line SDI transmits gradation data from certain precision to connected driving chip, after the display data transmissions of port arbitrary in driving chip, the gradation data of this port is latched, so repeatedly, until the equal end of transmission of the gradation data of all of the port and latch after, latch the gradation data of entirety, the gradation data of latch is used for output display.
In prior art, the transmission mode of 16 gradation datas is adopted between synchro control card and driving chip, that is to say, synchro control calorie requirement sends 16 gradation datas to driving chip within a display cycle, even if when showing the accuracy requirement of data lower than 16, still 0 and the transmission figure place of gradation data is remained unchanged need be mended at low level.And for showing the dynamic screen of dynamic menu, its picture refreshing rate depends primarily on line feed sweep frequency (that is: row frequency sweep rate), then when the display data of a dynamic screen display fixing display precision, need after the basic cycle of every a line LED complete display pwm signal, could enter a new line, now, the row frequency sweep rate of dynamic screen can be expressed as:
Wherein, F
framerow frequency sweep rate, F
gCLKbe the frequency of grayscale clock signal, n is display precision, and m is the number of scanning lines.Visible, if gradation data transmission quantity is large, in order to complete the transmission of gradation data, the number of cycles of desired data clock signal DCLK is many, frequency is fast, and then limit the upper frequency limit of grayscale clock signal GCLK, reduce row frequency sweep rate, and then reduce the refresh rate of picture.Such as, suppose that the driving chip number of cascade is 12, every sheet driving chip has 16 to drive port, display precision is 10, then within 1024 grayscale clock cycles (i.e. a display cycle), volume of transmitted data between synchro control card and driving chip is: the driving port number 16=3072 of gradation data figure place 16 × driving chip number 12 × each driving chip, that is to say, the frequency of data clock signal DCLK needs three times that reach grayscale clock signal GCLK, in practice, the maximum frequency of data clock signal DCLK and grayscale clock signal GCLK is 30MHz, and in this example, the frequency of maximum data clock signal DCLK is 30MHz, the frequency of maximum grayscale clock signal GCLK is restricted to 10MHz, for 8 scanning dynamic screen, then row frequency sweep rate is:
refresh rate is lower, and display precision is higher, and because the volume of transmitted data between synchro control card and driving chip does not promote, therefore refresh rate is lower, reduces user experience.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of display control method supporting gray shade scale to expand, be intended to solve in prior art, owing to adopting the transmission mode of 16 gradation datas between synchro control card and driving chip, the data volume of transmission is large, cause the refresh rate of picture low, the problem of user experience difference.
The embodiment of the present invention is achieved in that a kind of display control method supporting gray shade scale to expand, and said method comprising the steps of:
Synchro control card processes the gradation data to be shown that each display precision is n1, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip, described n1 and n2 is positive integer, and n2≤n1, n2 < 16,2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical;
Described synchro control card sends grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to described driving chip;
The precision that the driving chip that described driving chip samples described synchro control card or upper level connection at rising edge and/or the negative edge of described data clock signal exports is the gradation data of n2;
The gradation data that the described port latch instruction that described driving chip sends in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous.
Another object of the embodiment of the present invention is to provide a kind of synchro control card, and described synchro control card comprises:
Data processing module, for being that the gradation data to be shown of n1 processes to each display precision, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip, described n1 and n2 is positive integer, and n2≤n1, n2 < 16,2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical;
Transport module, for sending grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to described driving chip.
Another object of the embodiment of the present invention is to provide a kind of driving chip, and described driving chip comprises:
Sampling module, the precision that the driving chip of sampling described synchro control card or upper level connection for the rising edge of data clock signal that sends at synchro control card and/or negative edge exports is the gradation data of n2, described n2 is positive integer, and n2 < 16;
Driver module, for the gradation data that the port latch instruction sent in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous.
Another object of the embodiment of the present invention is to provide a kind of display control program supporting gray shade scale to expand, and described system comprises the driving chip that synchro control card is connected with cascade, and described synchro control card is synchro control card as above.
Display control method and the system of the support gray shade scale expansion that the embodiment of the present invention proposes are in synchro control card, the gradation data to be shown that each display precision is n1 is processed, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and have n2≤n1 and n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.Pass through the method, volume of transmitted data between synchro control card and driving chip is n2 position from existing 16 potential drops, therefore, message transmission rate between synchro control card and driving chip improves 16/n2 doubly, thus in terms of existing technologies, improve the upper frequency limit of grayscale clock signal GCLK, improve row frequency sweep rate, and then improve the refresh rate of picture.
Accompanying drawing explanation
Fig. 1 is in prior art, the exemplary block diagram of the display control program of LED display.
Fig. 2 is the process flow diagram of the display control method of the support gray shade scale expansion that the embodiment of the present invention one provides;
Fig. 3 is in the embodiment of the present invention one, and the detail flowchart that display gray scale data carry out processing treated by synchro control card;
Fig. 4 is in the embodiment of the present invention one, and driving chip drives the detail flowchart of each luminescence unit luminescence;
Fig. 5 is the process flow diagram of the gradation data output intent that the embodiment of the present invention two provides;
Fig. 6 is in the embodiment of the present invention two, treats the detail flowchart that display gray scale data carry out processing;
Fig. 7 is the process flow diagram of the driving method that the embodiment of the present invention three provides;
Fig. 8 is in the embodiment of the present invention three, drives the detail flowchart of each luminescence unit luminescence;
Fig. 9 is the structural drawing of the synchro control card that the embodiment of the present invention four provides;
Figure 10 is the structural drawing of data processing module in Fig. 9;
Figure 11 is the structural drawing of the driving chip that the embodiment of the present invention five provides;
Figure 12 is a kind of circuit diagram of the driving chip that the embodiment of the present invention five provides;
Figure 13 triggers a kind of circuit diagram along processing unit in Figure 12;
Figure 14 is a kind of circuit diagram of n2 bit shift buffer in Figure 12;
Figure 15 is a kind of circuit diagram of n2 digit counter in Figure 12;
Figure 16 is a kind of circuit diagram of Pwm controller in Figure 12;
Figure 17 is a kind of circuit diagram of comparer in Figure 12;
Figure 18 is a kind of circuit diagram of instruction control unit in Figure 12;
Figure 19 is a kind of circuit diagram of Figure 12 gradation data storage unit.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
For prior art Problems existing, the present invention proposes a kind of display control method supporting gray shade scale to expand, in the method, synchro control card processes the gradation data to be shown that each display precision is n1, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and have n2≤n1 and n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.Implementation of the present invention is described in detail below in conjunction with embodiment:
embodiment one
The embodiment of the present invention one proposes a kind of display control method supporting gray shade scale to expand, and as shown in Figure 2, comprising:
Step S1: synchro control card processes the gradation data to be shown that each display precision is n1, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip.Wherein, n1 and n2 is positive integer, and n2≤n1, n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical, that is to say, the gray shade scale that the gradation data to be shown that the gray shade scale that the gradation data that one group of display precision is respectively n2 characterizes and corresponding display precision are n1 characterizes is consistent.
Further, in the embodiment of the present invention one, as shown in Figure 3, step S1 can comprise again:
Step S11: the magnitude relationship between the display precision n1 of the gradation data to be shown that synchro control card is more current and display precision n2.
Step S12: according to the comparative result of step S11, if display precision n1 equals display precision n2, then current gradation data to be shown is directly exported to driving chip by synchro control card.
Step S13: according to the comparative result of step S11, if display precision n1 is greater than display precision n2, then synchro control card extracts the low n1-n2 bit data D1 in current gradation data to be shown, and calculates decimal data K corresponding to data D1.
Step S14: according to the comparative result of step S11, if display precision n1 is greater than display precision n2, then synchro control card extracts the high n2 bit data D2 in current gradation data to be shown.
Step S15: synchro control card judges whether everybody is 1 to data D2, is perform step S18, otherwise perform step S16.
Step S16: data D2 is added 1 by synchro control card, obtains data D3.
Step S17: synchro control card by K data D3, and 2
n1-n2-K data D2 Serial output is to driving chip.
Step S18: synchro control card is by 2
n1-n2individual data D2 Serial output is to driving chip.
According to above-mentioned steps S13 to step S18, if current gradation data to be shown is B
n1-1b
n1-2b
0, the dutycycle of the required display of this n1 bit binary data is Duty1=(B
n1-1*2
n1-1+ B
n1-2*2
n1-2+ ... + B
0*2
0)/2
n1.After step S13, the data D1 of extraction is B
n1-n2-1b
n1-n2-2b
0, the decimal data K=(B that data D1 is corresponding
n1-n2-1*2
n1-n2-1+ B
n1-n2-2*2
n1-n2-2+ ... + B
0*2
0); Afterwards, the data D2 extracted through step S14 is B
n1-1b
n1-2b
n1-n2; Afterwards, if the n1-n2 in data D2 binary data is 1, then perform step S18, by 2
n1-n2individual data D2 Serial output is to driving chip, if the n1-n2 in data D2 binary data is not 1 entirely, then perform step S16, obtaining data D3 is B
n1-1b
n1-2b
n1-n2+ 1, and after obtaining data D3, perform step S17, synchro control card is by K data D3 and 2
n1-n2-K data D2 Serial output is to driving chip.Wherein, data D3 is 2
n2in the individual grayscale clock signal cycle, effective grayscale clock number of cycles is B
n1-1*2
n2-1+ B
n1-2*2
n2-2+ ... + B
n1-n2*2
0+ 1, data D2 is 2
n2in the individual grayscale clock signal cycle, effective grayscale clock number of cycles is B
n1-1*2
n2-1+ B
n1-2*2
n2-2+ ... + B
n1-n2*2
0, like this, 2
n1in the individual grayscale clock cycle, effective grayscale clock number of cycles is K*(B
n1-1*2
n2-1+ B
n1-2*2
n2-2+ ... + B
n1-n2*2
0+ 1)+(2
n1-n2-K) * (B
n1-1*2
n2-1+ B
n1-2*2
n2-2+ ... + B
n1-n2*2
0), the dutycycle representated by it is Duty2=(B
n1-1*2
n1-1+ B
n1-2*2
n1-2+ ... + B
0*2
0)/2
n1, namely meet Duty2=Duty1.
For example, suppose n1=16, n2=10, current gradation data to be shown is 3a35, and binary representation is 0011101000110101, and its required dutycycle of showing is Duty1=14901/65536.After step S13, the data D1 of extraction is 110101, data D1 corresponding decimal number K=53; Afterwards, through step S14, the data D2 of extraction is 0011101000; Because the binary data in data D2 is not 1 entirely, therefore perform step S16, obtaining data D3 is 0011101000+1=0011101001; Afterwards, perform step S17, synchro control card by 53 data D3 and 11 data D2 Serial output to driving chip.Wherein, in data D3 2
10in the individual grayscale clock signal cycle, effective grayscale clock signal number of cycles is Lighth=233, and data D2 is 2
10in the individual grayscale clock signal cycle, effective grayscale clock signal number of cycles is Lightl=232, like this, 2
16in the individual grayscale clock signal cycle, effective grayscale clock signal number of cycles is Lighth+Lightl=53*233+11*232=14901, and the dutycycle Duty2=14901/65536 of its representative, meets Duty2=Duty1.
Step S2: synchro control card sends grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to driving chip.
Step S3: the precision that driving chip exports at the rising edge of data clock signal and/or the driving chip of negative edge sample-synchronous control card or upper level connection is the gradation data of n2.
In the embodiment of the present invention one, the precision that driving chip can export at the driving chip of the rising edge of data clock signal or negative edge sample-synchronous control card or upper level connection is the gradation data of n2, and the precision that also can export at the driving chip of the rising edge of data clock signal and the equal sample-synchronous control card of negative edge or upper level connection is the gradation data of n2.
Step S4: the gradation data that the port latch instruction that driving chip sends in conjunction with synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous.
Due in actual applications, the number optimum of the driving chip of cascade is 12, the port number of each driving chip is generally 16, if driving chip is more than 12, can cause the waste of resource, therefore, in the embodiment of the present invention one, in order to transfer the gradation data of corresponding number within the grayscale clock signal cycle, need, n2 is preferably 10, while being improved to make refresh rate, there is optimum cascade driving chip number.Certainly, in particular situations, n2 gets 9 or 11.
Further, in the embodiment of the present invention one, as shown in Figure 4, step S4 can comprise again:
Step S41: driving chip, according to counting instruction, counts grayscale clock signal.
Step S42: driving chip according to port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual grayscale clock signal cycle composition, to sampling, the one group gradation data corresponding with the light-emitting component of corresponding port obtained latches, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to overall latch instruction, entirety is carried out to each group of gradation data and latches.
Step S43: driving chip generates original gradation conditioning signal according to overall latch instruction.
Step S44: each group of gradation data of original gradation conditioning signal and latch compares by driving chip respectively, obtains each group of gradation data pulse width modulating signal corresponding respectively and exports, to drive each light-emitting component luminous.
The display control method of the support gray shade scale expansion that the embodiment of the present invention one proposes is in synchro control card, the gradation data to be shown that each display precision is n1 is processed, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and have n2≤n1 and n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.By the method, the volume of transmitted data between synchro control card and driving chip is n2 position from existing 16 potential drops, and therefore, the message transmission rate between synchro control card and driving chip improves 16/n2 doubly.And if further, the precision that driving chip exports at the rising edge of data clock signal and the driving chip of the equal sample-synchronous control card of negative edge or upper level connection is the gradation data of n2, then relative to existing clock sampling mode, message transmission rate between synchro control card and driving chip can be promoted 2 times further, that is to say, optimum can promote message transmission rate 16/n2*2 doubly.Thus in terms of existing technologies, improve the upper frequency limit of grayscale clock signal GCLK, further increase row frequency sweep rate, and then improve the refresh rate of picture.For example, suppose that the frequency of maximum data clock signal DCLK and the frequency of maximum grayscale clock signal GCLK are 30MHz, the driving chip number of cascade is 12, every sheet driving chip has 16 to drive port, display precision is 10, then within 1024 grayscale clock cycles (i.e. a display cycle), the volume of transmitted data between synchro control card and driving chip is: the driving port number 16=1920 of gradation data figure place 10 × driving chip number 12 × each driving chip.Driving chip is the gradation data of 10 at the rising edge of data clock signal and the equal sampling precision of negative edge, the data clock signal number of cycles then needed is 1920/2=960, because 960 are less than grayscale clock number of cycles 1024, therefore the upper frequency limit of grayscale clock signal GCLK can reach maximal value 30MHz, for 8 scanning dynamic screen, row frequency sweep rate can reach:
relative to existing 1.2KHz, refresh rate gets a promotion, and improves user experience.
embodiment two
The embodiment of the present invention two proposes a kind of gradation data output intent, as shown in Figure 5, comprising:
Step S5: the gradation data to be shown that each display precision is n1 is processed, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip.
Wherein, n1 and n2 is positive integer, and n2≤n1, n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.
Further, as shown in Figure 6, step S5 comprises again:
Step S51: the magnitude relationship between the display precision n1 of more current gradation data to be shown and display precision n2.
Step S52: according to the comparative result of step S51, if display precision n1 equals display precision n2, then directly exports to driving chip by current gradation data to be shown.
Step S53: according to the comparative result of step S51, if display precision n1 is greater than display precision n2, then extracts the low n1-n2 bit data D1 in current gradation data to be shown, and calculates decimal data K corresponding to data D1.
Step S54: according to the comparative result of step S51, if display precision n1 is greater than display precision n2, extracts the high n2 bit data D2 in current gradation data to be shown.
Step S55: judging whether everybody is 1 to data D2, is perform step S58, otherwise perform step S56.
Step S56: data D2 is added 1, obtains data D3.
Step S57: by K data D3, and 2
n1-n2-K data D2 Serial output is to driving chip.
Step S58: by 2
n1-n2individual data D2 Serial output is to driving chip.
Step S6: send grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to driving chip.
embodiment three
The embodiment of the present invention three proposes a kind of driving method, as shown in Figure 7, comprising:
Step S7: the precision exported at the rising edge of data clock signal and/or the driving chip of negative edge sample-synchronous control card or upper level connection is the gradation data of n2, and wherein, n2 is positive integer, and n2 < 16.
Step S8: the gradation data obtained in conjunction with the port latch instruction of synchro control card transmission, overall latch instruction, counting instruction, grayscale clock signal and sampling, drives each light-emitting component luminous.
Further, as shown in Figure 8, step S8 comprises again:
Step S81: according to counting instruction, grayscale clock signal is counted.
Step S82: according to port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual grayscale clock signal cycle composition, to sampling, the one group gradation data corresponding with the light-emitting component of corresponding port obtained latches, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to overall latch instruction, entirety is carried out to each group of gradation data and latches.
Step S83: generate original gradation conditioning signal according to overall latch instruction.
Step S84: compared respectively by each group of gradation data of original gradation conditioning signal and latch, obtains each group of gradation data pulse width modulating signal corresponding respectively and exports, to drive each light-emitting component luminous.
embodiment four
The embodiment of the present invention four proposes a kind of synchro control card, as shown in Figure 9, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention four.
Specifically, the synchro control card that the embodiment of the present invention four proposes comprises: data processing module 11, for being that the gradation data to be shown of n1 processes to each display precision, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip; Transport module 12, for sending grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to driving chip.
Wherein, n1 and n2 is positive integer, and n2≤n1, n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.
Further, as shown in Figure 10, data processing module 11 can comprise: comparison sub-module 111, for the magnitude relationship between the display precision n1 of more current gradation data to be shown and display precision n2; First output sub-module 112, for the comparative result according to comparison sub-module 111, if display precision n1 equals display precision n2, then directly exports to driving chip by current gradation data to be shown; First calculating sub module 113, for the comparative result according to step comparison sub-module 111, if display precision n1 is greater than display precision n2, then extracts the low n1-n2 bit data D1 in current gradation data to be shown, and calculates decimal data K corresponding to data D1; Extract submodule 114, for the comparative result according to comparison sub-module 111, if display precision n1 is greater than display precision n2, extract the high n2 bit data D2 in current gradation data to be shown; Judge submodule 115, for judging whether everybody is 1 to data D2; Second calculating sub module 116, for when judge that submodule 115 judges data D2 everybody be not 1 full time, data D2 is added 1, obtains data D3; Second output sub-module 117, for by K data D3, and 2
n1-n2-K data D2 Serial output is to driving chip; 3rd output sub-module 118, for when everybody judging that submodule 115 judges data D2 is 1, by 2
n1-n2individual data D2 Serial output is to driving chip.
embodiment five
The embodiment of the present invention five proposes a kind of driving chip, as shown in figure 11, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention five.
Specifically, the driving chip that the embodiment of the present invention five proposes comprises: sampling module 21, precision for exporting at the rising edge of data clock signal and/or the driving chip of negative edge sample-synchronous control card or upper level connection is the gradation data of n2, wherein, n2 is positive integer, and n2 < 16; Driver module 22, for the gradation data that the port latch instruction sent in conjunction with synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous.
Further, as Figure 12 shows a kind of circuit of the driving chip that the embodiment of the present invention five provides.Now, driving chip comprises data clock interface DCLK', serial date transfer interface SDI', grayscale clock interface GCLK', latch interface LE', serial data output interface SDO' and output that at least one connects light-emitting component respectively drives interface OUT, and this light-emitting component is preferably light emitting diode.Wherein, data clock interface DCLK', serial date transfer interface SDI', grayscale clock interface GCLK', latch interface LE' connect synchro control card respectively, and serial data output interface SDO' connects the serial date transfer interface SDI' of next stage driving chip.Sampling module 21 comprises: trigger along processing unit 212, for being received the data clock signal that synchro control card sends by data clock interface DCLK', and exports monostable pulses at the rising edge of data clock signal and/or negative edge.Driver module 22 comprises: n2 bit shift buffer 211, is the gradation data of n2 for the precision exported according to the driving chip triggering monostable pulses sample-synchronous control card or the upper level connection exported along processing unit 212; Instruction control unit 221, for the port latch instruction sent by latch interface LE' reception synchro control card, overall latch instruction and counting instruction; N2 digit counter 222, for being received the grayscale clock signal that synchro control card sends by grayscale clock interface GCLK', and according to counting instruction, is counted grayscale clock signal; At least one gradation data storage unit 223, for according to port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual grayscale clock signal cycle composition, the n2 bit shift buffer 211 one group gradation data corresponding with the light-emitting component of corresponding port obtained of sampling is latched, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to overall latch instruction, entirety is carried out to each group of gradation data and latches; Pwm controller 224, for generating original gradation conditioning signal according to overall latch instruction; At least one comparer 225 connected one to one with gradation data storage unit 223 respectively, the each group of gradation data latched for the original gradation conditioning signal that generated by Pwm controller 224 and gradation data storage unit 223 compares respectively, obtain each group of gradation data pulse width modulating signal corresponding respectively and export, to drive each light-emitting component luminous.
Further, as n2=10, as shown in figure 13, trigger and can comprise along processing unit 212: the input end connection data clock interface DCLK' of the first delay circuit 2121, first delay circuit 2121; The XOR gate XOR of two inputs, an input pin of XOR gate XOR connects the output terminal of the first delay circuit 2121, and the output pin of another input pin connection data clock interface DCLK' of XOR gate XOR, XOR gate XOR connects n2 bit shift buffer 211.
Wherein, the first delay circuit 2121, for generation of time delay, when each rising edge/negative edge action of data clock DCLK', all produces time delay.Data clock DCLK' is after the first delay circuit 2121, and relative data clock DCLK' is itself, only variant when rising edge/negative edge, and therefore, DCLK'_2 exports high impulse when data clock DCLK' rising edge/negative edge, and all the other times are 0.
Further, as n2=10, as shown in figure 14, n2 bit shift buffer 211 can comprise: 10 D flip-flop DFF be connected in series, and exports after converting the serial data inputted via serial date transfer interface SDI' to parallel data.Wherein, the data-out pin D of first D flip-flop DFF connects serial date transfer interface SDI', and the clock pins CLK of 10 D flip-flop DFF connects the output pin of XOR gate XOR jointly.
Further, as n2=10, as shown in figure 15, n2 digit counter 222 can comprise: 10 D flip-flop DFF1 be connected in series, 10 totalizer FA be connected in series, the data-out pin D of each D flip-flop DFF1 connects corresponding one totalizer FA's and output pin, and the clock pins CLK of 10 D flip-flop DFF1 be connected in series connects grayscale clock interface GCLK' jointly.N2 digit counter 222 is for counting the grayscale clock inputted via grayscale clock interface GCLK'.Its Q9 ~ Q0 was changed to and successively adds 1 in units of 1 grayscale clock GCLK' cycle.For example Q9 ~ Q0 change is expressed as with 16 systems: 000 → 001 → 002 →... ... 3FE → 3FF → 000.
Further, as n2=10, as shown in figure 16, Pwm controller 224 can comprise: 9 and door AND, 1 impact damper BUF, 7 rejection gate NOR, 1 not gate INV; 8 are divided other first input end to be connected n2 digit counter 222,8 with door AND to divide other second input end to connect the output pin of corresponding rejection gate NOR with door AND; 1 output terminal being connected n2 digit counter 222,1 with the first input end of door AND and being connected not gate INV with second input end of door AND, the input end of not gate INV is connected n2 digit counter 222 jointly with the input end of impact damper BUF; 9 are connected comparer 225 jointly with the output terminal of door AND and the output terminal of impact damper BUF.Pwm controller 224 Pwm controller 224, for processing the output of n2 digit counter 222, is convenient to the comparison of comparer 225.
Further, as n2=10, as shown in figure 17, comparer 225 can comprise: 10 and door AND1 and 1 or an OR.10 are divided other first input end to be connected gradation data storage unit 223 with door AND1,10 are divided other second input end to be connected Pwm controller 224 with door AND1,10 are divided other output terminal to be connected with door AND1 or the input end of door OR, or the output terminal OUT of door OR drives interface OUT as output.Comparer 225, for the output of the output of gradation data storage unit 223 and Pwm controller 224 being compared, obtains the dutycycle corresponding with gradation data.What deserves to be explained is, Pwm controller 224 and the realization of comparer 225, can change because of the PWM mode of OUT output.
Further, as n2=10, as shown in figure 18, instruction control unit 221 can comprise: the totalizer FA1 of 4 series connection, the D flip-flop DFF2 of 4 series connection, D flip-flop DFF3, D flip-flop DFF4, the second delay circuit 2211 and the 3rd delay circuit 2212, not gate U1 and not gate U2.Wherein, the data-out pin D being connected 1 corresponding D flip-flop DFF2 with output pin S of each totalizer FA1; The reset pin RST of D flip-flop DFF2 all connects latch interface LE', and the clock pins CLK of D flip-flop DFF2 all connects the output pin DCLK'_2 of XOR gate XOR; The data-out pin D of D flip-flop DFF3 connects the data output pins Q3 of last D flip-flop DFF2 in the D flip-flop DFF2 of 4 series connection, the clock pins CLK of D flip-flop DFF3 connects the output terminal of not gate U1, the input end of not gate U1 connects latch interface LE', and the data output pins Q of D flip-flop DFF3 connects the reset pin RST of D flip-flop DFF3 by the second delay circuit 2211; The data-out pin D of D flip-flop DFF4 connects the data output pins Q3 of last D flip-flop DFF2 in the D flip-flop DFF2 of 4 series connection, the clock pins CLK of D flip-flop DFF4 connects the output terminal of not gate U2, the input end of not gate U2 connects latch interface LE', and the data output pins Q of D flip-flop DFF4 connects the reset pin RST of D flip-flop DFF4 by the 3rd delay circuit 2212.
Instruction control unit 221, for the rising of data clock DCLK' in the high level time latching interface LE' and/or negative edge counting, according to count results, obtains corresponding instruction.Being the latches data (latchi) of OUT port and overall latching (latch_global) of this circuit realiration, is respectively used to store the data of certain port, latches all of the port data.
Further, as n2=10, as shown in figure 19, gradation data storage unit 223 can comprise: the latch LATCH1 of 10 series connection, the latch LATCH of 10 series connection.The clock pins CLK of each latch LATCH1 connects the data output pins Q of D flip-flop DFF3 jointly, the clock pins CLK of each latch LATCH connects the data output pins Q of D flip-flop DFF4 jointly, and the data output pins Q of each latch LATCH1 connects the data-out pin D of corresponding 1 latch LATCH.Gradation data storage unit 223, for by the gradation data in n2 bit shift buffer 211, is latched into corresponding port.Latchi corresponds to the latches data of OUTi port, and latch_global is the data latch clock of all of the port.
embodiment six
The embodiment of the present invention six proposes a kind of display control program supporting gray shade scale to expand, and comprises the synchro control card as above described in embodiment four and the driving chip described in embodiment five.
In sum, display control method and the system of the support gray shade scale expansion that the present invention proposes are in synchro control card, the gradation data to be shown that each display precision is n1 is processed, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and have n2≤n1 and n2 < 16, simultaneously 2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical.By the method, the volume of transmitted data between synchro control card and driving chip is n2 position from existing 16 potential drops, and therefore, the message transmission rate between synchro control card and driving chip improves 16/n2 doubly.And if further, the precision that driving chip exports at the rising edge of data clock signal and the driving chip of the equal sample-synchronous control card of negative edge or upper level connection is the gradation data of n2, then relative to existing clock sampling mode, message transmission rate between synchro control card and driving chip can be promoted 2 times further, that is to say, optimum can promote message transmission rate 16/n2*2 doubly.Thus in terms of existing technologies, improve the upper frequency limit of grayscale clock signal GCLK, further increase row frequency sweep rate, and then improve the refresh rate of picture.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. support to it is characterized in that the display control method that gray shade scale is expanded, said method comprising the steps of:
Synchro control card processes the gradation data to be shown that each display precision is n1, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip, described n1 and n2 is positive integer, and n2≤n1, n2 < 16,2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical;
Described synchro control card sends grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to described driving chip;
The precision that the driving chip that described driving chip samples described synchro control card or upper level connection at rising edge and/or the negative edge of described data clock signal exports is the gradation data of n2;
The gradation data that the described port latch instruction that described driving chip sends in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous.
2. the display control method supporting gray shade scale expansion as claimed in claim 1, it is characterized in that, described synchro control card processes the gradation data to be shown that each display precision is n1, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and the gradation data Serial output each group display precision being respectively n2 is further comprising the steps to the step of driving chip:
Magnitude relationship between the display precision n1 of the gradation data to be shown that described synchro control card is more current and display precision n2;
If described display precision n1 equals described display precision n2, then described current gradation data to be shown is directly exported to described driving chip by described synchro control card;
If described display precision n1 is greater than described display precision n2, then described synchro control card extracts the low n1-n2 bit data D1 in described current gradation data to be shown, and calculates decimal data K corresponding to described data D1;
If described display precision n1 is greater than described display precision n2, then described synchro control card extracts the high n2 bit data D2 in described current gradation data to be shown;
Described synchro control card judges whether everybody is 1 to described data D2, is then by 2
n1-n2individual described data D2 Serial output gives described driving chip, otherwise described data D2 is added 1, obtains data D3, and by K described data D3 and 2
n1-n2-K described data D2 Serial output gives described driving chip.
3. the display control method supporting gray shade scale expansion as claimed in claim 1, it is characterized in that, the gradation data that the described port latch instruction that described driving chip sends in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives the step of each light-emitting component luminescence further comprising the steps:
Described driving chip, according to described counting instruction, counts described grayscale clock signal;
Described driving chip according to described port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual described grayscale clock signal cycle composition, to sampling, the one group gradation data corresponding with the light-emitting component of corresponding port obtained latches, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to described overall latch instruction, entirety is carried out to each group of gradation data and latches;
Described driving chip generates original gradation conditioning signal according to described overall latch instruction;
Each group of gradation data of described original gradation conditioning signal and latch compares by described driving chip respectively, obtains each group of gradation data pulse width modulating signal corresponding respectively and exports, to drive described each light-emitting component luminous.
4. the display control method of the support gray shade scale expansion as described in any one of claims 1 to 3, it is characterized in that, described n2 is 10.
5. a synchro control card, is characterized in that, described synchro control card comprises:
Data processing module, for being that the gradation data to be shown of n1 processes to each display precision, obtain the gradation data that one group of display precision corresponding to gradation data to be shown with each is respectively n2, and each group display precision is respectively the gradation data Serial output of n2 to driving chip, described n1 and n2 is positive integer, and n2≤n1, n2 < 16,2
n1in the individual grayscale clock signal cycle, the dutycycle representated by gradation data that one group of display precision is respectively n2 and corresponding display precision are that the required dutycycle of showing of gradation data to be shown of n1 is identical;
Transport module, for sending grayscale clock signal, data clock signal, port latch instruction, overall latch instruction and counting instruction to described driving chip.
6. synchro control card as claimed in claim 5, it is characterized in that, described n2 is 10, and described data processing module comprises:
Comparison sub-module, for the magnitude relationship between the display precision n1 of more current gradation data to be shown and display precision n2;
First output sub-module, for the comparative result according to described comparison sub-module, if described display precision n1 equals described display precision n2, then directly exports to described driving chip by described current gradation data to be shown;
First calculating sub module, for the comparative result according to described comparison sub-module, if described display precision n1 is greater than described display precision n2, then extract the low n1-n2 bit data D1 in described current gradation data to be shown, and calculate decimal data K corresponding to described data D1;
Extract submodule, for the comparative result according to described comparison sub-module, if described display precision n1 is greater than described display precision n2, extract the high n2 bit data D2 in described current gradation data to be shown;
Judge submodule, for judging whether everybody is 1 to described data D2;
Second calculating sub module, for judge described data D2 when described judgement submodule everybody be not 1 full time, described data D2 is added 1, obtains data D3;
Second output sub-module, for inciting somebody to action a described data D3, and 2
n1-n2-K described data D2 Serial output gives described driving chip;
3rd output sub-module, when being 1 for everybody judging described data D2 when described judgement submodule, by 2
n1-n2individual described data D2 Serial output gives described driving chip.
7. a driving chip, is characterized in that, described driving chip comprises:
Sampling module, the precision that the driving chip of sampling described synchro control card or upper level connection for the rising edge of data clock signal that sends at synchro control card and/or negative edge exports is the gradation data of n2, described n2 is positive integer, and n2 < 16;
Driver module, for the gradation data that the port latch instruction sent in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous;
Described driving chip comprises the data clock interface, serial date transfer interface, grayscale clock interface, the latch interface that connect described synchro control card respectively, connect the serial data output interface of the serial date transfer interface of next stage driving chip, and at least one connects the output driving interface of light-emitting component respectively, described n2 is 10;
Described sampling module comprises:
Trigger along processing unit, for the data clock signal sent by synchro control card described in described data clock interface, and export monostable pulses at the rising edge of described data clock signal and/or negative edge;
N2 bit shift buffer is the gradation data of n2 for the precision exported along the driving chip that the described monostable pulses that processing unit exports samples described synchro control card or upper level connection according to described triggering;
Described driver module comprises:
Instruction control unit, for the described port latch instruction sent by synchro control card described in described latch interface, overall latch instruction and counting instruction;
N2 digit counter, for the grayscale clock signal sent by synchro control card described in described grayscale clock interface, and according to described counting instruction, is counted described grayscale clock signal;
At least one gradation data storage unit, for according to described port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual grayscale clock signal cycle composition, the described n2 bit shift buffer one group gradation data corresponding with the light-emitting component of corresponding port obtained of sampling is latched, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to described overall latch instruction, entirety is carried out to each group of gradation data and latches;
Pwm controller, for generating original gradation conditioning signal according to described overall latch instruction;
At least one comparer connected one to one with described gradation data storage unit respectively, the each group of gradation data latched for the described original gradation conditioning signal that generated by described Pwm controller and described gradation data storage unit compares respectively, obtain each group of gradation data pulse width modulating signal corresponding respectively and export, to drive each light-emitting component luminous.
8. support the display control program that gray shade scale is expanded, described system comprises the driving chip that synchro control card is connected with cascade, it is characterized in that, described synchro control card is the synchro control card as described in claim 5 or 6.
9. the display control program supporting gray shade scale expansion as claimed in claim 8, it is characterized in that, described driving chip connects data clock interface, serial date transfer interface, grayscale clock interface, the latch interface of synchro control card respectively, connect the serial data output interface of the serial date transfer interface of next stage driving chip, and at least one connects the output driving interface of light-emitting component respectively, described driving chip also comprises:
Sampling module, the precision that the driving chip of sampling described synchro control card or upper level connection for the rising edge of data clock signal that sends at synchro control card and/or negative edge exports is the gradation data of n2, and described n2 is 10;
Driver module, for the gradation data that the port latch instruction sent in conjunction with described synchro control card, overall latch instruction, counting instruction, grayscale clock signal and sampling obtain, drives each light-emitting component luminous;
Described sampling module comprises:
Trigger along processing unit, for the data clock signal sent by synchro control card described in described data clock interface, and export monostable pulses at the rising edge of described data clock signal and/or negative edge;
N2 bit shift buffer is the gradation data of n2 for the precision exported along the driving chip that the described monostable pulses that processing unit exports samples described synchro control card or upper level connection according to described triggering;
Described driver module comprises:
Instruction control unit, for the described port latch instruction sent by synchro control card described in described latch interface, overall latch instruction and counting instruction;
N2 digit counter, for the grayscale clock signal sent by synchro control card described in described grayscale clock interface, and according to described counting instruction, is counted described grayscale clock signal;
At least one gradation data storage unit, for according to described port latch instruction, 2
n1-n2individual respectively by 2
n2in the display cycle of individual grayscale clock signal cycle composition, the described n2 bit shift buffer one group gradation data corresponding with the light-emitting component of corresponding port obtained of sampling is latched, and after each group of gradation data that each light-emitting component is corresponding respectively all latches, according to described overall latch instruction, entirety is carried out to each group of gradation data and latches;
Pwm controller, for generating original gradation conditioning signal according to described overall latch instruction;
At least one comparer connected one to one with described gradation data storage unit respectively, the each group of gradation data latched for the described original gradation conditioning signal that generated by described Pwm controller and described gradation data storage unit compares respectively, obtain each group of gradation data pulse width modulating signal corresponding respectively and export, to drive each light-emitting component luminous.
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| CN107749272A (en) * | 2017-12-07 | 2018-03-02 | 大连海事大学 | A kind of gray-scale modulation methods and the image display system based on LED array |
| CN110120197B (en) * | 2019-04-11 | 2024-03-08 | 深圳天源中芯半导体有限公司 | Cascade application system capable of omitting peripheral resistance and capacitance to reduce interference and implementation method thereof |
| CN110277052B (en) * | 2019-06-13 | 2020-08-04 | 华中科技大学 | Full-color L ED driving chip with multi-row scanning high refresh rate and driving method |
| CN110996449B (en) * | 2019-11-29 | 2021-12-21 | 广州市雅江光电设备有限公司 | PWM pulse width modulation method and device |
| CN111010763B (en) * | 2019-11-29 | 2021-06-25 | 广州市雅江光电设备有限公司 | Dimming method of high-power LED constant current driving device |
| CN110996441B (en) * | 2019-11-29 | 2021-06-25 | 广州市雅江光电设备有限公司 | Dimming method of LED driving device |
| CN111161670B (en) * | 2020-03-02 | 2022-03-29 | 南京浣轩半导体有限公司 | Multi-line scanning and line changing display method and chip |
| CN113851074B (en) * | 2020-06-28 | 2023-07-28 | 深圳市明微电子股份有限公司 | LED driving pulse modulation method and device |
| CN112233615B (en) * | 2020-12-09 | 2021-03-05 | 卡莱特（深圳）云科技有限公司 | Method and device for improving display effect of LED display screen |
| CN112634821B (en) * | 2020-12-25 | 2022-05-13 | 京东方科技集团股份有限公司 | Data display method and device and readable storage medium |
| CN112799996B (en) * | 2021-02-03 | 2022-04-12 | 长沙锐逸微电子有限公司 | Chip cascade expansion control protocol |
| CN114758630B (en) | 2022-06-16 | 2022-09-09 | 惠科股份有限公司 | Backlight module, driving method thereof and display device |
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